TWI412230B - Register circuit - Google Patents

Abstract

A register circuit is provided in the application. The register circuit includes a plurality of circuit units which are serially connected to each other and used to sore and transmit a serial data. When the serial data is driving (image) data of light emitting diodes, the outputs of the circuit units are maintained to have the same logical level after the circuit units store corresponding driving data. When the serial data is the mode transformation signal, the circuit units transmit the received mode transformation signal. Because each output of the circuit units has the same logical level, so the transmission of the mode transformation signal would not be affected even if the switching timings of each circuit units are slightly inaccurate.

Description

Temporary circuit

The present invention relates to a temporary storage circuit, and more particularly to a temporary storage circuit for a light emitting diode driving device.

A light-emitting diode array or display is formed by a plurality of light-emitting diodes, and the pins of a single drive circuit are generally insufficient to drive the entire display. The driving circuit is usually formed by connecting a plurality of wafers in series, and each driving chip is responsible for driving a plurality of or a whole row of light emitting diodes. The operating mode (eg, driving or detecting) of the driving chip can be set by a plurality of control signals, but excessive control signals may cause an increase in circuit layout complexity. In addition, the wire required for long-distance serial connection will also greatly increase the system manufacturing cost, and all kinds of restrictions are severely popularized by the system.

Therefore, if the serial data received by the driving chip is directly used to switch the mode, the complexity of the circuit layout can be reduced, and the burden on the system can be reduced. However, when the mode switching signal is replaced by the waveform combination of the serial data and the clock signal, a switchable signal transmission mode must be set in the driving chip to respectively transmit the driving data and the mode switching signal in the serial data to switch in the transfer mode. At the time of signal, the mode switching signal in the serial data is simultaneously transmitted to all the serially connected driving chips to perform mode switching in synchronization. However, if the switchable signal transmission mode is not synchronized, the signal received by the next stage driving chip may be erroneously caused by the mode switching signal.

The invention provides a temporary storage circuit for transmitting driving data and mode switching signals of a light-emitting diode in a manner of a plurality of circuit unit series. In the case of the scratchpad of the light-emitting diode driving data, the individual circuit unit cooperates with the driving data to store the corresponding driving data, and the driving data thereof causes the last storage unit of the shift register in each circuit unit ( Bits) are all the same logic level (eg logic low or logic high). Therefore, when the temporary storage circuit is transmitting the mode switching signal, the output of each stage circuit unit will be at the same logic low level or high level at the beginning, so even if the switching timing of each stage circuit unit has slight error, it will not affect the mode. Switch the signal transmission.

The present invention further provides a temporary storage circuit that utilizes a multiplexer having three inputs for switching, wherein one input is coupled to a fixed logic level (eg, a logic high or a logic low). When the serial data received by the temporary storage circuit is converted from the driving data to the mode switching signal, each circuit unit in the temporary storage circuit first switches the output to the above fixed logic level, and then switches to the input end of the mode switching signal. . Thereby, the misjudgment of the mode switching signal caused by the slight switching error of the switching timing of each circuit unit can be avoided, and the transmission of the mode switching signal is not affected.

The invention further provides a temporary storage circuit for directly controlling the switching of the multiplexer by using the latch signal received by the LED to drive the wafer, thereby avoiding the problem of inconsistent timing in the individual circuit units.

In view of the above, the present invention provides a temporary storage circuit comprising a plurality of circuit units connected in series with each other and coupled to a clock signal, wherein one of the circuit units receives a series of data and clock signals The first circuit unit includes a data input terminal, a data output terminal, a shift register, a multiplexer and a selection unit. The data input end is configured to receive the serial data. The shift register has a plurality of storage elements connected in series, and the shift register is coupled to the data input end and transmits the serial data according to the clock signal. The multiplexer has a first input end and a second input end. The first input end is coupled to the data input end, the second input end is coupled to the output of the shift register, and the output end of the multiplexer is coupled to the output end. The data output end, and the multiplexer selects the signal received by the first input terminal or the second input terminal as the output of the multiplexer according to a selection signal. The selection unit is coupled to the selection end of the multiplexer and generates a selection signal according to the data mode of the serial data.

The serial data has a first data mode and a second data mode. When the serial data is in the first data mode, the data corresponding to the last storage component in the shift register in each circuit unit is For the same logic level (logic high or logic low) and the multiplexer selects the signal received by the second input as the output; when the serial data is converted to the second data mode, the multiplexer selects according to the selection signal The signal received at the first input acts as an output.

In an embodiment of the present invention, the circuit of each of the circuit units is the same as the first circuit unit, and each of the circuit units is connected to the data input end of the next-stage circuit unit via the data output end to be connected in series with each other. The drive data of the received serial data is transmitted in sequence.

In an embodiment of the invention, the circuit unit is a light emitting diode driving circuit.

In an embodiment of the invention, when the serial data is in the first data mode, the serial data includes a plurality of LED driving data, and each of the LED driving data is in the shift register. The data corresponding to the last storage element are all of the same logic level; when the serial data is converted into the second data mode, the serial data is transmitted with a mode switching signal and the clock signal is maintained at a fixed level, wherein the mode is switched. The signal includes a plurality of pulse signals.

In an embodiment of the invention, when the selecting unit detects that the clock signal is maintained at a fixed level for more than a predetermined time (ie, a length of time), the selecting unit adjusts the selection signal to cause the multiplexer to select the first input. The signal received by the terminal acts as an output.

In an embodiment of the invention, the selection unit includes an oscillation circuit and a counter.

The present invention further provides a temporary storage circuit, which may be composed of a single circuit unit or a plurality of circuit units connected in series. One of the circuit units receives a clock signal and a serial data, and the serial data includes a first data pattern and a second data pattern. The first circuit unit includes a data input terminal, a data output terminal, a shift register, a multiplexer and a selection unit. The data input end is configured to receive the serial data, the shift register has K storage elements connected in series (K is a positive integer), and the shift register is coupled to the data input end and according to the clock Signaling the above listed data. In the temporary storage circuit, the multiplexer has three input ends, which are a first input end, a second input end, and a third input end, wherein the first input end is coupled to the data input end, and the second input end is The third input end is coupled to the output of the shift register, and the output end of the multiplexer is coupled to the data output end, and is coupled to a fixed logic level (logic high or logic low) And the multiplexer selects a signal received by one of the first input terminal, the second input terminal and the third input terminal as an output of the multiplexer according to a selection signal. The selection unit is coupled to the selection end of the multiplexer, and generates the selection signal according to the data pattern of the serial data.

The serial data has a first data mode and a second data mode. When the serial data is the first data mode, the multiplexer selects a signal received by the third input as an output; When the serial data is converted into the second data mode, the clock signal is maintained at a fixed level, and the multiplexer first selects the signal received by the second input as an output according to the selection signal and maintains a preset. Time, and then select the signal received by the above first input as an output.

The invention further provides a temporary storage circuit, which is suitable for a light-emitting diode driving circuit, and the LED driving circuit receives a latch signal to latch the serial data, and the temporary storage circuit comprises a first circuit unit. The first circuit unit receives a series of data and a clock signal, the serial data has a first data mode and a second data mode, wherein the first circuit unit comprises a data input end, a data output end, and a shift Bit register and a multiplexer. The shift register has K storage elements connected in series (K is a positive integer), and the shift register is coupled to the data input terminal and transmits the serial data according to the clock signal. The multiplexer has a first input end coupled to the data input end, the second input end coupled to the output of the shift register, the multiplexer The output end is coupled to the data output end, and the multiplexer selects a signal received by the first input end or the second input end as an output of the multiplexer according to the latch signal.

Wherein, when the serial data is the first data mode, the multiplexer selects a signal received by the second input as an output; and when the serial data is converted into the second data mode, the multiplexer The signal received by the first input terminal is selected as an output according to the latch signal.

The invention further provides a temporary storage circuit comprising a data input terminal, a data output terminal, a shift register, a multiplexer and a selection unit. The data input end is configured to receive the serial data, the shift register has M storage elements connected in series, the shift register is coupled to the data input end and transmits the serial data according to a clock signal, and M is positive Integer. The multiplexer has a first input end and a second input end. The first input end is coupled to the data input end, the second input end is coupled to the output of the shift register, and the output end of the multiplexer is coupled to the output end. The data output end, and the multiplexer selects the signal received by the first input terminal or the second input terminal as the output of the multiplexer according to a selection signal. The selection unit is coupled to the selection end of the multiplexer for generating a selection signal.

The serial data has a first data mode and a second data mode. When the serial data is the first data mode, the serial data includes a plurality of driving data, and each of the driving data is M bits and the last one of them A valid bit is the same, so that after the transfer of each driver data is completed, the data corresponding to the last storage element is the same logic level and the multiplexer selects the signal received by the second input. As an output; when the serial data is converted into the second data mode, the multiplexer selects the signal received by the first input as the output according to the selection signal.

Based on the above, the present invention proposes several circuit architectures for solving the problem of signal transmission errors caused by inconsistent circuit switching. When the serial data received by the temporary storage circuit is converted into a mode switching signal by the driving data, the output of each circuit unit is first converted to the same logic level to avoid a signal transmission error of the circuit unit of the next stage.

The above described features and advantages of the present invention will be more apparent from the following description.

First embodiment

Please refer to FIG. 1. FIG. 1 is a temporary storage circuit according to a first embodiment of the present invention. The temporary storage circuit 100 is formed by a plurality of circuit units 110-140 connected in series, and the circuit structures of the respective circuit units 110-140 are the same. The circuit unit 110 includes a multiplexer 112, a shift register 114 and a selection unit 116. The shift register 114 is coupled to the data input end of the circuit unit 110 and the second input end of the multiplexer 112 ("0 The first input end ("1" end) of the multiplexer 112 is directly coupled to the data input end of the circuit unit 110, and the selection unit 116 is coupled to the selection end of the multiplexer 112 to provide a selection. Signal SEL1 through multiplexer 112 selects the signal received by the first input or the second input as its output signal. The circuit units 120, 130 and 140 are respectively composed of multiplexers 122, 132 and 142, shift registers 124, 134 and 144, and selection units 126, 136 and 146, and the selection units 126, 136 and 146 respectively output SEL2. SEL3 and SEL4 to multiplexers 122, 132 and 142, the remaining circuit structures are the same as circuit unit 110, and will not be described again.

The circuit units 110, 120, 130 and 140 are connected end to end and connected in series. The data output end of the first stage circuit unit (such as 110) is coupled to the data input end of the next level circuit unit (such as 120), and the The data input end of the primary circuit unit 110 is coupled to the serial data DIN, and the output signal is represented by the output signal DO1, and the output signals of the remaining stages of the circuit units 120, 130 and 140 are represented by DO2, DO3, and DO4. The circuit units 110-140 are further coupled to the clock signal CLK, and perform data shifting and storage according to the clock signal CLK.

The serial data DIN has two data modes, a first data mode and a second data mode. The first data mode is the driving data of the LED, and the second data mode is the mode switching signal. When the serial data DIN is the first data mode, it includes the driving data of the plurality of LEDs, and the multiplexers 112-142 switch to the second input terminal (“0” terminal). When the serial data DIN is the second data mode, the multiplexers 112-142 switch to the first input ("1" terminal). Taking the circuit unit 110 as an example, when the serial data DIN is in the first data mode, the multiplexer 112 selects the signal received by the second input (ie, the output of the shift register 114) as an output, and the remaining circuit units The multiplexers 122-142 in 120~140 also select the signal received by the second input as an output. The serial data DIN is transferred by the shift registers 114-144 and the driving data of the light-emitting diodes are stored in the shift registers 114-144, respectively.

The data format in the serial data DIN is matched with the bit length of the shift register 114, so that the data corresponding to the last one of the shift registers 114-144 in each of the circuit units 110-140 is The same logic level (for example, logic high or logic low). Taking the logic low potential as an example, as shown in FIG. 1, the last storage element (bit) of the shift registers 114-144 is at a logic low level in the "L" table.

Therefore, if the shift registers 114-144 are M-bit shift registers, it means that there are M storage elements connected in series, and M is a positive integer. The driving data in the serial data DIN is also M bits, and the last bit of each driving data is fixed to a logic low level, represented by "0" or "L". Thus, when the serial data DIN is transferred to the shift registers 114-144, the last bit of the shift registers 114-144 will remain at a logic low level, at which time the multiplexers 112-142 The output will also remain at a logic low.

Therefore, when the serial data DIN is converted into the second data mode, even if the circuit unit 120 and the circuit unit 110 cannot simultaneously switch the channels of the multiplexers 112, 122, the circuit unit 120 does not receive the erroneous mode switching signal. Because even if the multiplexer 122 switches to the first input faster than the multiplexer 112, the circuit unit 120 receives a logic low signal at the beginning of the switching, and does not generate an erroneous pulse signal. The circuit units 130 and 140 are the same as the circuit unit 120. Since the output of the previous stage circuit unit (for example, the output signals DO2 and DO3) is still at a logic low level at the time of switching, the circuit unit switching timing of the back end is faster and does not occur. Wrong pulse.

It should be noted that, in this embodiment, when the serial data DIN is converted into the second data mode, the clock signal CLK is matched to maintain a fixed level (for example, a logic high level or a logic low level). The switching timing of the circuit units 110-140 is mainly determined by the selecting units 116-146. The selecting units 116-146 select the signals SEL1~SEL4 according to the data pattern of the serial data DIN. Since the clock signal CLK waveform is in this embodiment. The data mode of the serial data DIN is changed. Therefore, the selection units 116-146 can generate the selection signals SEL1 to SEL4 according to the change of the clock signal CLK, for example, when the detection of the clock signal CLK is maintained at a high level exceeding a preset. The switching is performed at a preset time, but the embodiment is not limited thereto. When the selecting units 116-146 detect that the clock signal CLK is maintained at a fixed level for more than a preset time, the channels of the multiplexers 112-142 are switched to the first input terminal, and all the circuit units 110 connected in series are connected. ~140 can synchronously receive the mode switching signal to switch the driving mode.

Next, please refer to FIG. 2. FIG. 2 is a signal waveform diagram according to the first embodiment of the present invention. In this embodiment, the serial data DIN is converted into a mode switching signal, and the signal is composed of the pulse signal MS, and the clock signal CLK is matched to maintain a logic high level to inform the circuit unit 110~140 that the serial data DIN has been converted. To the second data mode. After time T1, the clock signal CLK is maintained at a logic high level, and the selection units 116-146 switch the channels of the multiplexers 112-142 to the first input after counting a predetermined time. Since the frequencies of the oscillators for counting time in the selection units 116-146 may not be completely identical, the order of the counting times of the actual switching levels of the selection signals SEL1 to SEL4 is assumed to be Tmode1>Tmode2>Tmode3>Tmode4. Taking the circuit units 110 and 120 as an example, although the selection unit 126 of the back end switches at a faster speed, since the output signal DO1 of the front end circuit unit 110 is still at a logic low level, the output signal DO2 is maintained after the SEL2 is switched to a logic high level. The logic is low until the pulse signal MS is received. The output signals DO3 and DO4 are the same. Even if the circuit unit switching speed of the back end is fast, the output signals DO3 and DO4 do not generate an erroneous pulse signal.

As is clear from FIG. 2, the waveforms of the output signals DO1, DO2, DO3, and DO4 faithfully reflect the pulse signal MS of the serial signal DIN. Even if the timings of the selection signals SEL1 to SEL4 do not coincide, the waveforms after the time T1 coincide. Therefore, by the technical means of the embodiment, the problem of data transmission errors caused by the inconsistent timing of the different circuit units 110-140 can be solved. In addition, it should be noted that the circuit units 110-140 in the temporary storage circuit 100 are not limited to four, and may be configured according to the number of serial connections required, or may be composed of one circuit unit. This embodiment does not Limited. The circuit units 110-140 are, for example, independent circuit components or driving chips of the light emitting diodes, wherein the circuit structure of the selecting unit, the multiplexer and the shift register can be integrated in the driving die of the light emitting diode to transmit Drive data with stored light-emitting diodes.

Similarly, if the data corresponding to the last storage element (114, 124, 134, 144) of the shift registers 114-144 in each of the circuit units 110-140 is logic high, the same may be used. Technical effect. When the data corresponding to the last storage element in the circuit units 110-140 is logic high, the outputs of the multiplexers 112-142 are maintained at a logic high level, so even if the multiplexers 112-142 do not simultaneously switch to the first At an input ("1" terminal), its output signals DO1, DO2, DO3, DO4 are also maintained at a logic high level until a pulse signal MS is generated. As long as the output signals DO1, DO2, DO3, and DO4 are maintained at the same level before the pulse signal MS is generated, the system can easily know the waveform change of the pulse signal MS. Moreover, even if the timings of the selection signals SEL1 to SEL4 do not coincide, the waveforms of the output signals DO1, DO2, DO3, and DO4 will coincide after the time T1. Thereby, the problem that the waveforms of the output signals DO1, DO2, DO3, and DO4 are inconsistent due to the timing inconsistency of the selection signals SEL1 to SEL4 can be overcome.

Second embodiment

It can be inferred from the above-described first embodiment that the mode switching signal in the serial data DIN can be correctly transmitted as long as the data stored in the last storage element of the shift register is maintained at a logic low level. Therefore, in the first embodiment, the data format in the serial data DIN will be directly used, and the last bit of the shift registers 114-144 is logic low to maintain the output of the multiplexers 112-142. Logic is low. However, such a method may sacrifice the resolution of the original data, such as reducing the 8-bit to 7-bit and using the last remaining bit to implement the logic low. Therefore, from another point of view, the present invention can also implement a technical means of the first embodiment by adding a bit storage element to the shift register, for example, a 9-bit shift register. To store 8-bit drive data with a logic low of 1 bit.

Please refer to FIG. 3. FIG. 3 is a temporary storage circuit according to a second embodiment of the present invention. The temporary storage circuit 200 includes circuit units 210-240, and the circuit units 210-240 are respectively multiplexers 212-242 and shift registers. 214~244 are composed of selection units 216~246, and the circuit structure thereof is similar to that of FIG. 1 above, and will not be described here. The main difference between FIG. 3 and FIG. 1 is that the shift registers 214-244 respectively have one more storage bit (ie, 201, 202, 203, 204) than the shift registers 114-144, so that the shift register 214 is shifted. ~244 is the M+1 bit shift register. After the serial data DIN transfers the corresponding data to the shift registers 214-244, the last one of the shift registers 214-244 (ie, 201, 202, 203, 204) is maintained. The logic is low, and the output of the multiplexers 212~242 will remain at a logic low. Since the shift registers 214~244 respectively add a storage element 201, 202, 203, 204, the serial data DIN also cooperates with the adjustment of the data format, and the driving data in each unit (light emitting diode) Add a new bit in the bit and set this bit to a logic low.

4 is a waveform diagram of a second embodiment of the present invention. Since the last bit in the shift registers 214-244 remains at a logic low level when the drive data is stored, the waveform of FIG. 4 and FIG. 2 Similarly, the output signals DO1 to DO4 do not generate an erroneous signal waveform due to the timing of the selection signals SEL1 to SE4.

Similarly, the serial data DIN can also be composed of the M bit drive data and a bit logic high potential, so that the last one of the shift registers 214~244 can be stored (ie, 201, 202). 203, 204) are all logic high after storing the corresponding driver data. Therefore, the outputs of the multiplexers 212, 222, 232, and 242 are maintained at a logic high level. In this case, as in the above-described first embodiment, even if the timings of the selection signals SEL1 to SEL4 are inconsistent, at time T1 After that, the waveforms of the output signals DO1, DO2, DO3, and DO4 will be the same. Thereby, the problem that the waveforms of the output signals DO1, DO2, DO3, and DO4 are inconsistent due to the selection signals SEL1 to SEL4 can be overcome.

Third embodiment

Please refer to FIG. 5. FIG. 5 is a temporary storage circuit according to a third embodiment of the present invention. The temporary storage circuit 500 includes circuit units 510-540, and the circuit units 510-540 are respectively multiplexers 512-542 and shift registers. 514~544 is composed of selection units 516~546, and its circuit structure is similar to that of FIG. 1 above, and will not be described here. The main difference between FIG. 5 and FIG. 1 is that the multiplexers 512-542 have multiplexers 512-542 having three inputs. Taking the circuit unit 510 as an example, the multiplexer 512 has a first input end, a second input end and a third input end. The first input end is coupled to the data input end to receive the serial data DIN, the second input. The terminal is coupled to a logic low potential L. The third input terminal is coupled to the output of the shift register 514. The output of the multiplexer 512 is coupled to the data output terminal to generate the output signal DO1. The multiplexer 512 selects a signal received by one of the first input terminal ("2" terminal), the second input terminal ("1" terminal), and the third input terminal ("0" terminal) according to the selection signal SEL1. The output of the tool 512. The internal circuit structure of the circuit units 520-540 is similar to that of the circuit unit 510, as shown in FIG. 5, and will not be described here.

When the serial data DIN is converted to the second data mode to transmit the mode switching signal, the clock signal CLK is maintained at a fixed level, and the multiplexers 512-542 select the second input according to the selection signals SEL1 SEL SEL4. The signal is output as a preset time and then the signal received at the first input is selected as the output. In other words, the multiplexers 512~542 are two-stage switching, and the channel is first switched to the second input terminal ("1" terminal), the output thereof is converted into a logic low potential L, and then the first input terminal is switched. ("2" end) to transfer the mode switching signal (ie, pulse signal MS) in the serial data DIN. Since the outputs of the multiplexers 512 to 542 are first switched to the logic low potential L, even if the switching timing of the circuit unit at the back end is fast, an erroneous pulse is not received. It should be noted that the multiplexer 512~542 selects the signal received by the second input as the output. The maintenance time can be expressed by the first preset time. The length can be determined according to the design requirements. This embodiment is not limited. In the above-mentioned first embodiment, the length of time for determining whether the selection signals SEL1 SEL SEL4 are switched by detecting whether the clock signal CLK is maintained at the fixed level exceeds a preset time may be represented by a second preset time, where the first preset is The time and the second preset time may be the same or different, and may be separately set according to design requirements, and the embodiment is not limited.

Next, please refer to FIG. 6 at the same time. FIG. 6 is a waveform diagram according to a third embodiment of the present invention. Taking the selection signal SEL1 as an example, when the serial data DIN is the second data mode to transmit the pulse signal MS, the clock signal is used. CLK will remain at a logic high level, and the selection signal SEL1 will switch the channel of the multiplexer 512 to the second input terminal ("1" terminal) after half of the counting time Tmode1 (ie, Tmode1/2), and then after the counting time After Tmode1, the channel of the multiplexer 512 is switched to the first input terminal ("2" terminal) to transmit the serial data DIN. Since the data stored in the last storage unit of the shift register 514 is logic high (H), the output signal DO1 is logic high before time T2, and then transitions to logic low after time T2, at time. After T3, the waveform of the output signal DO1 is the same as the serial signal DIN.

The selection signal SEL2 switches the channel of the multiplexer 522 to the second input terminal ("1" terminal) halfway through the counting time Tmode2 (ie, Tmode2/2), and then passes the multiplexer 522 after the counting time Tmode2 elapses. The channel is switched to the first input ("2" terminal) to pass the output signal DO1. Since the data stored in the last storage unit of the shift register 524 is a logic low (L), the output signal DO2 is always at a logic low until the output signal DO1 changes. After time T3, the waveform of the output signal DO2 is the same as the serial signal DIN.

The selection signal SEL3 switches the channel of the multiplexer 532 to the second input terminal ("1" terminal) after half of the counting time Tmode3 (ie, Tmode3/2), and then passes the multiplexer 532 after the counting time Tmode3 elapses. The channel is switched to the first input ("2" terminal) to pass the output signal DO2. Since the data stored in the last memory location of shift register 534 is logic high (H), output signal DO3 is logic high before time T4 and then transitions to logic low after time T4. After time T3, the waveform of the output signal DO3 is the same as the serial signal DIN.

The selection signal SEL4 switches the channel of the multiplexer 542 to the second input terminal ("1" terminal) at half of the count time Tmode4 (ie, Tmode4/2), and then passes the multiplexer 542 after the elapse of the count time Tmode4. The channel is switched to the first input ("2" end) to pass the output signal DO3. Since the data stored in the last storage unit of the shift register 544 is a logic low (L), the output signal DO4 is always at a logic low until the output signal DO3 changes. After time T3, the waveform of the output signal DO4 is the same as the serial signal DIN.

As can be seen from FIG. 6, although the switching timings of the selection signals SEL1 to SEL4 are different (Tmode1>Tmode2>Tmode3>Tmode4), after the time T3, the waveforms of the output signals DO1 to DO4 are the same as the serial signal DIN, and it is not caused by The timing difference produces an erroneous signal waveform. It should be noted that, regardless of whether the last storage unit in the shift register 514~544 is logic high or logic low, the multiplexers 512~542 will output their outputs before switching to the first input. It is first converted to a logic low level, thereby preventing the circuit unit at the back end from receiving an erroneous pulse signal. It is also shown that the technical means of this embodiment have the same effect regardless of whether the last storage unit in the shift registers 514-544 is a logic high or a logic low.

Similarly, the logic level coupled to the second input terminal ("1" terminal) of the multiplexers 512~542 can also be changed to a logic high level, and also has the effect of avoiding the output due to the timing inconsistency of the selection signals SEL1~SEL4. The waveforms of the signals DO1~DO4 are inconsistent.

In addition, it should be noted that in the present embodiment, the temporary storage circuit 500 may be composed of a plurality of circuit units 510-540 or a single circuit unit, and the number of circuit units constituting the temporary storage circuit 500 is not limited. Each of the circuit units 510-540 can be a separate integrated circuit or a chip, and the serial connection can be connected by a connection line or a cable on the printed circuit board.

Fourth embodiment

In order to solve the influence caused by the different switching timings of the selection signals SEL1 SEL SEL4, in addition to the technical means of the above embodiments, all the multiplexers can be uniformly driven directly by the shackle signal LAT outside the LED driving circuit, so that Avoid timing inconsistencies. In the field of driving circuits of light-emitting diodes, the driving circuit uses the external latch signal LAT to perform data latching. If the temporary storage circuit of this embodiment is applied to a driving circuit of a light-emitting diode, all the multiplexers can be controlled by using the shackle signal LAT. Please refer to FIG. 7. FIG. 7 is a temporary storage circuit according to a third embodiment of the present invention. The temporary storage circuit 700 includes circuit units 710-740, and the circuit units 710-740 are respectively composed of multiplexers 712-742 and shift registers 714-744, and multiplexers 712-742 and shift register 714. The circuit structure of ~744 is similar to that of FIG. 1 described above, and the main difference is that there are no selection units in circuit units 710-740.

The selection signals SEL1 to SEL4 of the circuit units 710 to 740 are generated by the external shackle signal LAT, so that the timings thereof are uniform, and there is no problem that the multiplexer switching timing is inconsistent. Please refer to FIG. 8 at the same time. FIG. 8 is a waveform diagram of a fourth embodiment of the present invention. Similarly, when the serial data DIN is converted to the second data mode, the latch signal LAT is converted to a logic high level at time T3 to switch the channels of the multiplexers 712-742 to the first input ("1"). End) until the end of the pulse signal MS. Since the selection signals SEL1~SEL4 are directly generated by the shackle signal LAT, the timing is consistent, and the waveforms of all the output signals DO1~DO4 will be the same as the serial data DIN after time T3. Therefore, the mode switching signals (composed of the pulse signals MS) received by the circuit units 710-740 of each stage are the same.

In this embodiment, the temporary storage circuit 700 may be formed by a plurality of circuit units 710-740 or may be composed of a single circuit unit 710-740, and the circuit units 710-740 may be integrated into different LED driving circuits respectively. The multiplexer 712~742 is switched by using the illuminating diode driving circuit for latching the shackle signal of the driving data. This not only avoids signal distortion, but also reduces the number of pins required for the LED driver circuit.

The above embodiments disclose embodiments of several temporary storage circuits, the main problem of which is to make the mode switching signals received by the circuit units of the stages consistent. Even if the switching timing of the circuit units of each stage is slightly different, it is possible to avoid generating an erroneous pulse signal in a certain degree of error by the above-mentioned technical means. In addition, the technical means of the above temporary storage circuit can be applied to various serially connected storage circuits or temporary storage circuits in a driving circuit (for example, a driving circuit of a display or a driving circuit of a light emitting diode). The circuit units in the temporary storage circuit can be disposed in the same wafer, or can be disposed in different wafers, and then connected to each other by the connecting lines without affecting the function.

In summary, the present invention utilizes the data format and the multiplexing sequence of the multiplexer to enable the multi-level serially connected circuit units to correctly transfer data, thereby avoiding data transmission errors due to inconsistent timing of individual circuits. In addition, the present invention is particularly suitable for a driving circuit of a light-emitting diode, and can be directly used to solve the problem of data transmission between multi-stage serial circuits.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 300, 500, 700. . . Temporary circuit

110~140, 210~240, 510~540, 710~740. . . Circuit unit

112~142, 212~242, 512~542, 712~742. . . Multiplexer

114~144, 214~244, 514~544, 714~744. . . Shift register

116~146, 216~246, 516~546. . . Selection unit

201, 202, 203, 204. . . Last storage bit

DIN. . . Serial signal

DO1~DO4. . . output signal

CLK. . . Clock signal

SEL1~SEL4. . . Selection signal

Tmode1~Tmode4. . . Counting time

T1~T4. . . Time point

MS. . . Pulse signal

H. . . Logic high potential

L. . . Logical low potential

0, 1, 2. . . Multiplexer input

1 is a temporary storage circuit in accordance with a first embodiment of the present invention.

Figure 2 is a signal waveform diagram in accordance with a first embodiment of the present invention.

3 is a temporary storage circuit in accordance with a second embodiment of the present invention.

Figure 4 is a waveform diagram in accordance with a second embodiment of the present invention.

Figure 5 is a temporary storage circuit in accordance with a third embodiment of the present invention.

Figure 6 is a waveform diagram of a third embodiment of the present invention.

Figure 7 is a temporary storage circuit in accordance with a third embodiment of the present invention.

Figure 8 is a waveform diagram showing a fourth embodiment of the present invention.

500. . . Temporary circuit

510~540. . . Circuit unit

512~542. . . Multiplexer

514~544. . . Shift register

516~546. . . Selection unit

DIN. . . Serial signal

DO1~DO4. . . output signal

CLK. . . Clock signal

SEL1~SEL4. . . Selection signal

L. . . Logical low potential

0, 1, 2. . . Multiplexer input

Claims (22)

A temporary storage circuit includes: a first circuit unit; and a second circuit unit, wherein the first circuit unit and the second circuit unit are coupled to a clock signal; wherein the first circuit unit comprises: a first a data input end for receiving the serial data; a first data output end; a first shift register having a plurality of storage elements connected in series, wherein the first one of the first shift registers The storage component is coupled to the first data input end and transmits the serial data according to the clock signal; and a first multiplexer includes a first input end, a second input end, a first output end, and a first input end a first selection end, wherein the first input end is coupled to the first data input end, the second input end is coupled to the last storage element of the first shift register, and the first output end is coupled Connected to the first data output terminal; wherein the first selection end of the first multiplexer receives a first selection signal to select a signal received by the first input terminal or the second input terminal as the first multiplexer Output and pass to the first data output ; The second circuit means comprises: a second data input end coupled to the first data output end; a second data output end; a second shift register having a plurality of storage elements connected in series, wherein the second shift The first storage element of the register is coupled to the second data input end and transmits the serial data according to the clock signal; and a second multiplexer has a third input end and a fourth input end. a second output end coupled to the second data input end, the fourth input end being coupled to the last storage element of the second shift register And the second output end is coupled to the second data output end; wherein the second multiplexer selects the signal received by the third input end or the fourth input end as the second multiple according to the second selection signal The output of the device is transmitted to the second data output terminal; wherein the first selection signal of the first multiplexer and the second selection signal of the second multiplexer are respectively set to be the second input By using the signal received by the terminal and the fourth input as an output And sending a serial data of the first data mode to the first circuit unit, and transmitting the data to the second circuit unit through the first circuit unit, and receiving the signal received by the second input end of the first multiplexer The signal received by the fourth input end of the second multiplexer is set to one after the serial data of the first data mode passes through the first shift register and the second shift register respectively. The same logic level. The temporary storage circuit of claim 1, wherein the signal received by the second input end of the first multiplexer is data corresponding to a last storage element of the first shift register, And the signal received by the fourth input end of the second multiplexer is data corresponding to the last storage element of the second shift register. The temporary storage circuit of claim 1, wherein the first selection signal of the first multiplexer and the second multiplexer of the first multiplexer are transmitted after the serial data of the first data pattern is transmitted The second selection signal is respectively set as a signal received by the first input end and the third input end, and then transmits a second data mode to the first circuit unit, and is transmitted to the first circuit unit through the first circuit unit. Second circuit unit. The temporary storage circuit of claim 3, wherein the serial data of the first data mode comprises a plurality of LED driving data, and the second data mode is a mode switching signal, wherein the mode switching The signal contains a plurality of pulse signals. The temporary storage circuit of claim 4, wherein the clock signal is maintained at a fixed level when the serial data of the first data pattern is converted to the second data mode. The temporary storage circuit of claim 5, wherein the clock signal is maintained at the fixed level for more than a predetermined time. The temporary storage circuit of claim 1, wherein the first selection signal and the second selection signal are derived from a shackle signal to lock the serial data. A temporary storage circuit includes: a first circuit unit that receives a clock signal and a series of data, the serial data comprising a first data mode and a second data mode, the first circuit unit comprising: a data input The terminal is configured to receive the serial data; a data output terminal; a shift register having K storage elements connected in series, K is a positive integer, and the shift register is coupled to the data input end And according to the clock Signaling the serial data; and a multiplexer having a first input end, a second input end, and a third input end, the first input end being coupled to the data input end, the second input end The third input end is coupled to the output of the shift register, the output end of the multiplexer is coupled to the data output end, and the multiplexer is configured according to a selection signal Selecting a signal received by one of the first input terminal, the second input terminal, and the third input terminal as an output of the multiplexer; and a selection unit coupled to the selection end of the multiplexer, and Generating the selection signal according to the data pattern of the serial data; wherein, when the serial data is the first data mode, the multiplexer selects the signal received by the third input as an output; when the serial data Converting to the second data mode, the multiplexer first selects a signal received by the second input as an output according to the selection signal and maintains a first preset time, and then selects the first input end to receive The signal acts as an output. The temporary storage circuit of claim 8, further comprising a plurality of second circuit units, the circuit structures of the second circuit units being the same as the first circuit unit, and the second circuit units and the a circuit unit connected in series and according to The clock signal sequentially transmits the serial data received by the first circuit unit. The temporary storage circuit of claim 8, wherein the first circuit unit is integrated in a light emitting diode driving circuit. The temporary storage circuit of claim 8, wherein when the serial data is the first data mode, the serial data comprises a plurality of LED driving data; when the serial data is converted into the In the second data mode, the serial data conveys a mode switching signal, wherein the mode switching signal includes a plurality of pulse signals. The temporary storage circuit of claim 11, wherein the clock signal is maintained at a fixed level when the serial data is converted to the second data mode. The temporary storage circuit of claim 12, wherein the selection unit adjusts the selection signal when the selection unit detects that the clock signal is maintained at the fixed level for more than a second predetermined time. The multiplexer first selects the signal received by the second input as an output and maintains the first preset time, and then selects the signal received by the first input as an output. The temporary storage circuit of claim 8, wherein the selection unit comprises an oscillation circuit and a counter. The temporary storage circuit of claim 1, wherein the first circuit unit and the second circuit unit are respectively integrated in a light emitting diode driving circuit. The temporary storage circuit of claim 1, wherein the first circuit unit further comprises a first selection unit for setting the first selection signal, the first selection unit comprising a first oscillation circuit and a first And the second circuit unit further includes a second selection unit for setting the second selection signal, the second selection unit comprising a second oscillation circuit and a second counter. A temporary storage circuit includes: a first circuit unit; and a second circuit unit, wherein the first circuit unit and the second circuit unit are coupled to a clock signal; wherein the first circuit unit comprises: a first a data input end for receiving serial data; a first data output end; a first shift register having a plurality of storage elements connected in series, wherein a first storage element of the first shift register is coupled to the first data input and transmitted according to the clock signal The first multiplexer includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a first selection terminal, wherein the first input terminal is coupled Connected to the first data input end, the second input end is coupled to the last storage element of the first shift register, and the first output end is coupled to the first data output end; wherein the first a first selection end of a multiplexer receives a first selection signal to select a signal received by the first input terminal, the second input terminal or the third input terminal as an output of the first multiplexer and is transmitted to the a first data output terminal; the second circuit unit includes: a second data input end coupled to the first data output end; a second data output end; a second shift register having a plurality of a storage element connected in series, wherein the second shift register a storage element coupled to the second data input end and transmitting the serial data according to the clock signal; and a second multiplexer having a fourth input end, a fifth input end, a sixth input end, a second output end and a second selection end, wherein the fourth The input end is coupled to the second data input end, the fifth input end is coupled to the last storage element of the second shift register, and the second output end is coupled to the second data output end; The second multiplexer selects a signal received by the fourth input terminal, the fifth input terminal or the sixth input terminal as an output of the second multiplexer according to the second selection signal, and transmits the signal to the second a data output end; wherein the first selection signal of the first multiplexer and the second selection signal of the second multiplexer are respectively set to be received by the second input end and the fifth input end When the signal is output, transmitting the serial data of the first data mode to the first circuit unit, and transmitting the third input to the second circuit unit through the first circuit unit, the third input of the first multiplexer And the serial data received by the terminal and the signal received by the sixth input end of the second multiplexer in the first data mode are temporarily stored in the first shift register and the second shift register Set to the same logic level after the device, and the first multiple The first selection signal and the second selection signal of the second multiplexer's are set to the third input terminal and the sixth input signal received by the output. The temporary storage circuit of claim 17, wherein the first selection signal of the first multiplexer and the second selection signal of the second multiplexer are respectively set After the signals received by the third input terminal and the sixth input terminal are output, the first selection signal of the first multiplexer and the second selection signal of the second multiplexer are respectively set. The signals received by the first input terminal and the fourth input terminal are output, and a second data mode is transmitted to the first circuit unit and transmitted to the second circuit unit through the first circuit unit. The temporary storage circuit of claim 18, wherein the serial data of the first data mode comprises a plurality of LED driving data, and the second data mode is a mode switching signal, wherein the mode switching The signal contains a plurality of pulse signals. The temporary storage circuit of claim 19, wherein the clock signal is maintained at a fixed level when the serial data of the first data pattern is converted to the second data mode. The temporary storage circuit of claim 20, wherein the clock signal is maintained at the fixed level for more than a predetermined time. The temporary storage circuit of claim 17, wherein the first circuit is The element and the second circuit unit are each integrated in a light emitting diode driving circuit.