KR100667546B1 - Test device and method of serial data link - Google Patents

Abstract

A device and a method for testing a serial data link are provided to prevent a testing error caused from an irregular delay time and facilitate a test by keeping the irregular delay time to a fixed state. An N-bit shift register(40) sequentially shifts a serial signal by synchronizing with a clock signal. A multiplexer(50) selects and outputs one of N bits shifted in the shift register according to a selection signal. An FSM(Finite State Machine)(70) counts a cycle of the clock signal until a toggle time point of the final output signal of the shift register from the toggle time point of a reference signal. The sift register is 4 serial connected flip-flops(41-44). A storing part temporarily stores an output signal of the multiplexer by synchronizing with the clock signal.

Description

Test device and method of serial data link

1 is a block diagram of a general serial data link.

FIG. 2 is a waveform diagram of serial data SDATA and clock signal RX_CLK of the receiver 20 shown in FIG. 1.

3 is a block diagram illustrating a general frame synchronizer.

4 is a configuration block diagram of a test apparatus for a serial data link according to the present invention.

FIG. 5 is a state diagram for describing an operation of the FSM shown in FIG. 4.

<Explanation of symbols for the main parts of the drawings>

1,12: clock generator 2: multiplexer

3, 13: retiming section 4, 11: buffer

14: Demultiplexer 31,32,34: Register

33: Shifter 35: Frame Pointer

36: FSM 40: Shift Register

50: multiplexer 60: D flip-flop

70: FSM

The present invention relates to an apparatus and method for testing a serial data link, and more particularly, to an apparatus and method for testing a serial data link, by maintaining a fixed delay time at the receiving end, thereby preventing test malfunction and enabling easy testing. .

1 is a diagram for explaining a general serial data link, and is composed of a transmitter 10 and a receiver 20 and a communication channel 30 between boards or systems between them.

First, the transmitter 10 includes a clock generator 1 for generating a first clock signal for serially converting parallel data and a second clock signal for data sampling, and parallel input data input according to the first clock signal ( An output of the retiming section 3 and a retiming section 3 for sampling serial data of the multiplexer 2 in accordance with a second clock signal in order to convert Din into serial data It is composed of an output buffer 4 for amplifying and buffering the logic level.

In addition, the receiver 20 includes an input buffer 11 for buffering serial input data, a clock generator 12 for generating a first clock signal for sampling and a second clock signal for converting serial data into parallel data, A retiming unit 13 for sampling serial data input in accordance with the first clock signal and a demultiplexer 14 for converting serial data into parallel data in accordance with the second clock signal.

FIG. 2 shows a waveform diagram of the serial data SDATA and the clock signal RX_CLK of the receiver 20 shown in FIG. 1.

As shown in FIG. 2, when one frame is 10 bits, the receiver 20 receives 10 bits of serial data SDATA during one period of the clock signal RX_CLK generated in the receiver 20. do. At this time, the rising or falling transition of the clock signal RX_CLK may occur at any bit of the serial data SDATA. Therefore, a separate frame aligner is required to find the starting point of a frame of parallel data output from the demultiplexer 14 shown in FIG.

FIG. 3 is a block diagram illustrating a general frame synchronizer, and finds a frame start point in parallel data output from the receiver 20 shown in FIG. 1.

The frame synchronizer shown in FIG. 3 stores a first register 31 that stores 10-bit parallel input data IN, 20 bits that store 10-bit output data and 10-bit input data IN of the first register 31, respectively. Shifter 33 and the lower 10 of the shifter 33 which receive and store the 20-bit output data of the second register 32 and the second register 32 of the bit and perform the shifting operation according to the shift control signal. The third register 34 storing the bits, the frame pointer 35 generating the shift control signal for controlling the shifting operation of the shifter 33, and the lower 10 bits of the shifter 33 are received and stored therein. It consists of a finite state machine (hereinafter abbreviated as FSM) 36 which controls the frame pointer 35 to compare with the start code and find the frame start point accordingly. At this time, each configuration is synchronized with the clock signal RX_CLK.

Referring to the operation according to the configuration, the final output data (Dout) recovered by the receiver 20 shown in Figure 1 corresponds to the 10-bit input data (IN) of the frame synchronizer. In this case, in order to find out which bit position of the input data IN is the beginning of the frame, a register capable of storing two frame sizes, that is, 20 bits, is required. Accordingly, the second register 32 stores the first 10 bits in the lower bit string and the second 10 bits input through the first register 31 in the upper bit string, respectively.

If the 9th bit of the input data IN is the start position of the frame, the 9th and 19th bits of the 20 bit data stored in the second register 32 become the start position of the frame. To find this, the FSM 36 receives the lower 10 bits of the shifter 33 and compares it with a prestored frame start code to find out which bit is the start of the frame. As a result, when the shifting control signal for controlling the operation of the shifter 33 is generated by the frame pointer 35, the lower 10 bits OUTA of the shifter 33 or the output data OUTB of the third register 34. The first bit of any one is the frame start position.

The test device based on the function test vector for checking the operation of the pseudo-synchronous or asynchronous serial transmission / reception circuits described above stores the expected output value against the input in a vector at each cycle of a specific clock and compares the actual output value with each clock cycle. The test is conducted by way of comparison. At this time, for any K-th vector value, the output value is always constant, but the output value of the actual receiver may have different test results than normal operation because the latency time varies with each test. That is, since the start position of the frame must be readjusted through the shifter 33 shown in FIG. 3, a delay of one clock cycle occurs, and since the delay time varies depending on the initial value of the frame pointer 35, one to three clock cycles. As many irregular changes occur. Therefore, the test result may be determined to be a failure even in normal operation due to an irregular delay time every time. Therefore, there has been a problem in that a lot of time wasted for the solution.

DISCLOSURE OF THE INVENTION An object of the present invention for solving the above-described problems is to provide a test apparatus method of a serial data link that can maintain an irregular delay time to prevent a malfunction of a test and to facilitate a test. .

A feature of a test apparatus for a serial data link according to the present invention for achieving the above object of the present invention is a predetermined N-bit shift register for sequentially shifting a serial signal in synchronization with a clock signal; A multiplexer for selectively outputting any one of predetermined N bits of the shift register according to a selection signal; And a finite state machine that counts a period of the clock signal from a toggle point of a reference signal to a toggle point of a final output signal of the shift register and generates the selection signal according to the result.

In addition, an additional feature of the test apparatus of the serial data link according to the present invention is that the shift register is four series connected flip-flops.

In addition, another additional feature of the apparatus for testing a serial data link according to the present invention further comprises storage means for temporarily storing an output signal of the multiplexer in synchronization with the clock signal, wherein the last Nth signal of the shift register is further included. Only the remaining signals are input to the multiplexer.

A characteristic of the test method of the serial data link according to the present invention for achieving the above object of the present invention is the first step of generating a predetermined N delay signal so as to have a difference by one clock period sequentially with respect to the serial input signal ; Counting a clock period from a toggle time point of the reference signal to a toggle time point of the Nth delay signal generated in the first step; And a third step of selectively outputting any one of the predetermined N delay signals generated in the first step according to the clock period counted in the second step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 illustrates a block diagram of a test apparatus for a serial data link according to the present invention, which includes a shift register 40, a multiplexer 50, a D flip-flop 60, and an FSM 70. It is composed of

First, the shift register 40 includes four serially connected D flip-flops (DF1 to DF4) 41 to 44, and sequentially shifts the 1-bit input signal DE in synchronization with the clock signal RX_CLK.

The multiplexer 50 selects and outputs one of each bit of the shift register 40, that is, the output bits of the D flip-flops 41 to 43, according to the selection signal SEL.

The D flip-flop 60 temporarily stores the 1-bit output signal DE_X of the multiplexer 50 in synchronization with the clock signal RX_CLK to give a delay time for one clock period.

The FSM 70 is synchronized with the clock signal RX_CLK and counts the clock period from the toggle point of the reference signal TOG_REF to the time point at which the transition of the input signal DE_CLK delayed by 4 clock periods occurs. According to the result, a selection signal SEL for signal selection of the multiplexer 50 is generated.

Looking at the operation according to the configuration as follows.

First, the shift register 40 sequentially shifts the DE signal in synchronization with the clock signal RX_CLK, so that the output signals DE_A, DE_B, DE_C, and DE_CLK of the four serially connected D flip-flops 41 to 44 are Each one has a difference of one clock cycle. At this time, the DE signal input to the shift register 40 is any bit signal of the final output data of the frame synchronizer shown in FIG. Therefore, the DE signal is an unstable state where the frame start point is unknown, but a signal generated to be toggled at the frame start point for the test. In addition, since the period of the clock signal RX_CLK corresponds to the period of the test vector in the test equipment based on the functional test vector, a signal that can be used as a reference is required. Accordingly, the reference signal TOG_REF is a signal for setting such a reference time point and is a signal generated when a transition of an arbitrary period of the test vector is performed.

5 is a state diagram for explaining the operation of the FSM 70 shown in FIG.

Looking at the operation of the FSM 70 with reference to Figure 5, first, the value of the internal count (CNT) is initially set to '0' and maintains the operation standby state (IDLE State). At this time, the internal count CNT is increased by 1 in synchronization with the clock signal RX_CLK from the toggle time of the reference signal TOG_REF (Count State). At this time, if the final output signal DE_CLK of the shift register 40 is shifted during the counting operation, the select signal SEL corresponding to the value of the internal count CNT is generated (Set State) and returns to the initial state ( Idle State). For example, assume that the reference signal TOG_REF has a rising transition in the 80th period of the test vector and the final output signal DE_CLK of the shift register 40 has a '0' delay time when the toggle occurs at the 84th time. lets do it. At this time, the DE signal may be toggled at the 80th, 81th, and 82nd times. At this time, the FSM 70 starts the counting operation from the 80th cycle. If the DE signal is toggled in the 81 st period, the DE_CLK signal is toggled in the 85 th cycle, so that the count value of the FSM 70 becomes 4. Accordingly, the FSM 70 generates the selection signal SEL to selectively output the three clock cycle delayed signal DE_C of the shift register 40 from the multiplexer 50. Then, since one clock period is further delayed while passing through the D flip-flop 60, the final output signal DE_OUT becomes the start bit of the frame. At this time, the FSM 70 transitions to the initial state again after generating the selection signal SEL and waits for operation until the next inspection.

As described above, since the final output signal DE_OUT has a fixed delay time, a malfunction due to an irregular delay time does not occur during inspection by the inspection equipment based on the functional test vector.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the test apparatus and method of the serial data link according to the present invention is configured to have a fixed delay time to prevent malfunction caused by the test due to the conventional irregular delay time, it is easy to test It is effective.

Claims (4)

A predetermined N-bit shift register for sequentially shifting serial signals in synchronization with a clock signal; A multiplexer for selectively outputting any one of predetermined N bits of the shift register according to a selection signal; And And a finite state machine that counts the period of the clock signal from a toggle point of a reference signal to a toggle point of a final output signal of the shift register and generates the selection signal according to the result. Device. 2. The test apparatus of claim 1, wherein the shift register is four series connected flip flops. 3. The method of claim 2, further comprising a storage means for temporarily storing an output signal of the multiplexer in synchronization with the clock signal, wherein only the remaining signals other than the last Nth signal of the shift register are input to the multiplexer. Characterized by a test device for serial data link Generating a predetermined N delay signals so as to sequentially have a difference by one clock period with respect to the serial input signal; Counting a clock period from a toggle time point of the reference signal to a toggle time point of the Nth delay signal generated in the first step; And And a third step of selectively outputting any one of the predetermined N delay signals generated in the first step according to the clock period counted in the second step.

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