TW201115922A - Register circuit - Google Patents

Abstract

A register circuit is provided in the application. The register circuit includes a plurality of circuit units which are serially connected to each other and used to sore and transmit a serial data. When the serial data is driving (image) data of light emitting diodes, the outputs of the circuit units are maintained to have the same logical level after the circuit units store corresponding driving data. When the serial data is the mode transformation signal, the circuit units transmit the received mode transformation signal. Because each output of the circuit units has the same logical level, so the transmission of the mode transformation signal would not be affected even if the switching timings of each circuit units are slightly inaccurate.

Description

201115922 32U8^twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a temporary storage circuit, and more particularly to a temporary storage circuit for a light-emitting diode driving device. [Prior Art] A light-emitting diode array or display is formed by a plurality of light-emitting diodes

In this case, the pins of a single drive circuit are usually not enough to drive the entire display. The drive circuit is usually formed by connecting a plurality of wafers in series, each of which is responsible for driving a plurality of or a whole row of light-emitting diodes. The operating mode of the driving chip (such as driving or detecting) can be set by a plurality of control signals, but excessive control signals cause an increase in circuit layout complexity. In addition, the wire required for long-distance serial connection will also greatly increase the manufacturing cost of the system, and all kinds of restrictions are severely popularized. Therefore, if the serial data received by the driver chip can be directly used to perform mode switching, the complexity of the circuit layout can be reduced, and the burden can be reduced. However, the data of the material list and the clock signal are combined to obtain the storage and exchange scales. (4) The towel must be set to transfer the drive data in the serial data to transfer the mode switching signal simultaneously. The tool change signal is transmitted to all serially connected drive chips for the same day. _, if the switchable signal transmission mode is switched incorrectly =:;:; = r received signal will be wrong 201115922 32082twf.doc / n [Summary] The present invention provides a temporary storage circuit, with multiple circuit unit delivery , the driving data and mode switching signal of the secondary body. When the light-emitting diode drives the data storage device, after the individual circuit unit stores the corresponding driving data, the driving device 丄: the last storage phase of the shift register in the saponin = = = = Bit (such as logic low or logic high potential ^ when the packet is switched in the transfer mode, the switching timing of the circuit units of each stage = 】 some micro error does not affect the mode switching multiplex circuit 'utilizes with three The wheeled end of the wheeled terminal __-fixed logic level high potential or logic low level). When the 2 capsules received by the temporary storage circuit are converted into the mode switching signal, the level is switched in the temporary storage circuit, and the :r::r sequence is slightly wrong': modulo == 涘爿, nor Will affect the transfer of the mode switching signal. The temporary storage circuit is directly used to directly solve the problem of inconsistent timing in the individual circuit units of the LED. Hunting this i-free unit: two Γΐ — - a temporary storage circuit 'including a plurality of circuit circuits 70 early and cross-connected - clock signal, which 201115922 32082twf.d〇c / n, the road Unit Receive - Serial Data and Clock Receiver on the multiplexer and a selection unit. The data input end is used to connect the component ^(4), and the shift register has a plurality of serially connected serial data input terminals and is used as the output of the letter if received by the third input terminal according to the clock signal transmission number. . Selecting the early blessing to the selection end of the multi-I device, generating a selection signal according to the data mode of the serial data.卞, f:,-the serial data has a first data mode and the second data mode is the same as the data material in the first data mode. The early position of the logic (砝 to potential or logic low) and the multiplexer = received = as the output; when the serial data is converted to the second data mode & for the wheel = profit according to the selection signal select the first round In the embodiment of the present invention, the circuit of the above-mentioned circuit unit is the same as the output unit, and each of the circuit units is connected to the data input terminal of the next-stage circuit unit via the above data transmission. The data is serially connected to each other and sequentially transmitted to the received serial data. In an embodiment of the invention, the circuit unit is a light emitting diode driving circuit. 201115922 32082twf.doc/n In the present invention-embodiment t, wherein when a plurality of pen-emitting diodes are included, the second-order first-pole drive is used to make the last logical = in the shift register Bit; when the serial data is converted to: the first signal to enable the multi-controller to select the first-input-received circuit to implement the 'there is a cap or the memory circuit' can be composed of a single-circuit unit ί The road is followed by - serial data, = package two rounds of human end mode. The first circuit unit comprises a _ _ 枓 枓 output, a shift register, a multiplexer and a device in a bevel input for receiving the serial data, shifting temporary storage; ^目_^=!Save component (κ is a positive integer) 'The above shift two new temporary red road, hit three rounds, round human end μ * human second input and third round The first input end is coupled to a first input end of the 201115922 32082 twf.doc/n fixed logic level (the logic high end is switched to the shift register = low potential) The third input is connected to the data output end, wherein: the rounding end of the multiplexer is coupled to the first input end, and the _============================================================= The three-wheeled input terminal is at the selection end of the multiplexer, and =, the selection unit is lightly connected to generate the above selection signal. ' The data mode of the series of shellfish materials, wherein the above-mentioned serial data has a material mode, when the above-mentioned serialized capital #贝枓极式 and a second migrant worker are crying 1 for the above-mentioned first data mode, '上诚夕- fixed level, the above (2) the clock signal maintains the selection signal received by the second input terminal, first selects the above-mentioned first and then selects the first input and __preset time, and then inputs the received signal as an output . The private 々 ^ month also proposed a kind of temporary storage circuit, suitable for - illuminating - (10) π: upper pole body. 駆 circuit receiving, lock signal = temporary memory circuit includes - the - circuit unit. The above-mentioned: - resources and - clock signals, the above-mentioned serial data has - data wheel ir -: ί, Γ 枓 mode 'where the first - circuit unit includes, a shell output, a shift Saver with a multiplex 5|. ::=;; There are "separate storages are positive integers), f passes 3f the above listed data. The first I input end is connected to the data input end, and the above-mentioned first 201115922 32〇82 twf.doc/n = the wheel end is lightly connected to the above shift. The output of the bit buffer, the multiplexed data output end, and the multiplexer outputs the output of the multiplexer according to the signal received by the latching input terminal or the second input terminal. , when the above-mentioned serial data is in the above-mentioned first data mode, when the above-mentioned series data selected by the second input terminal is converted into the second data mode, the above-mentioned multiple f cry = = The latching signal is selected as the signal received by the first-input terminal as = The present invention further proposes a temporary storage circuit, a output t, a shift register, a multiplexer, and a selection unit. Bay: ^" to receive the serial data 'shift register has M phase storage components, the shift register is coupled to the data input terminal and transmits the serial data according to the second tiger. Integer. The multiplexer has a first access to the end, a second input to the mountain, and the first input ♦ is connected to the data input terminal:: 3 is the output of the shift register, and the output of the multiplexer The two ends are coupled, and the multi-guard selects the signal received by the first input as the output of the multi-guard according to a selection signal. Select the 兀jlZ Workers? Selector to generate the selection signal. 4: (4) The tributary material has the -first data mode and the second data mode y zone, when the hopper is the data mode, the serial data includes the plurality of driving data as the Μ bit and the last one is valid. After the completion of each bit drive data Si, the data corresponding to the 'solid storage' are all the same logic level 201115922 32U82twf.d〇c/n The signal received by the second input terminal of the county As output; volume: input eight: ==: the serial data received by the wheel is converted from the driving data to the mode switching signal, and the circuit unit is converted into phase (4) 赖 ^ ^ The circuit unit of the reading stage has a signal transmission error. Happening. Correction of the field - The following is a brief description of the simplification and advantages of this issue, and the following is a detailed description of the article. [Embodiment] FIG. 1 is a temporary storage=two circuit waysheet 100 according to a first embodiment of the present invention, and a circuit unit is taken as a first step. Multi-gang peach structure (four). The circuit unit i 00 , the shift register 丨 14 盥 the selection unit 1 丨 6 ϋ the bit register 114 is coupled to the lightning loss to leave a 11 Λ, and the early 7 ° 116, wherein: the C of the 112th is 0 The input end of the material and the first wheel of the multiplex 112 ("〇" end) are directly coupled to the younger brother of the New 2 - input: Yuan 116 is engaged in multiplexed crying 2 early 11 (four) data input End 'select.

At most work crying: ID, 的2 selection end, providing selection signal SEI to evening work 112 from the selection of the first wheel signal as its output 翊 two output 边 or the brother-input terminal received · work (four): circuit unit 120, 130 and 140 are respectively composed of "142, shift register 124, 134 and 144 201115922 32082twf.doc/n select units 126, 136 and 146, and select units 丨 26, 136 and 146 respectively output SEL2 'SEL3 and SEL4 to multiplex The other circuit structures are the same as those of the circuit unit 110, and are not described in detail. The circuit units 110, 120, 130 and 140 are connected end to end, and are connected in series to the 'pre-stage circuit unit (such as 11 〇). The data output end is coupled to the data input end of the next-stage circuit unit (such as 120), and the data input end of the first-stage circuit unit 11〇 is coupled to the serial data DIN, and the output signal is output signal D01. It is shown that the output signals of the remaining stages of the circuit unit 12〇' 13〇 and H0 are represented by d〇2, D03, D04. The circuit units 110~14〇 are additionally coupled to the clock signal CLK, and are performed according to the clock signal CLK. Data shift and storage. ', f column data DIN has two The material mode is the first data mode and the first data mode, the first data mode is the driving data of the light emitting diode, and the second data mode is the mode switching signal. When the serial data, the first pure mode, The drive multiplexer 112-142 including the plurality of light-emitting diodes is switched to the second input terminal ("〇" end). When the tandem material (four) is in the second lean mode, ΙΉ 112 142 Will switch to the ^^^" end). Taking the circuit single 1G as an example, when the serial data (4) =-before mode, the multiplex H 112 selects the domain of the second input terminal (ie, the output of the shift register 114) as the output, and the remaining circuit orders = 20: The multiplexers 122 to 142 in Μ0 also select the second input terminal and the k number as the output. The data _ will be stored in the shift by shifting the temporary storage crying diodes in the memory: stocks 114 to 144. The poor material format in 201115922 32082twf.doc/n - will match the bit length of the shift register 114, so that the shift temporary storage number 114~H4 k secret elements in each of the circuit units UG~M0 For example: as shown in Figure 1 of the 7K 'shift register 114 ~ M4 last storage element (bit ♦ W table its level is logic low. Cry j this position, register 114 ~ 144 for M The shifting of the bit is temporarily stored in the second table. There is a series of serially connected strings. The driving data of the syllabus is also the Μ bit' and the last-bit of each of the negatives is fixed. For logic low, when “〇,, = 114: °, this shift DIN is transferred to the shift register to maintain a logic low, and the last bit in U1 ~Γ will be at a logic low. The rotation of the benefit 112~142 will also maintain the circuit] when the data is converted to the second data mode, even if the 122^ circuit unit 110 cannot switch the multiplexer 112 and the waybill 70120 at the same time, it will not receive the wrong mode switch. ^虎. Because even if more m2 than the multiplexer 112 switch to the first H' circuit 1 yuan 12G in the early stage of switching will receive the logic low, ^ number - no The wrong pulse signal is generated. The circuit unit 130, 140 = the road unit 12〇4 is the same, because the output of the front-stage circuit unit (for example, the output signals D02, D〇3) is still at a logic low level during the switching, because j After this, the *t channel unit switching timing is faster and does not generate an erroneous pulse. 0 201115922 32082twf.doc/n It is worth noting that, in this embodiment, when the serial data DIN is converted into the second data mode, The clock signal CLK is matched to maintain a fixed level (for example, a logic high level or a logic low level). The switching timing of the circuit units 11 〇 14 14 主要 is mainly determined by the selecting units 116 146 146, and the selecting units 116 146 146 are arranged according to the series. The data mode of the data DIN is used to select the signals SEL1 to SEL4. Since the clock signal CLK waveform of the present embodiment is changed in accordance with the data pattern of the serial data DIN, the selection units 116 to 146 can be changed according to the clock signal CLK. The selection signals SEL1 to SEL4 are generated, for example, when it is detected that the clock signal CLK is maintained high above a preset pre-set, but the embodiment is not limited thereto. When the 146 clock signal CLK is maintained at a fixed level for more than a preset time, the channels of the multiplexers 112 142 142 are switched to the first input terminal, so that all the serially connected circuit units 11 〇 14 14 〇 The mode switching signal can be synchronously received to switch the driving mode.

Next, please refer to Fig. 2'. Fig. 2 shows an apostrophe wave_ according to the first embodiment of the present invention. In this implementation, the '(4) material is converted to a mode switching signal' whose signal is composed of the pulse signal Ms, and its clock signal [Μ will be maintained at a logic high level to inform the circuit of the single magic 1 (M4g L material plane has been converted To the second data mode, after the time T1, the clock signal CLK is maintained at a logic high level, and the selection unit (10) to (10) has two preset times, and the channel fields of the multiplexers 112 to 142 are to the first input terminal. The frequency of the dials for selecting the counting time 116~146 t counting time may not be completely - so that the order of the counting time of the selection signals sel1 to sel is assumed to be T_del > T_de2 > 201115922 jzu6Ziwf.doc/n >Tmode 4. Taking the circuit units 110, 12A as an example, although the selection unit 126 of the back end switches at a faster speed, since the output k number D01 of the front end circuit unit 110 is still at a logic low level, the output signal D 〇 2 is at SEL. 2 After switching to logic high, it still maintains logic low until the pulse signal MS is received. The same is true for the rounding signals D03 and D04, even if the switching circuit speed of the back end is faster, the output signals D03 and D04 will not be produced. Error pulse signal. As is clear from Figure 2, the output signals D01, D02, D03

The waveform of the "U\J^" faithfully reflects the pulse signal 訄8 of the serial signal DIN, even if the timings of the selection signals SEL1 to SEL4 are inconsistent, the waveform after the time T1 is caused by the second embodiment. The technical means can solve the problem of data transmission error caused by the difference of the road order 7L 11G~14G timing. In addition, it is worth noting that the circuit list in the temporary storage circuit is not limited to four '1' to 14G', and may be composed of - a plurality of circuit units. Limited. Circuit action: m: as a separate circuit or a driver chip of a light-emitting diode to transfer and store the light-emitting diodes to take the next storage element (114, 124, 1; Μ, Μ The corresponding data is a logic high potential, and can also be the technical effect of the last j phase of the circuit unit 11()~14〇. For the logic high mine position, the data corresponding to the Japanese eve store is the same as the electric can, the output of the multi-guard 112~142 will remain at the logic high 13 201115922 32082twf.doc / n potential, so even the multiplexer 112 ~ 142 Without switching to the first input ("1''), the output signals D01, D02, D03, D04 will remain at the logic potential until the pulse signal MS is generated. As long as the output signal D01 ' D02 ' D03, D04 is Before the pulse signal MS is generated at the same level, the system can easily know the waveform change of the pulse signal MS. And 'even if the timings of the selection signals SEL1 to SEL4 are inconsistent, after the time τι, the signals D01, D〇 are rotated. 2. The waveforms of D〇3 and D〇4 are the same, thereby overcoming the problem that the waveforms of the output signals (10), D02, D03, and D04 are inconsistent due to the timing inconsistency of the selection signals SEL1 to SEL4. For example, it can be inferred from the above-mentioned first embodiment that the mode switching signal in the data Dm can be serially arranged as long as the (four) material stored in the last storage element of the shift register is kept at a logic low level. Therefore, in the first implementation In the example疋 Directly _ serial data _ in the # material format, let the shift temporary memory cry 114 ~ 144 of the last bit is logic low to maintain multiplex; 112 ~ 142 output is logic low. But such The method may be: The resolution of the data, for example, the (four) element is reduced to 7 bits, and the remaining last bit is used to implement the logic low. Therefore, the present invention can also be added to the shift register. - A technical means of the embodiment of the bit ST embodiment, for example, 9 兀, private temporary storage state to store 8-bit drive data 盥 1 bit 亓 logic low potential. FIG. 3, FIG. 3 is a temporary storage circuit 201115922 32082 twf.doc/n according to the second embodiment of the present invention, the temporary storage circuit 200 includes circuit units 21 〇 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 The devices 212 to 242, the shift registers 214 to 244 and the selection units 216 to 246 are constructed, and the circuit structure thereof is similar to that of the above-mentioned figure, and will not be described here. The main difference between FIG. 3 and FIG. 2M~244 respectively have one more storage bit than the shift register 114~144 (ie 2 (Π, 202, 203, 204) The shift registers 214 to 244 are the shift registers of the Μ+ι bit. When the serial data 1:)1]^ transfers the corresponding data to the shift registers 214-244 The last one of the shift registers 214~2 (ie, 201, 202, 203, 204) will remain at a logic low level 'At this time, the outputs of the multiplexers 212-242 will also remain at Logic low potential. Since the shift registers 214 to 244 respectively add a storage element 2〇1, 202, 203, 204 ' so the serial data _ will also coordinate with the adjustment of its data format, in each unit (lighting two A new bit is added to the driver data of the polar body and the bit is set to a logic low. 4 is a waveform diagram according to a second embodiment of the present invention. Since the last bit in the shift registers 2M to 244 is still * and maintained at a logic low level when the drive data is stored, the FIG. 4 The waveform is the same as that of FIG. 2, and the output signals D01 to D〇4 do not generate an erroneous signal waveform due to the timing of the selection signals SEU to SE4. Similarly, the serial data DIN can also be composed of the driving data of the bit and the logic high potential of one bit, so that the shift can temporarily store the last storage bit in the cry 214~244 (ie 2 (Π, 202, 2〇3, 2〇J are all logic high after storing the corresponding driver data. Therefore, the outputs of multiplexers 212, 222, 232 and 242 will remain at a logic high level, at ^ 15 201115922 32082 tw In the case of /n, as in the above-described first embodiment, even if the timings of the selection letters SEL1 to SEL4 are inconsistent, after the time T1, the waveforms of the output signals DO1, D2, D03, and D04 are identical. Therefore, the problem that the waveforms of the output signals d〇1, D02, D03, and D04 do not coincide with each other due to the selection signals SEL1 to SEL4 can be overcome. Referring to FIG. 5 for the third embodiment, FIG. 5 is a third embodiment of the present invention. The temporary storage circuit 500 includes circuit units 51 〇 540 540, and the circuit units 510 540 540 are composed of multiplexers 512 542 542, shift register 514 544 544 and selection units 516 546 546, respectively. Similar to Figure 1 above, it will not be described here. Figure 5 and Figure 1 main The difference lies in the multiplexers 512 to 542, and the multiplexers 512 to 542 respectively have three input terminals. Taking the circuit unit 51A as an example, the multiplexer 512 has a first input terminal, a second input terminal and a first a third input end, the first input end is coupled to the data input end to receive the serial data DIN, the first input end is connected to a logic low potential L, and the third input end is connected to the output of the shift register 514. The output of the multiplexer 512 is connected to the data output terminal to generate an output signal. The DOH multiplexer 512 selects the first input terminal ("2" terminal) and the second input terminal ("; [" terminal) according to the selection signal SEL1. The signal received by one of the third input terminals ("0" terminal) is output as the multiplexer 512. The internal circuit structure of the circuit units 520 540 540 is similar to that of the circuit unit 51 ' as shown in FIG. 5, and is not here. When the serial data DIN is converted to the second data mode to transmit the mode switching signal, the clock signal CLK is maintained at a fixed level, and the multiplexers 512 to 542 select the second according to the selection signals SEL1 to SEL4. The signal received by the terminal at 201115922 32082twf.d〇c/n is output as Hold the input end to drag the pre-sigh time, and then select the first to enter the ^ (4) field as the output. Change to the two-stage switch, prepare the first night of the work -512 ~ 542 to make the basin Switch to the second input terminal ," end, the potential L ' switch to the first input

The mode switching signal in the Γ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Will receive the wrong pulse. It should be noted that the multi-guards 512 to 542 select the first input; the received 彳 § as the output maintenance time can be expressed by the first preset time, and the length can be determined according to the design requirements, and this embodiment does not Limit of the text. In the above first embodiment, whether the time length of the selection signal S EL 1 SS EL4 is switched by the detection of whether the clock signal CLK is maintained at the fixed level exceeds a preset time may be represented by a second preset time, the foregoing The preset time and the second preset time may be the same or different, and may be separately set according to design requirements. The present embodiment is not limited. Next, please refer to FIG. 6 at the same time. FIG. 6 is a waveform diagram according to a third embodiment of the present invention. Taking the selection signal SEL1 as an example, when the serial data DIN is the second data mode to transmit the pulse signal MS, the clock signal is used. CLK will remain at logic high and select signal SEL1 is counting time

Half of the Tmodel (ie Tmodel/2) switches the channel of the multiplexer 512 to the second input ("1" end), and then switches the channel of the multiplexer 512 to the first after the counting time Tmodel Input ("2" end) to pass the serial data DIN. Since the data stored in the last memory location of shift register 514 is logic high (H), output signal D01 is at time 17 201115922 32082twf.doc/n

After the D2 is converted to a logic low, the waveform is logic high before the serial signal DIN T2, and then in the time bit, after the time Τ3, the turn signal d〇1 is the same. The selection signal SEL2 switches the multiplex n 522 (five) channel to the second input, at the half Tm 〇 de2/2 of the count time Tm()de2, and then multiplexer 522 after the elapse of the counting time Tmode2. The channel is switched to the first input ("2,") to pass the output signal (10). Since the data stored in the last memory cell of the shift register 524 is logic low (L) ', the output signal D 〇2 is always at logic low until the output signal should change. After time T3, the waveform of the output signal (10) is the same as the serial signal DIN. The selection signal SEL3 is half of the count time Tm〇de3 (ie Tm〇de3/2 Switching the channel of the multiplexer 532 to the second input terminal ('(ι) terminal and then switching the channel of the multiplexer 532 to the first input terminal (2'' end) after the counting time Tmode3 has elapsed The output of the output signal is the logical south potential (H) because the data stored in the last storage unit of the temporary storage 534 is 'so the output signal D03 is logic high before time T4, and then converted to logic low after time Τ4. Potential, and after time, output signal D03 The waveform is the same as the serial signal din. The selection signal SEL4 switches the channel of the multiplexer 542 to the second input terminal ^" at half of the count time Tm 〇 de4 (ie, TmoddQ), and then after the counting time Tmode4 Then, the channel of the multiplexer 542 is switched to the first input terminal (2" end to transmit the output signal. The data stored in the last storage unit of the shift register 544 is logic 201115922 32082twf.doc/n low. The potential (L) 'so the output signal d〇4 is directly at the logic low level until the output signal D03 changes. After the time D3, the waveform of the output signal D〇4 is the same as the serial signal DIN. As can be seen from Fig. 6, The switching timings of the selection signals SELi to SEL4 are different (1'111〇(161>1'111〇(162>1'111〇(163>1'111〇(164), but after time T3' output signal D01~ The waveform of D04 is the same as the serial signal DIN' and does not generate an erroneous signal waveform due to the timing difference. It is worth noting that the last memory cell in the shift registers 514 to 544 is logic high or logic low. , its multiplexers 512 ~ 542 will switch to the first Before an input, its output is first converted to a logic low, thereby avoiding that the circuit unit at the back end receives the wrong pulse signal. It also means that the last storage unit in the shift registers 514 to 544. For the logic high potential or the logic low potential, the technical means of the embodiment have the same effect. Similarly, the logic level coupled to the second input end ("1" end) of the multiplexers 512 542 542 can also be The logic high potential is also used to avoid the problem that the waveforms of the output signals D01 to D04 are inconsistent due to the inconsistent timing of the selection signals SEL1 to SEL4. In addition, it should be noted that, in this embodiment, the temporary storage circuit 5 can be composed of a plurality of circuit units 51 〇 540 or a single circuit unit, and the number of circuit units constituting the temporary storage circuit 500 is not affected. limit. Each of the circuit units 510-540 can be a separate integrated circuit or a chip, and the serial connection can be connected by a connecting line or a wiring on the printed circuit board.

19 201115922 32082twf.doc/n The fourth embodiment (4) is to change the timing of the selection signal seli~seu to switch the shirt b, in addition to the technical means of the above embodiments, it is also possible to directly drive the electric material part with the light emitting diode The lock number LAT is unified - the switch multiplexer' can avoid the problem of timing inconsistency. In the driving circuit field of the light-emitting diode, the driving circuit uses an external latching signal to enter the body pick. In this case, the temporary storage circuit can control all the multiplexers by taking care of the driving circuit towel of the light-emitting diode f. Please refer to FIG. 7. FIG. 7 shows a temporary storage circuit temporary storage turtle 700 according to a third embodiment of the present invention, including circuit units 71〇-740, which are respectively multiplexer 712~742 and shift temporary storage. The 714 to 7 are privately constructed, and the circuit configurations of the multiplexers 712 to 742 and the shift registers 714 to 744 are similar to those of the above-described FIG. 1, and the main difference is that the circuit units 71A to 74B do not have a selection unit. The selection signals SEL1 to SEL4 of the circuit units 710 to 740 are generated by the external pickup signal LAT, so that the timings thereof are uniform, and there is no problem that the multiplexer switching timing is inconsistent. Please also refer to Fig. 8, which is a waveform diagram according to a fourth embodiment of the present invention. Similarly, when the serial data din is converted to the second data mode, the shackle signal LAT will be converted to a logic high level at time T3 to switch the channels of the multiplexers 712 to 742 to the first input ("Γ" Until the pulse signal MS ends, since the selection signals SEL1 to SEL4 are directly generated by the shackle signal LAT, the timing is the same, and the waveforms of all the output signals D01 to D04 are the same as the serial data DIN after the time T3. The mode switching signals (composed of the pulse signal Ms) received by the first-stage circuit units 710-740 of 201115922 32082hvf.doc/n are the same. In this embodiment, the temporary storage circuit 700 can be composed of a plurality of circuit units, ~ 740 strings. Connected or composed of a single circuit unit 71〇~74〇^^ can be integrated in the non-light emitting diode driving electric pin: the m body driving circuit is used to lock the driving data of the 拴 diode driving circuit:砀 are all connected to the circuit units of each level. The above-mentioned technical means can be used as long as the signal is transmitted. In addition, the above-mentioned temporary storage avoids the generation of erroneous pulse circuits (such as the display circuit of the female circuit orThe unit can be arranged in the circuit in the same wafer path temporary writing stroke, and then connected to each other by the connecting line (10) 曰 片 综 综 综 综 综 综 综 综 综 综 、 、 、 、 、 、 、 、 、 、 厂 厂 厂 厂 厂 厂 厂The circuit unit can switch the sequence of the circuit of the circumstance of the circumstance of the circumstance of the circumstance of the circumstance of the circumstance of the circumstance of the circumstance of the circumstance of the circuit of the present invention. Resolving multiple stages Although the present invention has been disclosed above by way of example, the present invention is not limited to any one of the prior art. God and Guannai's can make some changes and: = 21 S] 201115922 32082twf.doc/n The scope of protection of the invention is subject to the patent application axis attached to the attached ~ and the other is subject to. [Simple description] 1 is a temporary storage circuit according to a first embodiment of the present invention. FIG. 2 is a signal according to a first embodiment of the present invention. FIG. 3 is a temporary storage circuit according to a second embodiment of the present invention. FIG. 4 is a second embodiment of the present invention. Example waveform diagram. Figure 5 is a third embodiment according to the present invention. Figure 6 is a waveform diagram in accordance with a third embodiment of the present invention. Figure 7 is a temporary storage circuit in accordance with a third embodiment of the present invention. Figure 8 is a waveform diagram in accordance with a fourth embodiment of the present invention. [Description of main component symbols] 100, 300, 500, 700: temporary storage circuits 110 to 140, 210 to 240, 510 to 540, 710 to 740: electrical single_112 to 142, 212 to 242, 512 to 542 ' 712 to 742: multiplexes g 114 to 144, 214 to 244, 514 to 544, 714 to 744: shift registers 116-146, 216 to 246, 516-546: selection units 201, 202, 203, 204: Last storage bit DIN: serial signal D01~D04: output signal CLK; clock signal SEL1~SEL4: selection signal

Tmodel~Tmode4: Counting time: 22 201115922 32082twf.doc/n

T1~T4 : B Snap point MS: Pulse signal Η: Logic high potential L: Logic low potential 0, 1, 2 : Input of multiplexer

twenty three

Claims (1)

201115922 32082twf.doc/n VII. Application for Patent Fan Park·· L—A temporary storage circuit, including: In a clock circuit, the circuit units are connected in series and received separately - wherein the circuits are single- The circuit unit Ϊ mode and the "number" of the serial data have a ---data two-batch type, the first circuit unit comprises: a bead input end for receiving the serial data; a data output end; The shift register has a plurality of storage elements connected in series: the shift register is coupled to the data input end and transmits the serial data according to the clock; the multiplexer has a first input end, a second input end, the first input end is coupled to the data input end, the second input end is coupled to the output of the shift temporary storage, and the output end of the multiplexer is light Connected to the tributary output end, and the multiplexer selects the first according to a selection signal a signal received by an input terminal or the second input terminal as an output of the multiplexer; and a selection unit coupled to the selection end of the multiplexer and generating the selection signal according to a data mode of the serial data ; : wherein, when the serial data is in the first physical mode, the shift register in each of the circuit units causes the shift in each of the circuit units after the serial data transfer is completed The data corresponding to the last storage element of the register is the same logic level and the multiplexer selects the signal received by the second input as the wheel ib; when the contention data is converted into the second resource 24 201115922 32082twf.doc/n = mode, which is based on the signal received by the selection as a round. The internal circuit of the input circuit of the younger brother is the temporary storage circuit as described in item 1 of the profit range, and each unit in the basin is identical to the output end of the data wheel, and the input ends of the circuits are connected in series with each other, (4) The data of the road unit is the serial data. According to the _ pulse signal, the received data is transmitted in sequence. 3. The circuit unit of the first application of the patent scope is reinforced in the light-emitting diode material, wherein each of the data is listed in the i-th item of the patent application. For the first data mode, the string:: the most device after the first data mode is delivered, the string; should: the data are all the same logical level; when the mode switching letter, the second When the second data is in the mode, the serial data transfer-5 is as follows; the main: 丨5▲-type switching signal includes a plurality of pulse signals. The serial data is converted into the temporary storage circuit described in item 4 of the monthly range, wherein when the fixed:: is converted to the two data mode, the clock signal is maintained in a selection as described in item 2 And storing the signal, wherein when the selection unit adjusts the selection signal to ==:=, the received signal is used as an output. (4) Select 5 Hai 7. If you apply for the full-time (4) item, the temporary storage circuit, which is selected 25 201115922 32082twf.doc/n The selection unit includes an oscillation circuit and a counter. 8. A temporary storage circuit, comprising: a first circuit unit, receiving a serial data comprising - a - data 巧 j smart number and - serial data, the circuit unit comprising: , , ^ ^ second data mode, the The first I:: is used to receive the serial data; the κ is a bit serially connected to each other, and the string is transmitted according to the clock signal; the:: the poor input terminal and the second output, The second input is connected to the = end, at the data output end, and the output end of the device is lightly connected..., the second round of the eight ends;::== the received signal is used as the multiplexer Turning out the second, the middle one - a selection unit, coupled to the 兮 列 column r capital: mode production (four) selection end and according to the conversion to the second data mode, the multi-n although the serial data selects the second The signal received at the input is as follows: and: according to the selection signal, the time is selected first and then the first input: the sustain-first-preemptive eight% received signal is output as an output. 26 201115922 320S2twf.doc/n Several 8 items of material, including complex-circuit list = and: Γ:: The circuit structure of the unit is connected with the first: and according to the; ΐς = port second unit The serial data received. The first circuit unit according to the eighth aspect of the patent application scope is integrated in the light-emitting diode drive, and the second temporary storage circuit described in item 8 of the patent scope, the basin Medium - the serial poor material is the first data mode, the string two:::: LED driving data; when the serial data is converted into the two; =, the serial data is transmitted The mode switching signal, the ^^+3 signal includes a plurality of pulse signals. A r-nuclear switch 12. If the temporary storage as described in item (4) of the patent application is a, the time is changed to the second data mode, and only the second level is fixed. According to the temporary storage circuit described in item 12 of the patent application scope, the selection unit detects that the clock signal is maintained at the fixed level exceeding [the second preset time, the selection The unit adjusts the selection signal to =, first selects the signal received by the second input as the round-out and maintains the preset time of the device, and then selects the first input to receive the ▼ — Out. As the wheel 14. The temporary storage selection unit as described in claim 8 includes an oscillation circuit and a counter. Among them, the 15-storage circuit is suitable for the -light diode drive_, 27 201115922 32082tw£doc/n The circuit receives-pick-up signal to lock the serial data, the first string circuit is early, pure-(four) Data and - clock signal, the f column ^ has - the first data mode and a second data mode circuit unit includes: a data input terminal; a data output terminal; - a shift temporary storage H' has κ interconnected a storage element, a second positive integer 'the shift register handle is connected to the data input end and the root data signal is transmitted by the root 5 Hz signal; and the green #-multiplexer has a first input end, a first The second input end, the younger-input end is secretive to the capital machine end, the second input end face 5 is at the output of the shift register, and the output end of the multiplexer is secreted to the output end of the device The multi 4 selects the output of the signal received by the first input terminal or the second input terminal according to the latch signal; (4) when the serial data is the first data mode, the multiplex crying is converted into an end The subtracted signal is used as the output; when the serial string is ^ the first difficult type, the more than 4 According to the latch signal Yi is selected from the play gear signal received as output. Plural: == 范: Item 45: The temporary storage circuit, including the first unit is the same, and the element: the circuit structure is connected in series with the mutual, and the first circuit circuit is sequentially transmitted according to the clock signal. ^ 28 201115922 32082twf.doc/n : Pick up the data and the rotation of the multiplexer in the early cut according to the shackle signal. Brother 17. ^Please refer to the temporary storage circuit diagram described in Item j5 of the Patent Park, which is integrated into the LED driving circuit. "18. If the application of the first-information mode mentioned in Item 15 of the Patent Fan Park is used, the serialized package is = diode driven data; when the serial data is converted into multiple pens When the (4) asset transfer-mode switching signal, the = model signal includes a plurality of pulse signals. μ mode switching Μ. A temporary storage circuit, comprising: a data input terminal for receiving the serial data; The output terminal has a storage unit that is connected in series with each other. The bit register is coupled to the data input terminal and is based on a temporary data. The data is a positive integer; the red channel passes the string. A Γ multiplexer ' has a first input end and a second round end end, so that the upper (four) is connected to the data input end, the second round end _ is; J: the output of the register is ' The output end of the multiplexer is coupled to: and the multiplexer selects the second core wheel according to a selection signal - the signal received by the second input is used as the multiplexer's turn; 'and or the brother selects a unit coupled to the selected _ selection signal of the multiplexer; Media ★ Its I' the serial data has a first data mode and - the second rough type 1 the serial data is the first data mode = 枓 τ ° 豕 工 选择 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 n The signal received by the second input terminal is used as the driving data of the pen, and each of the driving data is the heart == the data includes the same as the recurring bit, so that (4) the shift register is the last - there, the shift The last storage element of the register: =^ material passes the logic level; when the serial resource signal is used as the wheel. The input string received by the input port: the temporary storage circuit described in the second paragraph, When the mode switches mode, the serial data transfer - 21. Mode switching money includes a plurality of pulse signals. The serial resource 4: =;: two, ^ a fixed level. When the brother a mode, the Xu The pulse signal is maintained in the temporary storage circuit described in item 19 of the second patent scope, wherein when the time is set, the pulse-collecting signal is maintained at the fixed level, and the pre-processing is more difficult than the acceptance of the 23-round input. The signal is used as an output. The unit is selected from the temporary storage circuit described in claim 19, wherein Includes an oscillation circuit and a counter. 30