JP6673100B2 - Semiconductor device - Google Patents

Description

  The technology disclosed in this specification relates to a semiconductor device.

  A semiconductor element having a substantially rectangular parallelepiped shape, electrodes are formed on each of the front and rear surfaces, and a low resistance is formed between the front and rear electrodes by the semiconductor structure formed inside the semiconductor element. Semiconductor devices that switch between a state and a high resistance state are known. Various electrodes are formed on the surface of the semiconductor element. For example, an electrode for inputting a voltage indicating a resistance state, an electrode for outputting a voltage corresponding to a temperature, an electrode for outputting a voltage corresponding to a current value, and the like are prepared. Have been. In the present specification, a command voltage input electrode, a temperature-corresponding voltage output electrode, a current value-corresponding voltage output electrode, and the like are collectively referred to as signal electrodes. The side on which the signal electrode is formed is called a surface. A front electrode and a signal electrode group are formed on the front surface of the semiconductor element, and a back electrode is formed on the back surface of the semiconductor element.

  The surface electrode has a larger area than the individual signal electrodes. A signal electrode group is arranged along one side on the surface of the semiconductor element having a substantially rectangular shape in plan view, and the surface electrodes are formed widely in other areas. The front surface electrode and the back surface electrode are joined to the conductive material by the solder layer. At least one of the front surface electrode and the back surface electrode is soldered to the conductive plate directly or via a conductive member. The conductive plate includes a bus bar extending from the semiconductor element and connecting the load or power supply to the semiconductor element.

  When the semiconductor element operates, a state where a current flows between the front surface electrode and the back surface electrode and a state where the current does not flow are switched. Therefore, when the semiconductor element operates, the semiconductor element generates heat. Accordingly, the solder layer is also heated. The solder layer is heated when the semiconductor device operates, and cooled when the semiconductor device ends operation. The solder layer is subjected to a cycle of thermal stress. The solder layer is required to have durability to withstand thermal stress cycles.

  The surface electrode is formed on a substantially rectangular surface in plan view, and has a substantially rectangular outline. That is, it has four corners. Thermal stress that develops in the semiconductor layer becomes large near the corner. Therefore, there is a need for a technique for reducing the peak value of the thermal stress generated in the solder layer located near the corner. For example, in the technique of Patent Document 1, all four corners of the surface electrode are chamfered, and the degree of concentration of thermal stress developed near the corners is reduced.

JP 2004-134746 A

  As described above, the surface electrode is formed in a range avoiding the signal electrode group formed along one side. In this case, of the four corners of the surface electrode, two corners close to the signal electrode group are easily cooled, while two corners far from the signal electrode group are hard to be cooled. Large thermal stress easily develops. The size of the chamfer required to avoid the development of excessive thermal stress differs between the near and far corners. The conductive plate to which at least one of the front surface electrode and the back surface electrode is soldered has a bus bar. In this case, of the four corners of the surface electrode, two corners near the bus bar are easily cooled, while two corners far from the bus bar are hard to cool. Stress easily develops. The size of the chamfer required to avoid the development of excessive thermal stress differs between the two corners near and far from the bus bar.

  However, in the technique of Patent Document 1, all four corners of the surface electrode are chamfered uniformly. If all four corners are uniformly chamfered, the area of the surface electrode is unnecessarily reduced at the corners near the signal electrode group and at the corners near the bus bar. For this reason, the area of the solder layer is reduced, and the thermal resistance between the surface electrode and the conductive material is increased.

  This specification discloses a technique for reducing thermal stress generated in a solder layer for joining semiconductor elements.

  The semiconductor device disclosed in this specification includes a semiconductor element and a conductive plate. The semiconductor device has a substantially rectangular surface, a signal electrode group is formed at a position along one side of the surface, a surface electrode is formed at a position avoiding the signal electrode group, and a back surface is formed. A back electrode is formed. The conductive plate is provided with a bus bar which is electrically connected to at least one of the front surface electrode and the back surface electrode and extends toward another member. The surface electrode has four corners chamfered on an arc and can be classified into one corner far from the signal electrode group and the bus bar, and three corners closer to the signal electrode group or the bus bar than the one corner. The radius of curvature at one corner is larger than the radius of curvature at the three corners. The outline of the solder layer that joins the surface electrodes corresponds to the outline of the surface electrodes. That is, the solder layer also has four corners, and the radius of curvature of one corner far from the signal electrode group and the bus bar is larger than the radius of curvature of the three corners near the signal electrode group or the bus bar.

  In the above semiconductor device, of the four corners of the surface electrode, the radius of curvature of one corner far from the signal electrode group and far from the bus bar is the radius of curvature of the three corners closer to one of the signal electrode group or the bus bar than the one corner. Greater than. That is, of the four corners of the surface electrode, the radius of curvature of one corner that is most difficult to cool is larger than the other three corners. For this reason, stress concentration occurring in the solder layer located in the vicinity of one corner where cooling is most difficult can be suitably reduced. In addition, since the radius of curvature of the other three corners is smaller than the radius of curvature of one corner far from the signal electrode group and far from the bus bar, a decrease in the area of the surface electrode at the other three corners can be suppressed. Therefore, an increase in thermal resistance between the surface electrode and the conductive material can be suppressed. Therefore, it is possible to suppress the increase in thermal resistance between the surface electrode and the conductive material while reducing the stress concentration generated in the solder layer, and it is possible to reduce the thermal stress generated in the solder layer.

FIG. 1 is an exploded perspective view illustrating a schematic configuration of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of a part of the semiconductor device according to the first embodiment. FIG. 2 is a top view illustrating a schematic configuration of a lead frame and a semiconductor element included in the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view of a part of the semiconductor device according to the second embodiment.

  FIG. 1 is an exploded perspective view of the semiconductor device 2 according to the first embodiment. FIG. 2 is a sectional view of the semiconductor device 2 in the yz plane. As shown in FIG. 1, the semiconductor device 2 includes a semiconductor element 10, lead frames 20a and 20b, and a metal block 30. The semiconductor element 10 and the metal block 30 are sandwiched between the lead frames 20a and 20b. That is, the semiconductor element 10 is arranged on the lead frame 20a, the metal block 30 is arranged on the semiconductor element 10, and the lead frame 20b is arranged on the metal block 30.

  The semiconductor element 10 is substantially a rectangular parallelepiped. A surface electrode (emitter electrode) 12 and five signal electrodes 18 are exposed on the surface of the semiconductor element 10 (that is, on the + z direction side). As shown in FIG. 2, a back surface electrode (collector electrode) 16 is exposed on the back surface of the semiconductor element 10 (that is, on the −z direction side). The semiconductor layer 14 is formed between the emitter electrode 12 and the signal electrode 18 and the collector electrode 16. In the semiconductor layer 14, a semiconductor structure for switching between a low resistance state and a high resistance state between the emitter electrode 12 and the collector electrode 16 is formed. The surface of the semiconductor element 10 where neither the emitter electrode 12 nor the signal electrode 18 is exposed is covered with an insulating layer (not shown).

  The five signal electrodes 18 are arranged along one side 11 of the surface of the semiconductor element 10. The side 11 is one side of a substantially rectangular surface of the semiconductor element 10, and is a side parallel to the x direction and on the −y direction side as shown in FIG. The five signal electrodes 18 input and output different types of voltages, respectively. In the present embodiment, five signal electrodes 18 are exposed on the surface of the semiconductor element 10, but the present invention is not limited to such a configuration, and the type and number thereof can be changed as needed. . The type of the signal electrode 18 includes, for example, an electrode for inputting an instruction voltage for instructing the semiconductor element 10 to be in a low resistance state or a high resistance state, an electrode for outputting a temperature corresponding voltage indicating the temperature of the semiconductor element 10, There is an electrode that outputs a current value-corresponding voltage indicating a current value flowing through the semiconductor element 10. The signal electrode 18 is connected to another member by a wire (not shown). The signal electrode 18 and the wire are connected by, for example, wire bonding.

  The emitter electrode 12 is arranged on the surface of the semiconductor element 10 so as to avoid the position where the signal electrodes 18 are arranged. That is, the emitter electrode 12 is arranged at a position away from the group of signal electrodes 18 from one side 11 along which the signal electrodes 18 are arranged. The emitter electrode 12 is formed larger than the signal electrode 18. The shape in which the emitter electrode 12 is exposed on the surface of the semiconductor element 10 (the shape when viewed from the z direction) will be described later. As shown in FIG. 2, the emitter electrode 12 and the signal electrode 18 are embedded in the surface of the semiconductor element 10, and the surface formed by the insulating member covering the emitter electrode 12, the signal electrode 18, and other areas is It is almost flat.

  The lead frames 20a, 20b are flat conductive members. The lead frame 20a includes a substantially rectangular main body 22a and a bus bar 24a connecting the main body 22a to another member. In FIG. 1, the bus bar 24a is parallel to the x direction and extends from one side 26a of the main body 22a in the + y direction. Further, the bus bar 24a is connected to the main body 22a on the −x direction side from the center of the side 26a. The bus bar 24a extends from the semiconductor device 2 and is connected to, for example, a load or a power supply. The lead frame 20b has substantially the same shape as the lead frame 20a, and when the semiconductor device 2 is viewed in a plan view (when viewed from the z direction), the lead frames 20a and 20b substantially match. In this embodiment, each of the lead frames 20a and 20b has a bus bar, but the present invention is not limited to such a configuration. For example, one of the two lead frames may be provided with a bus bar, and the other may not be provided with a bus bar.

  The metal block 30 has a substantially rectangular parallelepiped shape and is formed of copper (Cu). The surface of the metal block 30 perpendicular to the z direction is substantially the same as the exposed shape of the emitter electrode 12 described later. The metal block 30 is a spacer. By arranging the metal block 30, a space is created between the signal electrodes 18 and the lead frame 20b. Thereby, a wire can be connected to the signal electrode 18 group.

  The semiconductor element 10, the lead frames 20a and 20b, and the metal block 30 are respectively soldered. As shown in FIG. 2, the collector electrode 16 is connected to the lead frame 20a via the solder layer 36. The emitter electrode 12 is connected to the metal block 30 via the solder layer 34. The metal block 30 is connected to the lead frame 20b via the solder layer 32. Only the part of the surface of the semiconductor element 10 where the emitter electrode 12 is exposed is joined to the metal block 30. The outline of the solder layer 34 substantially matches the outline of the area where the emitter electrode 12 is exposed. The outline of the solder layer 32 substantially matches the outline of a surface of the metal block 30 perpendicular to the z direction.

  The semiconductor element 10 is connected to the lead frame 20b via the solder layer 34, the metal block 30, and the solder layer 32, and is connected to the lead frame 20a via the solder layer 36. The heat of the semiconductor element 10 is transmitted to the lead frame 20b via the solder layer 34, the metal block 30, and the solder layer 32, and is transmitted to the lead frame 20a via the solder layer 36. The lead frames 20a and 20b are connected to a cooler via an insulating plate (not shown). The semiconductor device 10 can be cooled by the cooler.

  The shape of the emitter electrode 12 will be described. FIG. 3 is a top view of the lead frame 20a and the semiconductor element 10. FIG. In addition, illustration of the solder layer 34, the metal block 30, the solder layer 32, and the lead frame 20b is omitted for convenience of explanation.

  As shown in FIG. 3, the outline of the range where the emitter electrode 12 is exposed is substantially rectangular. That is, the contour of the emitter electrode 12 has four corners 41, 42, 43, 44. The corner 41 is an upper right corner in FIG. 3 and is located in the + x direction and the + y direction of the emitter electrode 12. That is, the corner 41 is far from the signal electrodes 18 arranged near the one side 11 of the semiconductor element 10 and far from the bus bar 24a. The corner 42 is an upper left corner of FIG. 3 and is located in the −x direction and the + y direction of the emitter electrode 12. That is, the corner 42 is far from the signal electrode 18 group but close to the bus bar 24a. The corner 43 is a lower right corner of FIG. 3 and is located in the + x direction and the −y direction of the emitter electrode 12. That is, the corner 43 is far from the bus bar 24a but close to the signal electrode 18 group. The corner 44 is a lower left corner in FIG. 3 and is located in the −x direction and the −y direction of the emitter electrode 12. That is, the corner 44 is close to the signal electrode group 18 and also close to the bus bar 24a. Each of the four corners 41, 42, 43, and 44 is chamfered and has an arc shape. The radius of curvature of the corner 41 is larger than the radius of curvature of the other three corners 42, 43, 44.

  Since the four corners of the emitter electrode 12 are chamfered, the concentration of thermal stress at the corner of the solder layer 34 adjacent to the emitter electrode 12 can be reduced. As described above, the emitter electrode 12 is substantially rectangular. If the corner of the emitter electrode 12 is not chamfered, the thermal stress developed in the solder layer 34 increases near the corner (apex). In the emitter electrode 12 of this embodiment, since the four corners 41, 42, 43, and 44 are chamfered, the concentration of thermal stress at the corners can be reduced.

  Further, among the four corners 41, 42, 43, 44 of the emitter electrode 12, the radius of curvature of the corner 41 is larger than the radius of curvature of the other three corners 42, 43, 44. As described above, the corner 41 is far from the signal electrode group 18 and far from the bus bar 24a. Since the group of signal electrodes 18 is arranged between the emitter electrode 12 and one side 11 of the semiconductor element 10, the corners 43 and 44 closer to the group of signal electrodes 18 generate more heat than the corners 41 and 42 farther from the group of signal electrodes 18. Easy to spread. Further, heat is more easily diffused at the corners 42 and 44 near the bus bar 24a than at the corners 41 and 43 far from the bus bar 24a. Therefore, in the corner 41 far from the side 11 and far from the bus bar 24a, heat is least diffused among the four corners 41, 42, 43, and 44. That is, thermal stress is most likely to be concentrated. In the emitter electrode 12 of this embodiment, the radius of curvature of the corner 41 is larger than the radius of curvature of the other three corners 42, 43, and 44, so that the concentration of thermal stress can be effectively reduced.

  Further, the radii of curvature of the three corners 42, 43, 44 are smaller than the radii of curvature of the corner 41. If the corner is chamfered, the concentration of thermal stress can be reduced, but the area of the emitter electrode 12 decreases, so that the thermal resistance between the semiconductor element 10 and the lead frame 20a increases. In the emitter electrode 12 of the present embodiment, the curvature radii of the corners 41 where the thermal stress is most likely to be concentrated are increased, and the curvature radii of the three corners 42, 43 and 44 where the thermal stress is less likely to be concentrated as compared with the corner 41 are reduced. ing. As a result, the amount of decrease in the electrode area caused by chamfering can be suppressed. That is, a decrease in the area of the emitter electrode 12 can be suppressed. Therefore, it is possible to effectively reduce the concentration of the thermal stress and to suppress an increase in the thermal resistance between the semiconductor element 10 and the lead frame 20a. Therefore, thermal stress generated in the solder layer 34 can be reduced.

  As described above, the shape of the surface of the metal block 30 of the present embodiment perpendicular to the z direction substantially matches the shape of the emitter electrode 12. Therefore, also in the solder layer 32, the concentration of the thermal stress can be effectively reduced, and the increase in the thermal resistance between the semiconductor element 10 and the lead frame 20a can be suppressed.

  In this embodiment, the difference in the radius of curvature between the three corners 42, 43, and 44 other than the corner 41 is not described. For example, the radius of curvature of the corner 44 is smaller than the radius of curvature of the corners 42 and 43. You may. As described above, the corner 44 is close to the group of signal electrodes 18 and close to the bus bar 24a. Therefore, the corner 44 is more likely to be cooled than the corner 42 far from the signal electrode 18 group or the corner 43 far from the bus bar 24a. Therefore, the radius of curvature of the corner 44 can be made smaller than the radius of curvature of the corners 42 and 43.

  The semiconductor device 102 will be described with reference to FIG. As shown in FIG. 4, the semiconductor device 102 includes a lead frame 120, and the lead frame 120 is connected to the emitter electrode 12 via a solder layer 132. Note that the semiconductor device 102 does not include the metal block 30 of the semiconductor device 2 of the first embodiment, and the lead frame 120 and the emitter electrode 12 are connected without the metal block 30 therebetween. It is the same. Therefore, the description of the same configuration as the semiconductor device 2 of the first embodiment is omitted.

  The lead frame 120 includes a main body 122 and a concave portion 121 arranged at the center of the main body 122. The concave portion 121 is formed at a position substantially coincident with the emitter electrode 12 when viewed in plan (when viewed from the z direction). The recess 121 projects from the outside of the semiconductor device 102 toward the semiconductor element 10. The bottom of the recess 121 has a shape substantially matching the shape of the emitter electrode 12. The main body 122 has the same shape as the main body 22 of the first embodiment except for the portion where the concave portion 121 is provided.

  The semiconductor device 102 does not include the metal block 30 used as the spacer in the first embodiment. However, since the lead frame 120 includes the concave portion 121, a space can be secured between the signal electrode 18 and the lead frame 120. Therefore, a wire can be connected to the signal electrode 18.

  In the semiconductor device 102 as well, the radius of curvature of one corner 41 of the emitter electrode 12 is larger than the radius of curvature of the other three corners 42, 43, 44. Further, the shape of the bottom of the concave portion 121 connected to the emitter electrode 12 via the solder layer 132 substantially matches the shape of the emitter electrode 12. Therefore, also in the semiconductor device 102, the concentration of the thermal stress can be effectively reduced, and the increase in the thermal resistance between the semiconductor element 10 and the lead frame 120 can be suppressed. Therefore, thermal stress generated in the solder layer 132 can be reduced.

  Points to keep in mind regarding the semiconductor device described in the embodiment will be described. The emitter electrode 12 of the embodiment is an example of the “front surface electrode” of the claims, and the collector electrode 16 of the embodiment is an example of the “back surface electrode” of the claims, and the lead frames 20a, 20b, and 120 of the embodiment are described. Is an example of the “conductive plate” of the claims, the corner 41 of the embodiment is an example of the “one corner” of the claims, and the corners 42, 43, 44 of the embodiment are the “three corners” of the claims. This is an example.

  As described above, specific examples of the present invention have been described in detail, but these are merely examples, and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and has technical utility by achieving one of the objects.

2: semiconductor device 10: semiconductor element 12: emitter electrode 14: semiconductor layer 16: collector electrode 18: signal electrode 20a, 20b: lead frame 22a: main body 24a: bus bar 30: metal block 32, 34, 36: solder layer 41 , 42, 43, 44: corners of emitter electrode

Claims (1)

It has a substantially rectangular surface, a signal electrode group is formed at a position along one side of the surface, a front electrode is formed at a position avoiding the signal electrode group, and a back electrode is formed on the back surface Semiconductor element,
A conductive plate having a bus bar that is electrically connected to at least one of the front surface electrode and the back surface electrode and that extends toward another member is provided.
The surface electrode has four corners chamfered on an arc, the four corners are one corner far from the signal electrode group and far from the bus bar, and three corners closer to the signal electrode group or the bus bar than the one corner. Can be classified into
The radius of curvature of the one corner is larger than the radius of curvature of the three corners,
A semiconductor device, wherein an outline of a solder layer joining the surface electrodes corresponds to an outline of the surface electrodes.

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