JP6660754B2 - A / D converter, remaining battery level detection circuit using the same, and electronic device - Google Patents

Description

  The present invention relates to an A / D converter.

  2. Description of the Related Art In various electronic devices, an A / D converter that converts an analog signal representing these states into a digital signal is used to digitally process an electrical state of an internal circuit and a physical state of the electronic apparatus. The A / D converter has a large circuit area and is expensive. Therefore, when it is necessary to process a plurality of analog signals, a multiplexer (selector) is inserted before the A / D converter, and the multiplexer selects a plurality of electric signals. In some cases, a shared configuration may be adopted.

  In such a combination circuit of a multiplexer and an A / D converter, it is common to switch a plurality of analog signals sequentially for each A / D conversion, or to switch based on a table defined in advance.

Japanese Patent No. 4646285 Japanese Patent No. 5557866

  Conventionally, it has been necessary to determine which analog signal is to be measured and at what period in a design stage or in a setup stage before the start of operation. However, in a situation where an analog signal whose variation time scale (that is, variation speed) dynamically changes is to be measured, if the conversion cycle is fixed, the following problem occurs. For example, if the time scale of the variation of the analog signal is longer than a predetermined conversion cycle, the same value will be repeatedly converted even though the value does not substantially change compared to the previous conversion timing, Power consumption is wasted. Conversely, if the time scale of the fluctuation of the analog signal is shorter than the predetermined conversion cycle, the high-speed fluctuation of the analog signal will be missed.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an embodiment thereof is to provide an A / D conversion circuit capable of A / D converting a plurality of analog signals at an appropriate frequency. .

  One embodiment of the present invention relates to an A / D converter. The A / D converter includes a multiplexer that receives a plurality of analog signals, a main A / D converter that performs A / D conversion on the analog signal selected by the multiplexer, and a slope detector that detects a slope of each of the plurality of analog signals. A controller that controls the multiplexer and the A / D converter. The controller schedules A / D conversion of the main A / D converter for each analog signal based on the corresponding slope.

  According to this aspect, A / D conversion can be scheduled at an appropriate frequency by measuring a slope having a correlation with the time scale of fluctuation for each of the plurality of analog signals. As a result, useless power consumption due to useless A / D conversion can be reduced. Further, when the time scale of the fluctuation is shortened, the A / D conversion is scheduled at a short time interval so that the measurement can be performed without missing the high-speed fluctuation of the analog signal.

The inclination detection unit may include a sub A / D converter that performs A / D conversion on an analog signal selected by the multiplexer.
To detect the inclination, two A / D conversions are required. By allocating at least one of the two A / D conversions to the sub A / D converter, the number of empty slots in the main A / D converter can be increased.

The controller schedules A / D conversion by the sub A / D converter after the A / D conversion by the main A / D converter for each channel, and outputs the output data of the main A / D converter and the output of the sub A / D converter. The inclination may be detected based on a data pair.
By allocating one of the two A / D conversions for inclination detection to the original A / D conversion by the main A / D converter, the number of conversions and power consumption can be reduced.

  The number of bits of the sub A / D converter may be smaller than the number of bits of the main A / D converter. Thereby, the area of the sub A / D converter can be reduced, or the power consumption can be reduced.

The controller may schedule the A / D conversion by the sub A / D converter twice consecutively for each channel, and detect the slope based on the pair of output data of the sub A / D converter twice. .
Thus, the inclination can be detected regardless of the original A / D conversion by the main A / D converter.

The main A / D converter may be a successive approximation type. The controller schedules the second A / D conversion by the main A / D converter with a smaller number of bits than the first one after the A / D conversion by the main A / D converter for each channel. The inclination may be detected based on a pair of two output data of the converter.
Since a sub A / D converter is not required, an increase in circuit area can be suppressed.

  The A / D converter may be integrated on one semiconductor substrate. "Integrated integration" includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrally integrated. A resistor, a capacitor, and the like may be provided outside the semiconductor substrate.

  Another embodiment of the present invention relates to a battery level detection (Fuel Gauge) circuit. The remaining amount detection circuit may include any one of the above-described A / D converters.

  The plurality of analog signals input to the multiplexer of the A / D converter may include at least a signal indicating the charge / discharge current of the battery and a signal indicating the temperature of the battery.

  It should be noted that any combination of the above-described components, and any replacement of the components and expressions of the present invention between methods, apparatuses, systems, and the like are also effective as embodiments of the present invention.

  According to the present invention, a plurality of analog signals can be A / D converted at an appropriate frequency.

FIG. 2 is a block diagram of an A / D converter according to the embodiment. FIG. 2 is an operation waveform diagram of the A / D converter of FIG. 1. FIGS. 3A to 3C are diagrams schematically illustrating A / D conversion scheduling of a plurality of analog signals. FIG. 2 is a block diagram illustrating a first configuration example of an A / D converter. FIG. 5A is an operation waveform diagram of the A / D conversion device according to the first configuration example, and FIG. 5B is an operation waveform diagram of the A / D conversion device according to the second configuration example. It is a block diagram showing the 3rd example of composition of an A / D converter. FIG. 13 is an operation waveform diagram of the A / D converter according to the third configuration example. FIG. 2 is a block diagram of a battery remaining amount detection circuit including the A / D converter.

  Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and the repeated description will be omitted as appropriate. In addition, the embodiments do not limit the invention, but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” refers to a case where the member A and the member B are physically directly connected, or a case where the member A and the member B are electrically connected to each other. It does not substantially affect the connection state or does not impair the function or effect provided by the combination thereof, and also includes the case where the connection is indirectly performed through another member.
Similarly, “the state in which the member C is provided between the member A and the member B” means that the member A and the member C or the member B and the member C are directly connected, It does not substantially affect the actual connection state, or does not impair the function or effect exerted by the combination thereof, and also includes the case where the connection is made indirectly via another member.

  Further, in this specification, reference numerals given to voltage signals, current signals, or resistors represent respective voltage values, current values, or resistance values as necessary.

  FIG. 1 is a block diagram of an A / D converter 100 according to the embodiment. The A / D converter 100 mainly includes a main A / D converter 102, a multiplexer 104, a tilt detector 110, and a controller 120. Preferably, the A / D conversion device 100 is integrated on a single semiconductor substrate alone or together with other circuit blocks.

  The A / D converter 100 includes a plurality of N (N is an integer of 2 or more) analog input ports PORT1 to PORTN, and can input a plurality of analog signals V1 to VN to be measured. The multiplexer 104 receives a plurality of analog signals V1 to VN and selects one according to the control signal S1. The type and properties of the analog signal are not particularly limited. For example, the plurality of analog signals may include a signal indicating an electrical state, such as a current detection signal indicating a current flowing through a predetermined node, a voltage detection signal indicating a voltage generated at a predetermined node, or the like. Alternatively, the plurality of analog signals include a signal indicating a physical state, such as a signal from a temperature sensor (thermistor, posistor, thermocouple), a signal from a gyro sensor, an acceleration sensor, a speed sensor, a signal from a motor rotation sensor, and the like. May be.

  The main A / D converter 102 receives the analog signal S2 selected by the multiplexer 104, and converts the analog signal S2 into a digital signal S4 in response to an A / D conversion timing signal S3. The controller 120 generates the control signal S1 and the timing signal S3, and controls the multiplexer 104 and the main A / D converter 102. The main A / D converter 102 may be, for example, a successive approximation type, but is not limited thereto, and may be a flash type, a tilt type, a ΔΣ type, or the like.

  The inclination detection unit 110 detects the inclination α1 to αN of each of the plurality of analog signals V1 to VN, and detects data (referred to as inclination data) S6 indicating the inclination. The tilt data S6 is input to the controller 120. Since the controller 120 currently knows which port of the analog signal is selected by the multiplexer 104, the controller 120 can know the number of the analog signal whose slope data S6 indicates. The controller 120 schedules the detected A / D conversion of the main A / D converter 102 for each analog signal Vi (1 ≦ i ≦ N) based on the corresponding slope αi indicated by the slope data S6. Although the timing of detecting the inclination by the inclination detection unit 110 is not particularly limited, in the present embodiment, the inclination is detected for each A / D conversion by the main A / D converter 102, and the following is detected based on the obtained inclination α. A / D conversion is scheduled. The controller 120 may hold the gradient α and the time interval of A / D conversion in a table, or may define a function using the gradient α as an argument and calculate the time interval.

  The ADC interface 130 and the data register 132 are interface circuits for transferring output data S4 of the main A / D converter 102 to a subsequent block, and are optional. The ADC interface 130 writes the output data S4 of the main A / D converter 102 into the data register 132 indicated by the control signal S5 from the controller 120. For example, data register 132 may include a plurality of data registers corresponding to a plurality of ports, and output data S4 obtained for the i-th port may be stored in the i-th data register. Alternatively, the ADC interface 130 may store the sequentially generated output data S4 in a plurality of data registers in chronological order.

  The above is the configuration of the A / D converter 100. Subsequently, the operation will be described. FIG. 2 is an operation waveform diagram of the A / D converter 100 of FIG. FIG. 2 shows the operation of one analog signal V1.

(Step i) When the timing signal S3 is asserted, the analog signal V1 at that time is A / D converted to generate a digital signal S4.
(Step ii) Subsequently, the inclination of the analog signal V1 is detected, and the inclination data S6 is updated.
(Step iii) The next A / D conversion timing is scheduled based on the updated inclination data S6. Specifically, in the period until the next A / D conversion, the scheduling is shorter as the absolute value of the gradient is larger, and the scheduling is longer as the absolute value of the gradient is smaller.
The above is the operation of one cycle. In the next cycle (step i), the timing signal S3 is asserted at the timing scheduled in the previous cycle (step iii). The A / D converter 100 repeats this operation.

  FIG. 2 shows only the operation related to one analog signal V1, but in reality, the same processing is performed in parallel on a plurality of analog signals V1 to VN, and the time of the fluctuation of each analog signal V1 is changed. The timing of A / D conversion is appropriately adjusted according to the scale.

  FIGS. 3A to 3C are diagrams schematically illustrating A / D conversion scheduling of a plurality of analog signals. Here, N = 3 is taken as an example. Three A / D conversions are regarded as one set. In FIG. 3A, the conversion of the analog signals V1 and V3 is scheduled once in one set, and the conversion of the analog signal V2 is scheduled once in three sets. In FIG. 3B, conversion of analog signals V1 and V2 is scheduled once every two sets, and conversion of analog signal V3 is scheduled once every set. In FIG. 3 (c), the conversion of the analog signal V1 is scheduled less frequently, and the conversion of the analog signals V2 and V3 is scheduled once in one set.

  According to the A / D converter 100 according to the embodiment, it is possible to reduce unnecessary power consumption due to unnecessary A / D conversion. Further, when the time scale of the fluctuation is shortened, the A / D conversion is scheduled at a short time interval so that the measurement can be performed without missing the high-speed fluctuation of the analog signal.

  The present invention extends to various devices and circuits that can be grasped as the block diagram or circuit diagram of FIG. 1 or derived from the above description, and is not limited to a specific configuration. Hereinafter, a more specific configuration example will be described, not to narrow the scope of the present invention, but to help understand and clarify the essence and circuit operation of the present invention.

(First configuration example)
FIG. 4 is a block diagram illustrating a first configuration example of the A / D conversion device 100. The inclination detection unit 110 includes a sub A / D converter 112 for A / D converting the analog signal S2 selected by the multiplexer 104. Since a high degree of accuracy is not required for the inclination, the sub A / D converter 112 may be configured with a lower bit number than the main A / D converter 102. As a result, the circuit area of the sub A / D converter 112 can be reduced, and its power consumption can be reduced.

  The controller 120 schedules A / D conversion by the sub A / D converter 112 after A / D conversion by the main A / D converter 102 for each channel. The controller 120 generates a timing signal S7 generated by the controller 120. The digital signal S8, which is output data of the sub A / D converter 112, is input to the arithmetic unit 114.

The calculation unit 114 calculates the slope α based on a pair of the output data S4 of the main A / D converter 102 and the output data S8 of the sub A / D converter 112.
α = (S4-S8) / Δt
Δt is the time difference between the conversion timing by the main A / D converter 102 and the conversion timing by the sub A / D converter 112. The time difference Δt may be provided from the controller 120. Alternatively, when the controller 120 always controls the time difference Δ to be constant, the division by Δt is unnecessary, and (S4-S8) can be used as a value indicating the slope. The arithmetic unit 114 and the controller 120 may be configured by hardware, or may be configured by a microcomputer or a processor controlled by software.

  FIG. 5A is an operation waveform diagram of the A / D converter 100 according to the first configuration example. When the timing signal S3 is asserted, the operation of the main A / D converter 102 starts, and after the conversion period has elapsed, the output data S4 is determined. Subsequently, when the controller 120 asserts the timing signal S7 after the elapse of the time Δt, the sub A / D converter 112 starts operating, and after the elapse of the conversion period, the output data S8 is determined. When the values of the digital signals S4 and S8 are determined, the calculation unit 114 calculates the inclination, and the inclination data S6 is generated.

  In order to detect the inclination, two A / D conversions are required for the same analog signal. By allocating the second of the two A / D conversions to the sub A / D converter 112, the number of empty slots in the main A / D converter 102 can be increased.

(Second configuration example)
A second configuration example will be described with reference to FIG. The operation unit 114 does not receive the output data S4 of the main A / D converter 102 but receives only the output data S8 of the sub A / D converter 112. The controller 120 successively schedules A / D conversion by the sub A / D converter 112 twice for each channel. Then, the arithmetic unit 114 detects the inclination based on the pair of the output data S8_1 and S8_2 of the sub-A / D converter 112 twice.
α = (S8_2-S8_1) / Δt

  FIG. 5B is an operation waveform diagram of the A / D converter 100 according to the second configuration example. The controller 120 asserts the timing signal S7 to instruct the sub A / D converter 112 to perform the first A / D conversion in a situation where the inclination is necessary. As a result, the first output data S8_1 is generated. Subsequently, after the elapse of Δt, the timing signal S7 is asserted to instruct the sub A / D converter 112 to perform the second A / D conversion. As a result, the second output data S8_2 is generated. The operation unit 114 calculates the inclination data S6 from the two output data.

  In the first configuration example, when the time interval of the A / D conversion of the main A / D converter 102 is set to be wide, when the time scale of the fluctuation of the analog signal becomes short during the wide time interval, Response may be delayed. On the other hand, according to the second configuration example, the inclination detection timing can be set freely without being restricted by the A / D conversion timing of the main A / D converter 102, so that a response delay can be suppressed.

  In the second configuration example, similarly to the first configuration example, the inclination may be detected by operating the sub A / D converter 112 twice for each A / D conversion by the main A / D converter 102.

(Third configuration example)
FIG. 6 is a block diagram illustrating a third configuration example of the A / D conversion device 100. In the third configuration example, the sub A / D converter 112 is not provided, and the inclination is obtained using the main A / D converter 102. The main A / D converter 102 is a successive approximation type. The controller 120 schedules the second A / D conversion for inclination detection by the main A / D converter 102 after the original A / D conversion by the main A / D converter 102 for each channel. The second A / D conversion is performed with a smaller number of bits than the first A / D conversion. The inclination detection unit 110 calculates an inclination based on two pairs of output data S4_1 and S4_2 of the main A / D converter 102.

  FIG. 7 is an operation waveform diagram of the A / D converter 100 according to the third configuration example. The controller 120 asserts the timing signal S3 and causes the main A / D converter 102 to generate the digital signal S4_1 in order to perform the original A / D conversion. The digital signal S4_1 is supplied to a subsequent circuit block via the ADC interface 130 and the data register 132 in FIG. After a lapse of Δt, the controller 120 asserts the timing signal S3 again and causes the main A / D converter 102 to generate the digital signal S4_2. In the second A / D conversion, the successive approximation processing is stopped halfway, so that the conversion time τ2 is shorter than the first time τ1. The operation unit 114 calculates the inclination data S6 based on the two output data S4_1 and S4_2.

  According to the third configuration example, since the sub A / D converter 112 is unnecessary, the circuit area can be reduced. Further, in the second A / D conversion, since the operation is performed with a small number of bits, the power consumption can be substantially equal to that of the sub A / D converter.

  Next, the application of the A / D converter 100 will be described. The A / D converter 100 is suitable for use in sensing an electrical state or a physical state in which the time scale of the change dynamically changes. One such application is battery level detection.

FIG. 8 is a block diagram of a battery remaining power detection circuit 200 including the A / D converter 100. The electronic device 300 includes a battery 302, a charging circuit 304, a power supply circuit 306, and a remaining battery level detection circuit 200. Charging circuit 304 receives voltage V _EXT from the outside and charges battery 302. The power supply circuit 306 receives the battery voltage V _BAT or the voltage V _EXT from the outside, boosts or drops the voltage, and supplies the power supply voltage V _DD to a load (not shown). The remaining battery level detection circuit 200 detects a state of charge (SOC) of the battery 302. For example, the battery level detection circuit 200 receives the battery voltage V _BAT , the current detection signal V _CS indicating the charge / discharge current of the battery 302, and the temperature detection signal V _TS indicating the temperature of the battery 302. The current detection signal _VCS is, for example, a voltage drop of the sense resistor _RS inserted in series with the battery 302. The temperature detection signal _VTS is generated by a temperature sensor 308 such as a thermistor or a thermocouple. The remaining battery level detection circuit 200 includes the A / D converter 100 described above. The A / D converter 100 receives the battery voltage V _BAT , the current detection signal V _CS , and the temperature detection signal V _TS and converts them into digital values. That is, the battery voltage V _BAT , the current detection signal V _CS , and the temperature detection signal V _TS correspond to the above-described analog signals V1 to V3.
The arithmetic unit 202 estimates the remaining amount of the battery 302 based on the battery voltage, current value, and temperature measured by the A / D converter 100. There are several methods for estimating the remaining amount of the battery 302. For example, a method based on an open circuit voltage (OCV) measured in a no-load state of the battery, a Coulomb counting method for integrating charging / discharging current, and the like are used. be able to.

The changing speed of the battery voltage V _BAT differs depending on the state of the electronic device 300. For example, when the electronic device 300 is a communication terminal, when the electronic device 300 is operated under a high load, or during rapid charging, the battery voltage V _BAT changes on a short time scale. Conversely, in the non-use state of the electronic device 300, that is, in the sleep state, the changing speed of the battery voltage V _BAT becomes extremely slow. Also, the time scale of the change in temperature changes dynamically.

  Conventionally, the arithmetic unit 202 needs to adjust the timing of A / D conversion according to the change speed of each analog signal. On the other hand, the A / D converter 100 according to the embodiment automatically adjusts the interval of A / D conversion, so that the calculation load of the calculation unit 202 can be reduced.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and changes in arrangement may be made without departing from the spirit of the present invention.

100 A / D converter, 102 Main A / D converter, 104 Multiplexer, 110 Slope detection unit, 112 Sub A / D converter, 114 Operation unit, 120 Controller, 130 ADC interface, 132 Data register, S1: control signal, S2: analog signal, S3: timing signal, S4: digital signal, S5: control signal, S6: slope data, S7: timing signal, S8: digital signal, 200: remaining battery level detection circuit , 202: arithmetic unit, 300: electronic device, 302: battery, 304: charging circuit, 306: power circuit, 308: temperature sensor.

Claims (9)

A multiplexer for receiving a plurality of analog signals,
A main A / D converter for A / D converting the analog signal selected by the multiplexer;
A slope detection unit that detects a slope of each of the plurality of analog signals,
A controller for controlling the multiplexer and the main A / D converter;
With
The controller schedules the next A / D conversion timing of the main A / D converter for each analog signal based on a corresponding slope detected by the slope detection unit ,
The inclination detection unit includes a sub A / D converter for A / D converting the analog signal selected by the multiplexer,
The controller is
For each channel, after A / D conversion by the main A / D converter, schedule the timing of A / D conversion by the sub A / D converter;
An A / D converter, wherein the inclination is detected based on a pair of output data of the main A / D converter and output data of the sub A / D converter .   The A / D converter according to claim 1, wherein the number of bits of the sub A / D converter is smaller than the number of bits of the main A / D converter. A multiplexer for receiving a plurality of analog signals,
A main A / D converter for A / D converting the analog signal selected by the multiplexer;
A slope detection unit that detects a slope of each of the plurality of analog signals,
A controller for controlling the multiplexer and the main A / D converter;
With
The controller schedules the next A / D conversion timing of the main A / D converter for each analog signal based on a corresponding slope detected by the slope detector.
The inclination detection unit includes a sub A / D converter for A / D converting the analog signal selected by the multiplexer,
The sub A / D converter number of bits, the main A / D converter A / D converter you being smaller than the number of bits of the. A multiplexer for receiving a plurality of analog signals,
A main A / D converter for A / D converting the analog signal selected by the multiplexer;
A slope detection unit that detects a slope of each of the plurality of analog signals,
A controller for controlling the multiplexer and the main A / D converter;
With
The controller schedules the next A / D conversion timing of the main A / D converter for each analog signal based on a corresponding slope detected by the slope detector.
The inclination detection unit includes a sub A / D converter for A / D converting the analog signal selected by the multiplexer,
The controller is
A / D conversion by the sub A / D converter is scheduled twice consecutively for each channel,
The sub A / D converter A / D converter you and detecting the inclination on the basis of the two output data pairs. A multiplexer for receiving a plurality of analog signals,
A main A / D converter for A / D converting the analog signal selected by the multiplexer;
A slope detection unit that detects a slope of each of the plurality of analog signals,
A controller for controlling the multiplexer and the main A / D converter;
With
The controller schedules the next A / D conversion timing of the main A / D converter for each analog signal based on a corresponding slope detected by the slope detector.
The main A / D converter is a successive approximation type,
The controller is
For each channel, after the A / D conversion by the main A / D converter, schedule the second A / D conversion by the main A / D converter with a smaller number of bits than the first.
The main A / D converter A / D converter you and detecting the inclination on the basis of the two output data pairs. A / D converter according to any one of to be integrated on a single semiconductor substrate from claim 1, wherein 5. A battery remaining amount detection circuit comprising the A / D converter according to any one of claims 1 to 6 . 8. The method according to claim 7 , wherein the plurality of analog signals input to the multiplexer of the A / D converter include at least a signal indicating a charge / discharge current of a battery and a signal indicating a temperature of the battery. A battery remaining amount detection circuit according to the above. Battery and
A charging circuit for charging the battery;
The battery remaining amount detection circuit according to claim 7 or 8 , wherein the battery remaining amount is detected.
An electronic device comprising:

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