JP6652337B2 - 半導体装置の実装状態の検査方法および実装基板に実装された半導体装置 - Google Patents

半導体装置の実装状態の検査方法および実装基板に実装された半導体装置 Download PDF

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Publication number
JP6652337B2
JP6652337B2 JP2015131486A JP2015131486A JP6652337B2 JP 6652337 B2 JP6652337 B2 JP 6652337B2 JP 2015131486 A JP2015131486 A JP 2015131486A JP 2015131486 A JP2015131486 A JP 2015131486A JP 6652337 B2 JP6652337 B2 JP 6652337B2
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JP
Japan
Prior art keywords
semiconductor device
heat radiating
radiating portion
resistance
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015131486A
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English (en)
Japanese (ja)
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JP2017015519A (ja
JP2017015519A5 (enExample
Inventor
聖明 門井
聖明 門井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Ablic Inc
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Publication date
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Priority to JP2015131486A priority Critical patent/JP6652337B2/ja
Publication of JP2017015519A publication Critical patent/JP2017015519A/ja
Publication of JP2017015519A5 publication Critical patent/JP2017015519A5/ja
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2015131486A 2015-06-30 2015-06-30 半導体装置の実装状態の検査方法および実装基板に実装された半導体装置 Expired - Fee Related JP6652337B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015131486A JP6652337B2 (ja) 2015-06-30 2015-06-30 半導体装置の実装状態の検査方法および実装基板に実装された半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015131486A JP6652337B2 (ja) 2015-06-30 2015-06-30 半導体装置の実装状態の検査方法および実装基板に実装された半導体装置

Publications (3)

Publication Number Publication Date
JP2017015519A JP2017015519A (ja) 2017-01-19
JP2017015519A5 JP2017015519A5 (enExample) 2018-06-21
JP6652337B2 true JP6652337B2 (ja) 2020-02-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015131486A Expired - Fee Related JP6652337B2 (ja) 2015-06-30 2015-06-30 半導体装置の実装状態の検査方法および実装基板に実装された半導体装置

Country Status (1)

Country Link
JP (1) JP6652337B2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023209856A1 (ja) * 2022-04-27 2023-11-02 日立Astemo株式会社 車載制御装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594234A (en) * 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
JP2003297965A (ja) * 2002-03-29 2003-10-17 Toyota Motor Corp 半導体装置およびその製造方法
JP2004325363A (ja) * 2003-04-28 2004-11-18 Matsushita Electric Ind Co Ltd 実装済みプリント基板の検査方法およびプリント基板
JP2008166403A (ja) * 2006-12-27 2008-07-17 Toshiba Corp プリント配線板、プリント回路板、およびプリント回路板の接合部検査方法
US8823407B2 (en) * 2012-03-01 2014-09-02 Integrated Device Technology, Inc. Test assembly for verifying heat spreader grounding in a production test
JP6022546B2 (ja) * 2012-03-30 2016-11-09 昭和電工株式会社 硬化性放熱組成物
JP6121692B2 (ja) * 2012-11-05 2017-04-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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JP2017015519A (ja) 2017-01-19

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