JP6643268B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6643268B2 JP6643268B2 JP2017059842A JP2017059842A JP6643268B2 JP 6643268 B2 JP6643268 B2 JP 6643268B2 JP 2017059842 A JP2017059842 A JP 2017059842A JP 2017059842 A JP2017059842 A JP 2017059842A JP 6643268 B2 JP6643268 B2 JP 6643268B2
- Authority
- JP
- Japan
- Prior art keywords
- clamp circuit
- drain
- gate
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 39
- 230000002457 bidirectional effect Effects 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 7
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/22—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
- H01H47/32—Energising current supplied by semiconductor device
- H01H47/325—Energising current supplied by semiconductor device by switching regulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
- H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1は、本実施形態に係る半導体装置を示す回路図である。
図2は、本実施形態に係る半導体装置を示す平面図である。
図3は、図2の拡大図である。
図1に示すように、半導体装置1においては、MOSFET10が設けられている。MOSFET10には、ドレイン10d、ソース10s、ゲート10gが設けられており、ソース10sとドレイン10dとの間には、ボディダイオード10bが形成されている。ボディダイオード10bのアノードはソース10sに接続され、カソードはドレイン10dに接続されている。
図2に示すように、半導体装置1には、例えば樹脂材料からなる外囲器30が設けられている。ドレイン電極11には、外囲器30の内部に配置された板状のドレインパッド11aと、ドレインパッド11aから外囲器30の外部に引き出されたドレイン端子11bが一体的に設けられている。ソース電極12には、外囲器30の内部に配置された板状のボンディングパッド12aと、ボンディングパッド12aから外囲器の外部に引き出されたソース端子12bが一体的に設けられている。ゲート電極13には、外囲器30の内部に配置された板状のボンディングパッド13aと、ボンディングパッド13aから外囲器の外部に引き出されたゲート端子13bが一体的に設けられている。
図4(a)は、横軸に電圧をとり、縦軸に電流をとって、クランプ回路のV−I特性を示すグラフ図であり、(b)は、横軸にドレイン−ゲート間電圧をとり、縦軸にドレイン−ゲート間電流をとって、本実施形態に係る半導体装置のV−I特性を示すグラフ図である。
図5は、本実施形態に係る半導体装置の使用例を示す回路図である。
図5に示すように、本使用例においては、半導体装置1をメカニカルリレー100のスイッチ回路として使用する。メカニカルリレー100においては、機械式スイッチ101が設けられており、その近傍に、コイル102が設けられている。コイル102には、直流電源103及び半導体装置1が直列に接続されている。また、機械式スイッチ101には一定の力が印加されており、コイル102から磁力が印加されなければ、一方の状態を維持するようになっている。
本実施形態によれば、GD間クランプ回路17に対して並列に、GD間クランプ回路15及びゲート抵抗19を設け、GD間クランプ回路15のクランプ電圧Vclamp1をGD間クランプ回路17のクランプ電圧Vclamp2よりも低く設定している。これにより、GD間クランプ回路17が降伏する前にGD間クランプ回路15が降伏し、ゲート抵抗19を介して少しずつ電流を流すことにより、GD間クランプ回路17の破壊を防止できる。この結果、MOSFET10を確実に保護することができる。このように、本実施形態に係る半導体装置1は、外部から印加される電気的負荷に対する耐性が高い。
Claims (4)
- 電界効果型トランジスタと、
前記電界効果型トランジスタのドレインとゲートとの間に接続され、双方向ダイオードを有し、クランプ電圧が前記電界効果型トランジスタのソース−ドレイン間のブレークダウン電圧よりも低い第1クランプ回路と、
第1端が前記第1クランプ回路と前記ゲートとの間のノードに接続された第1抵抗と、
前記ドレインと前記第1抵抗の第2端との間に接続され、双方向ダイオードを有し、クランプ電圧が前記第1クランプ回路のクランプ電圧よりも高く前記ブレークダウン電圧よりも低い第2クランプ回路と、
を備えた半導体装置。 - 前記第1抵抗と前記第2クランプ回路との間のノードと基準電位との間に接続された第2抵抗をさらに備えた請求項1記載の半導体装置。
- 前記電界効果型トランジスタのソースと前記第2端との間に接続され、双方向ダイオードを有する第3クランプ回路をさらに備えた請求項1または2に記載の半導体装置。
- メカニカルリレーのスイッチ回路である請求項1〜3のいずれか1つに記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017059842A JP6643268B2 (ja) | 2017-03-24 | 2017-03-24 | 半導体装置 |
US15/693,258 US10636728B2 (en) | 2017-03-24 | 2017-08-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017059842A JP6643268B2 (ja) | 2017-03-24 | 2017-03-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018163960A JP2018163960A (ja) | 2018-10-18 |
JP6643268B2 true JP6643268B2 (ja) | 2020-02-12 |
Family
ID=63583578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017059842A Active JP6643268B2 (ja) | 2017-03-24 | 2017-03-24 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10636728B2 (ja) |
JP (1) | JP6643268B2 (ja) |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2792417B2 (ja) * | 1993-12-17 | 1998-09-03 | 日本電気株式会社 | 半導体回路の入力保護回路 |
EP0860947B1 (en) * | 1997-02-19 | 2004-10-13 | STMicroelectronics S.r.l. | Overvoltages protection device for the protection of a power transistor having a MOS control terminal |
US6172383B1 (en) * | 1997-12-31 | 2001-01-09 | Siliconix Incorporated | Power MOSFET having voltage-clamped gate |
JP3255147B2 (ja) * | 1998-06-19 | 2002-02-12 | 株式会社デンソー | 絶縁ゲート型トランジスタのサージ保護回路 |
US6614633B1 (en) * | 1999-03-19 | 2003-09-02 | Denso Corporation | Semiconductor device including a surge protecting circuit |
JP4917709B2 (ja) | 2000-03-06 | 2012-04-18 | ローム株式会社 | 半導体装置 |
JP2004214353A (ja) | 2002-12-27 | 2004-07-29 | Nec Kansai Ltd | 縦型絶縁ゲート電界効果トランジスタ |
JP4866672B2 (ja) | 2006-07-27 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 負荷駆動回路 |
TWI496272B (zh) * | 2006-09-29 | 2015-08-11 | Fairchild Semiconductor | 用於功率金氧半導體場效電晶體之雙電壓多晶矽二極體靜電放電電路 |
US8213142B2 (en) * | 2008-10-29 | 2012-07-03 | Qualcomm, Incorporated | Amplifier with improved ESD protection circuitry |
TWI453893B (zh) * | 2011-08-15 | 2014-09-21 | Faraday Tech Corp | 靜電放電保護電路 |
US9438031B2 (en) * | 2012-02-29 | 2016-09-06 | Freescale Semiconductor, Inc. | Electrostatic discharge protection circuit arrangement, electronic circuit and ESD protection method |
US9013848B2 (en) * | 2012-09-27 | 2015-04-21 | Alpha And Omega Semiconductor Incorporated | Active clamp protection circuit for power semiconductor device for high frequency switching |
JP2014216573A (ja) | 2013-04-26 | 2014-11-17 | 株式会社東芝 | 半導体装置 |
DE102014226690A1 (de) * | 2014-12-19 | 2016-06-23 | Ziehl-Abegg Se | Schutzschaltung für einen Wechselrichter sowie Wechselrichtersystem |
JP6271461B2 (ja) * | 2015-03-09 | 2018-01-31 | 株式会社東芝 | 半導体装置 |
-
2017
- 2017-03-24 JP JP2017059842A patent/JP6643268B2/ja active Active
- 2017-08-31 US US15/693,258 patent/US10636728B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20180277467A1 (en) | 2018-09-27 |
US10636728B2 (en) | 2020-04-28 |
JP2018163960A (ja) | 2018-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9991884B2 (en) | Switching circuits having ferrite beads | |
JP6201422B2 (ja) | 半導体装置 | |
US9041456B2 (en) | Power semiconductor device | |
US9595500B2 (en) | Semiconductor device | |
US9048838B2 (en) | Switching circuit | |
US10277219B2 (en) | Electronic switching and reverse polarity protection circuit | |
US11309884B1 (en) | Switching circuits having drain connected ferrite beads | |
US9196686B2 (en) | Diode circuit and DC to DC converter | |
US20160248422A1 (en) | Switching circuit, semiconductor switching arrangement and method | |
US10128829B2 (en) | Composite semiconductor device | |
JP6643268B2 (ja) | 半導体装置 | |
US20230412167A1 (en) | Power Electronic Module Comprising a Gate-Source Control Unit | |
WO2016157813A1 (ja) | 負荷駆動装置 | |
JP2016046923A (ja) | 半導体装置 | |
US11398473B2 (en) | Semiconductor device | |
JP2019161495A (ja) | 半導体装置および装置 | |
JP2023041166A (ja) | 半導体装置 | |
US20160233209A1 (en) | Semiconductor device | |
JP2017123359A (ja) | 半導体装置 | |
JP2012222280A (ja) | 半導体装置及びdc−dcコンバータ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20171116 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20171117 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20181130 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20190925 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191002 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191127 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20191206 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200106 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6643268 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |