JP6591741B2 - Multi-display device, display, and image display method - Google Patents

Description

  The present invention relates to a multi-display device that displays an image using a plurality of displays, a single display, and a method for displaying an image using the multi-display device.

  There are multi-display devices in which a plurality of displays are arranged two-dimensionally to form a larger screen display. Each display displays an image, so that one large image obtained by combining a plurality of images is displayed on the multi-display device. Patent Document 1 discloses an example of a multi-display device.

  An image displayed on the display is composed of a plurality of pixels arranged vertically and horizontally. More specifically, in the image, a plurality of pixel lines in which a plurality of pixels are arranged in the horizontal direction are arranged in the vertical direction. When an image is displayed on the display, each pixel line is sequentially displayed. More specifically, the pixels included in the pixel line at one end are displayed, then the pixels included in the adjacent second pixel line are displayed, each pixel line is displayed sequentially, and finally the other end The pixels included in the pixel line are displayed. For this reason, a time difference occurs between the time points when the two pixel lines are displayed. Assuming that the number of pixel lines included in the image is N, the time difference between the time points when the two pixel lines are displayed is the first pixel line that exists at one end of the plurality of pixel lines and is displayed at the other end. It becomes the largest among the Nth pixel lines that exist and are displayed last.

JP 2010-156846 A

  In the multi-display device in which a plurality of displays are arranged vertically, the first pixel included in the image displayed by the Nth pixel line included in the image displayed by one display and the image displayed by the other display at the boundary portion between two adjacent displays. The pixel line is in close proximity. When an image is displayed on the multi-display device, the boundary between the two displays has a large time difference in which the adjacent first pixel line and the Nth pixel line are displayed, resulting in image disturbance. In particular, when a moving image is displayed on a multi-display device, an image shift occurs at the boundary between two displays.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a multi-display device, a display, and an image display method that prevent the occurrence of image disturbance at the boundary portion of the display. There is.

In the multi-display device according to the present invention, a plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged at least in the vertical direction, Each display is a multi-display device that sequentially displays each pixel line when displaying an image. Each display has a plurality of elements arranged in a matrix to display each pixel included in the image. A circuit including first to Nth signal lines respectively connected to a plurality of elements corresponding to first to Nth pixel lines arranged in order in the vertical direction, where N is the number of pixel lines included. And a driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines, wherein the driver 1 to N for supplying the operation signal to each of the signal lines, and 1st to Nth shift registers, and H is N / 2 or (N + 1) / An n-th shift register in which n is an integer of 2 and n is an integer of 1 to N is used to supply the operation signal to the (H− (n−1) / 2) -th signal line. The nth shift register connected to the (H− (n−1) / 2) th supply unit and n is an even number supplies the operation signal to the (H + n / 2) th signal line. the (H + n / 2) is connected to the supply portion of the for, when display of the image, sequentially trigger signal to the shift register from the first through n are input, the n is an odd number When the trigger signal is input, the n shift register is connected to the (H− (n−1) / 2) supply unit. If the (H- (n-1) / 2) to the signal line to supply the operating signal, the shift register of the n n is an even number, that the trigger signal is input, the first (H + By supplying the operation signal to the (H + n / 2) signal line in the (n / 2) supply unit, the H pixel line is displayed first, and the first pixel from the H pixel line is displayed first. Each pixel line is sequentially displayed toward the pixel line and the Nth pixel line.

In the multi-display device according to the present invention, a plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged at least in the vertical direction, Each display is a multi-display device that sequentially displays each pixel line when displaying an image. Each display has a plurality of elements arranged in a matrix to display each pixel included in the image. A circuit including first to Nth signal lines respectively connected to a plurality of elements corresponding to first to Nth pixel lines arranged in order in the vertical direction, where N is the number of pixel lines included. And a driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines, wherein the driver 1st to Nth supply parts for supplying the operation signal to each of the signal lines up to 1st to 1st to Nth connected to the 1st to Nth supply parts, respectively. Shift registers, wherein H is an integer of N / 2 or (N + 1) / 2, n is an integer of 1 to (N-1), and n is an odd number (H- (n-1 ) / 2) is connected to the (H + (n + 1) / 2) th shift register, and the (H + n / 2) th shift register in which n is an even number is the (H−n / 2) th shift register. The (H- (n-1) / 2) shift register, which is connected to the shift register, is first input with a trigger signal to the H-th shift register at the time of image display, and n is an odd number. The (H + (n + 1) / 2) shift register when the trigger signal is input The trigger signal is input, and the operation signal is supplied to the (H- (n-1) / 2) -th signal line by the (H- (n-1) / 2) -th supply unit, where n is an even number. When the trigger signal is input, the (H + n / 2) th shift register inputs the trigger signal to the (H−n / 2) th shift register, and the (H + n / 2) th shift register. By supplying the operation signal to the (H + n / 2) th signal line in the supply unit, the Hth pixel line is displayed first, and the first pixel line and the Nth pixel from the Hth pixel line are displayed. Each pixel line is displayed sequentially toward the line .

The display according to the present invention is a display that sequentially displays each pixel line in order to display an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction. A plurality of elements for displaying each pixel included are arranged in a matrix, and the number of pixel lines included in the image is N, and each of the first to Nth pixel lines sequentially arranged in the vertical direction is provided. A circuit including first to Nth signal lines respectively connected to a plurality of elements corresponding to, and an operation signal for operating the plurality of elements to each of the first to Nth signal lines. A driver for supplying, the driver including first to Nth supply units for supplying the operation signal to each of the first to Nth signal lines; With shift register An nth shift register in which n is an odd number, where H is an integer that is N / 2 or (N + 1) / 2, n is an integer that is 1 or more and N or less, is (H− (n−1) / 2). The nth shift register connected to the (H− (n−1) / 2) th supply unit for supplying the operation signal to the signal line, and n is an even number, is (H + n / 2). Are connected to the (H + n / 2) supply section for supplying the operation signal to the signal line of the first, and when the image is displayed, the trigger signals are sequentially supplied to the first to Nth shift registers. And n is an odd number, the nth shift register receives the (H− (n−)) to the (H− (n−1) / 2) supply unit when the trigger signal is input. -1) / 2) The operation signal is supplied to the signal line, and the trigger signal is input to the nth shift register in which n is an even number. If it is, by supplying the first (H + n / 2) the operation signal to the signal line of the first (H + n / 2) in the supply portion of the pixel line of the H is displayed first The pixel lines are sequentially displayed from the Hth pixel line toward the first pixel line and the Nth pixel line.

Display according to the present invention, in order to display an image in which a plurality of pixel lines in which a plurality of pixels respectively are arranged in the lateral direction is arranged in the longitudinal direction, in a display to sequentially display each pixel line, to the image A plurality of elements for displaying each pixel included are arranged in a matrix, and the number of pixel lines included in the image is N, and each of the first to Nth pixel lines sequentially arranged in the vertical direction is provided. A circuit including first to Nth signal lines respectively connected to a plurality of elements corresponding to, and an operation signal for operating the plurality of elements to each of the first to Nth signal lines. A driver for supplying, the driver including first to Nth supply units for supplying the operation signal to each of the first to Nth signal lines, and the first to Nth One-to-one contact with the supply section N is an odd number, where H is an integer of N / 2 or (N + 1) / 2, n is an integer of 1 to (N-1), and n is an odd number. The (H− (n−1) / 2) th shift register is connected to the (H + (n + 1) / 2) th shift register, and the (H + n / 2) th shift register where n is an even number The (H−n / 2) shift register is connected, and when an image is displayed, a trigger signal is first input to the Hth shift register, and n is an odd number (H− (n−1). ) / 2) shift register inputs the trigger signal to the (H + (n + 1) / 2) th shift register when the trigger signal is input, and (H− (n−1) / 2) supplying the operation signal to the (H− (n−1) / 2) th signal line in the supply unit; The (H + n / 2) shift register having an even number inputs the trigger signal to the (H−n / 2) shift register when the trigger signal is input, and (H + n / The operation signal is supplied to the (H + n / 2) th signal line by the supply unit 2), whereby the Hth pixel line is displayed first, and the first pixel line and the first pixel line are displayed from the Hth pixel line. Each pixel line is sequentially displayed toward N pixel lines .

In the image display method according to the present invention, a plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged at least in the vertical direction, Each display is a multi-display device that sequentially displays each pixel line when displaying an image. In the method for displaying an image, each display has a plurality of elements for displaying each pixel included in the image in a matrix. The first to Nth elements are arranged and connected to a plurality of elements corresponding to the first to Nth pixel lines arranged in the vertical direction, where N is the number of pixel lines included in the image. A circuit including a plurality of signal lines, and a driver that supplies an operation signal for operating the plurality of elements to each of the first to Nth signal lines. A first to Nth supply section for supplying the operation signal to each of the first to Nth signal lines; and a first to Nth shift register; Alternatively, an integer that is (N + 1) / 2, where n is an integer that is greater than or equal to 1 and less than or equal to N, when an image is displayed, a trigger signal is sequentially input to the first to Nth shift registers, and n is an odd number When the trigger signal is input, the nth shift register connects the (H− (n−1) / 2) th supply line to the (H− (n−1) / 2) th supply line. to supply the operation signal, the shift register of the n n is an even number, when the trigger signal is input, the (H + n / 2) signal of the (H + n / 2) to the supply of By supplying the operation signal to the line, the H-th pixel line is displayed first, and the H-th pixel line is displayed. Wherein the sequentially display each pixel line toward the pixel line of the first pixel line and the N.

In the image display method according to the present invention, a plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged at least in the vertical direction, Each display is a multi-display device that sequentially displays each pixel line when displaying an image. In the method for displaying an image, each display has a plurality of elements for displaying each pixel included in the image in a matrix. The first to Nth elements are arranged and connected to a plurality of elements corresponding to the first to Nth pixel lines arranged in the vertical direction, where N is the number of pixel lines included in the image. A circuit including a plurality of signal lines, and a driver that supplies an operation signal for operating the plurality of elements to each of the first to Nth signal lines. First to Nth supply sections for supplying the operation signal to each of the first to Nth signal lines, and first to Nth supply sections connected to the first to Nth supply sections on a one-to-one basis. 1 to N shift registers, H is an integer that is N / 2 or (N + 1) / 2, and n is an integer that is greater than or equal to 1 and less than or equal to (N−1). When a trigger signal is first input to the shift register and n is an odd number, the (H− (n−1) / 2) th shift register has an (H + (n + 1) / The trigger signal is input to the shift register 2), and the operation signal is supplied to the (H- (n-1) / 2) signal line to the (H- (n-1) / 2) supply unit. The (H + n / 2) th shift register in which n is an even number is the (H−n−2) th shift register when the trigger signal is input. / 2) of the shift register inputs the trigger signal, the (by supplying H + n / 2) the operation signal to the signal line of the (H + n / 2) in the supply portion of the first pixel line of the H The pixel lines are sequentially displayed from the H-th pixel line toward the first pixel line and the N-th pixel line .

  In the present invention, the multi-display device can display an image without disturbance at a boundary portion between a plurality of displays, and can prevent the occurrence of image shift even when displaying a moving image. It has excellent effects such as being possible.

It is a block diagram which shows the structure of a multi-display apparatus. It is a block diagram which shows the structure of a display. It is a typical circuit diagram which shows the structure of an active matrix circuit. It is a block diagram which shows the structure of the conventional gate driver. It is a timing chart which shows typically the supply timing of the signal to each gate line in the conventional multi display device. It is a schematic diagram which shows the example of the image displayed with a multi-display apparatus. It is a schematic diagram which shows a mode that the display state of each pixel changes, when the image switches in the conventional multi-display apparatus. 2 is a block diagram illustrating a configuration of a gate driver according to Embodiment 1. FIG. 3 is a timing chart schematically showing the timing of supplying signals to each gate line in the multi-display device according to the first embodiment. FIG. 3 is a schematic diagram illustrating how the display state of each pixel changes when images are switched in the multi-display device according to the first embodiment. FIG. 6 is a block diagram illustrating a configuration of a gate driver according to a second embodiment. FIG. 10 is a block diagram illustrating a configuration of a gate driver according to a third embodiment. 10 is a timing chart schematically showing timing for supplying signals to each gate line in the multi-display device according to the third embodiment. FIG. 10 is a schematic diagram illustrating how the display state of each pixel changes when an image is switched in the multi-display device according to the third embodiment.

Hereinafter, the present invention will be specifically described with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration of a multi-display device. The multi-display device is an information display that is installed in, for example, a store or a public space, and displays images representing various types of information such as news or advertisements. The multi-display device includes a plurality of displays 1. The display 1 is a liquid crystal display that displays an image using a liquid crystal panel, and is formed in a rectangular shape when viewed from the front. The plurality of displays 1 are arranged at least in the vertical direction with the same image display direction, and form a rectangle as a whole. A combination of a plurality of displays 1 constitutes a huge rectangular display. Although the figure shows an example in which three displays 1 are arranged vertically, the multi-display device may have a form in which two displays 1 are arranged, and four or more displays 1 are arranged. Form may be sufficient. In addition, the multi-display device may have a form in which a plurality of displays 1 are arranged in the horizontal direction.

  The multi-display apparatus includes an input unit 22 for inputting image data from the outside and an image processing unit 21 for performing image processing. Each of the plurality of displays 1 is connected to the image processing unit 21. The image processing unit 21 enlarges the size of the image represented by the image data input to the input unit 22 and divides the enlarged image into a plurality of partial images. Each of the plurality of partial images is an image to be displayed on any one of the plurality of displays 1. The image processing unit 21 inputs data representing a partial image to be displayed on each display 1 to each display 1.

  FIG. 2 is a block diagram showing the configuration of the display 1. The display 1 includes a liquid crystal panel 11 and a backlight 14 disposed behind the liquid crystal panel 11. The liquid crystal panel 11 is illuminated by the backlight 14 from behind and displays an image. The liquid crystal panel 11 includes a liquid crystal layer, a color filter, an electrode layer and an active matrix circuit for applying a voltage to the liquid crystal layer, and two polarizing plates.

  FIG. 3 is a schematic circuit diagram showing the configuration of the active matrix circuit. In the active matrix circuit 110, a plurality of signal lines are wired in a grid pattern. A plurality of pixel electrodes 31 for applying a voltage to the liquid crystal corresponding to the pixels are arranged in a matrix. Each pixel electrode 31 corresponds to an intersection of signal lines. Each pixel electrode 31 is connected to an active element 32 such as a TFT (thin film transistor). Each active element 32 is connected to two signal lines intersecting each pixel electrode 31 at a corresponding intersection. When the active element 32 is a TFT, the gate of the active element 32 is connected to the signal line along the horizontal direction, and the source of the active element 32 is connected to the signal line along the vertical direction. A signal line along the horizontal direction is called a gate line, and a signal line along the vertical direction is called a source line. The number of pixels included in the image displayed on the display 1 is N in the vertical direction and M in the horizontal direction. N pixel electrodes 31 and active elements 32 are arranged in the vertical direction and M in the horizontal direction. Also, N gate lines 331 to 33N are wired in parallel, and M source lines 341 to 34M are wired in parallel. When a signal flows through any one of the gate line and the source line, the active element 32 connected to the gate line and the source line is turned on, the pixel electrode 31 connected to the active element 32 operates, and a voltage is applied to the liquid crystal. Apply. Each gate line is connected to a plurality of pixel electrodes 31 corresponding to a plurality of pixels included in each pixel line included in an image to be displayed on the display 1 via an active element 32. When a signal flows through one gate line and a signal flows through each source line in parallel, the pixel electrode 31 corresponding to the pixel included in the one pixel line operates to display one pixel line.

  The display 1 includes a gate driver 12 connected to a plurality of gate lines and a source driver 13 connected to a plurality of source lines. The gate driver 12 generates signals to be supplied to a plurality of gate lines, and sequentially supplies the generated signals to the respective gate lines. The source driver 13 generates signals to be supplied to a plurality of source lines, and sequentially supplies the generated signals to each source line. The display 1 includes a control unit 16 and a timing controller 15 that controls the display timing of the image. The timing controller 15 is connected to the control unit 16 and is connected to the gate driver 12 and the source driver 13. The control unit 16 is connected to the image processing unit 21 and receives data representing a partial image from the image processing unit 21. The control unit 16 adjusts the input data and inputs the adjusted data to the timing controller 15. The timing controller 15 converts the data input from the control unit 16 into driving signals for the gate driver 12 and the source driver 13, and inputs the driving signals to the gate driver 12 and the source driver 13. The gate driver 12 and the source driver 13 are driven according to the driving signal, the pixel electrode 31 corresponding to each pixel operates, each pixel is displayed, and an image is displayed.

  The display 1 includes a power supply unit 18 and a backlight driver 17 that supplies power to the backlight 14. The power supply unit 18 is supplied with power from a power source (not shown) included in the multi-display device or a power source outside the multi-display device. The power supply unit 18 supplies driving power to the backlight driver 17, the control unit 16, the timing controller 15, the gate driver 12, and the source driver 13. The backlight driver 17 converts the power from the power supply unit 18 into power for lighting the backlight 14 and supplies the converted power to the backlight 14.

  A conventional image display method using a conventional multi-display device will be described. FIG. 4 is a block diagram showing a configuration of a conventional gate driver. N is an even number, and N / 2 = H. The gate driver includes N shift registers (SR), a level shifter (LS), and a supply unit. A clock signal is input from the timing controller to each shift register, and a trigger signal is input to the first shift register 711. The shift register 711 inputs a signal to the first level shifter 721 in response to the input of the trigger signal. The level shifter 721 converts the level of the input signal and inputs it to the first supply unit 731, and the supply unit 731. Supplies a signal to the first gate line. The first gate line is connected to a plurality of pixel electrodes corresponding to a plurality of pixels included in a first pixel line included in an image to be displayed on a display via an active element. In a state where a signal is supplied to the first gate line, the source driver supplies a signal to each source line. Thereby, the pixel electrode connected to the first gate line via the active element operates, and the pixels included in the first pixel line are displayed. Thus, the first pixel line is displayed.

  The shift register 711 inputs a trigger signal to the second shift register 712. The shift register 712 inputs a signal to the second level shifter 722, the level shifter 722 inputs the signal to the second supply unit 732, and the supply unit 732 supplies the signal to the second gate line. As a result, the second pixel line is displayed. Similarly, assuming that n is a natural number from 1 to N, the (n−1) th shift register inputs a trigger signal to the nth shift register, and the nth shift register sends the signal to the nth level shifter. The nth level shifter inputs a signal to the nth supply unit, and the nth supply unit supplies a signal to the nth gate line. As a result, the nth pixel line is displayed. As described above, the first pixel line to the Nth pixel line are displayed in order, and as a result, an image is displayed on the display. Images are displayed in the same manner on each of the plurality of displays.

  FIG. 5 is a timing chart schematically showing signal supply timing to each gate line in the conventional multi-display device. It is assumed that the first display and the second display are arranged in the vertical direction, and the signal supply timing to each gate line in each display is shown. The horizontal axis in the figure is time, and the state in which a signal is supplied to the gate line is indicated by high on the vertical axis. In each of the first and second displays, when an image is displayed, signals are sequentially supplied from the first gate line to the Nth gate line, and from the first pixel line corresponding to each gate line. The images are sequentially displayed up to the Nth pixel line. On the screen of the multi-display device, the Nth pixel line displayed by the first display and the first pixel line displayed by the second display are close to each other. As shown in FIG. 5, the first gate line and the Nth gate line are greatly different in the timing at which signals are supplied, so the Nth pixel line displayed on the first display and the first display displayed on the second display. A large time difference occurs between the time points when the pixel lines are displayed.

  FIG. 6 is a schematic diagram illustrating an example of an image displayed on the multi-display device. The image is composed of images displayed on the first and second displays, respectively, and the image displayed on each display is composed of N × M pixels. FIG. 6A is an image of one frame when displaying a moving image in which a vertical straight line moves in the horizontal direction on the multi-display device. The image shown in FIG. 6A is composed of vertical straight lines. FIG. 6B is an image of the next frame of the image shown in FIG. 6A. In FIG. 6B, the position of the pixel displaying the straight line is different from that in FIG. 6A. When the moving image is displayed, the image shown in FIG. 6A is switched to the image shown in FIG. 6B.

  FIG. 7 is a schematic diagram showing how the display state of each pixel changes when an image is switched in a conventional multi-display device. FIG. 7A shows a state in which the first pixel line has changed. Since an image is sequentially displayed from the first pixel line to the Nth pixel line when an image is displayed, the first pixel line is changed first. That is, the position of the pixel displaying the straight line on the first pixel line changes, while the position of the pixel displaying the straight line on the other pixel lines does not change. At the boundary between the first and second displays, the position of the pixel displaying a straight line is between the Nth pixel line displayed on the first display and the first pixel line displayed on the second display. It's off. FIG. 7B shows a state where the pixel line has changed second. Following the first pixel line, the second pixel line changes. Similarly, each pixel line changes sequentially. FIG. 7C shows a state in which the pixel line has changed in the (N-1) th. From the first pixel line to the (N−1) th pixel line, the position of the pixel displaying a straight line on the pixel line has changed, and the position of the pixel still displaying a straight line on the Nth pixel line Has not changed. Even in this state, the position of the pixel displaying the straight line is shifted between the Nth pixel line displayed on the first display and the first pixel line displayed on the second display. Finally, the Nth pixel line changes, and the images are switched as shown in FIG. 6B.

  As shown in FIG. 7, in the conventional multi-display device, when an image is switched, an image is displayed between the Nth pixel line displayed on the first display and the first pixel line displayed on the second display. The position of the current pixel is shifted for a long time. Since the displacement of the pixel position occurs for a long time, an image disturbance that can be recognized by human eyes occurs. Accordingly, when a moving image is displayed on a conventional multi-display device, an image shift occurs at the boundary portion of the display.

  In the multi-display device according to this embodiment, the display order of the pixel lines on each display is different from the conventional order, thereby preventing the position of the pixel displaying the image from shifting between adjacent pixel lines for a long time. . FIG. 8 is a block diagram illustrating a configuration of the gate driver 12 according to the first embodiment. Each component of the gate driver 12 operates with power supplied from the power supply unit 18. From the timing controller 15, a clock signal is input to each shift register, a trigger signal is input to the first shift register 41, and a trigger signal is sequentially input from the second shift register 42 to the Nth shift register 4N. It has come to be. The shift register 41 is connected to the H-th level shifter 5H. Therefore, the shift register 41 inputs a signal to the level shifter 5H, the level shifter 5H inputs a signal to the Hth supply unit 6H, and the supply unit 6H supplies a signal to the Hth gate line 33H. Therefore, in the display 1 according to the present embodiment, a signal is first supplied to the gate line 33H among the N gate lines, and the Hth pixel line is displayed first among the N pixel lines.

  The second shift register 42 is connected to the (H + 1) th level shifter 5 (H + 1). Therefore, the shift register 42 inputs a signal to the level shifter 5 (H + 1), and finally a signal is supplied to the (H + 1) th gate line 33 (H + 1). The third shift register 43 is connected to the (H-1) th level shifter 5 (H-1). Therefore, the shift register 43 inputs a signal to the level shifter 5 (H−1), and finally the signal is supplied to the (H−1) th gate line 33 (H−1). Although not shown, the fourth shift register is connected to the (H + 2) level shifter, and the fifth shift register is connected to the (H-2) level shifter. The (N-1) th shift register 4 (N-1) is connected to the first level shifter 51, and the Nth shift register 4N is connected to the Nth level shifter 5N. For this reason, a signal is supplied to the first gate line 331 second from the end, and finally a signal is supplied to the Nth gate line 33N. In this way, the gate driver 12 first supplies a signal to the gate line 33H located at the middle of both ends of the N gate lines wired in parallel, and the gate line closer to the gate line 3N at one end A signal is sequentially supplied to each gate line from the gate line 33H toward the gate line 331 and the gate line 33N while alternately supplying a signal to the gate line on the side close to the gate line 331 at the other end. ing. A signal is supplied to each gate line in the order as described above, each pixel line is displayed, and an image is displayed on the display 1.

  FIG. 9 is a timing chart schematically showing the timing of supplying signals to the gate lines in the multi-display device according to the first embodiment. The signal supply timing to each gate line in the first and second displays 1 arranged vertically is shown. The horizontal axis in the figure is time, and the state in which a signal is supplied to the gate line is indicated by high on the vertical axis. A signal is first supplied to the gate line 33H corresponding to the H-th pixel line, and the signal is alternately supplied to the gate line close to the gate line 33N and the gate line close to the gate line 331. A signal is sequentially supplied to each gate line toward the gate line 33N. The display 1 sequentially displays pixel lines corresponding to the gate lines. The gate line 331 and the gate line 33N are very close in timing for supplying signals. For this reason, the time difference at the time of display is very small between the Nth pixel line which the 1st display 1 displays, and the 1st pixel line 1 which the 2nd display 1 displays.

  FIG. 10 is a schematic diagram illustrating a state in which the display state of each pixel changes when an image is switched in the multi-display apparatus according to the first embodiment. FIG. 10 shows a display state when an image composed of vertical straight lines is switched as shown in FIG. FIG. 10A shows a state in which the first pixel line has changed from the state shown in FIG. 6A. First, the Hth pixel line changes. While the position of the pixel displaying a straight line on the Hth pixel line changes, the position of the pixel displaying a straight line does not change on the other pixel lines. Pixels displaying a straight line between the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1 at the boundary between the first and second displays 1 The position of is not off. FIG. 10B shows a state where the pixel line has changed second. Following the Hth pixel line, the (H + 1) th pixel line changes. FIG. 10C shows a state where the pixel line is changed third. Subsequently, the (H-1) th pixel line changes. Similarly, the pixel line closer to the Nth pixel line and the pixel line closer to the first pixel line are alternately changed, and each pixel is sequentially shifted toward the first pixel line and the Nth pixel line. The line changes.

  FIG. 10D shows a state in which the pixel line has changed in the (N−2) th. From the second pixel line to the (N−1) th pixel line, the position of the pixel displaying a straight line on the pixel line is changed. Even in this state, the position of the pixel displaying the straight line is not shifted between the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1. FIG. 10E shows a state where the pixel line has changed in the (N-1) th. The position of the pixel displaying the straight line on the first pixel line changes, and a straight line is formed between the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1. The position of the pixel displaying is shifted. Next, as shown in FIG. 6B, the position of the pixel displaying a straight line on the Nth pixel line is changed, and the Nth pixel line displayed on the first display 1 and the second display 1 are displayed. The displacement of the pixel position from the first pixel line is eliminated.

  As shown in FIG. 10, although the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1 are close to each other, the image is displayed when the image is switched. The displacement of the position of the pixel being eliminated is eliminated in a very short time. In addition, the displacement of the position of the pixel displaying the image can be eliminated in a very short time between other adjacent pixel lines. Therefore, it is possible to prevent the position of the pixel displaying an image from being shifted between adjacent pixel lines for a long time.

  As described above in detail, the multi-display device according to the present embodiment displays the image in which the plurality of pixel lines are arranged in the vertical direction on each display 1, at approximately the center of the N pixel lines. The first pixel line and the Nth pixel line are displayed while the H-th pixel line is first displayed, and the pixel line closer to the N-th pixel line and the pixel line closer to the first pixel line are alternately displayed. Each pixel line is displayed sequentially toward. Thus, by making the display order of each pixel line different from the conventional one, the time difference between the time points when the display 1 displays the first pixel line and the Nth pixel line becomes very small. At the boundary between two displays 1 arranged vertically, the Nth pixel line of one display 1 and the first pixel line of the other display 1 are close to each other, but the first pixel line and the Nth pixel line Since the time difference between the time points at which is displayed is small, there is no disturbance of the image that can be recognized by human eyes. In addition, when switching the image to be displayed on the multi-display device, such as when displaying a moving image, the position of the pixel displaying the image between the adjacent pixel lines at the boundary portion of the display 1 is prevented from shifting for a long time. . For this reason, the shift of the position of the pixel displaying the image is not recognized by the user. Therefore, the multi-display apparatus according to the present embodiment can display an image without disturbance, and can prevent the occurrence of image shift even when displaying a moving image.

(Embodiment 2)
FIG. 11 is a block diagram illustrating a configuration of the gate driver 12 according to the second embodiment. The configuration other than the gate driver 12 of the multi-display device is the same as that of the first embodiment. A trigger signal is input from the timing controller 15 to the H-th shift register 4H, the shift register 4H inputs a signal to the H-th level shifter 5H, and the level shifter 5H inputs the signal to the H-th supply unit 6H for supply. The unit 6H supplies a signal to the Hth gate line 33H. Therefore, also in the display 1 according to the present embodiment, a signal is first supplied to the gate line 33H among the N gate lines, and the Hth pixel line is displayed first among the N pixel lines.

  The shift register 4H is connected to the (H + 1) th shift register 4 (H + 1), and inputs a trigger signal to the shift register 4 (H + 1). The shift register 4 (H + 1) inputs a signal to the (H + 1) th level shifter 5 (H + 1), and finally the signal is supplied to the (H + 1) th gate line 33 (H + 1). The shift register 4 (H + 1) is connected to the (H-1) th shift register 4 (H-1), and inputs a trigger signal to the shift register 4 (H-1). In this way, the plurality of shift registers input the trigger signal alternately from the shift register 4H to the shift register closer to the Nth shift register 3N and the shift register closer to the first shift register 41. These are connected to each other so as to sequentially input trigger signals toward the shift register 41 and the shift register 3N. The second shift register 42 inputs a trigger signal to the (N−1) th shift register 4 (N−1), and the shift register 4 (N−1) inputs a trigger signal to the first shift register 41. The shift register 41 inputs a trigger signal to the Nth shift register 4N.

  Since the shift registers are connected as described above, also in the present embodiment, a signal is first supplied to the gate line 33H and is close to the Nth gate line 33N toward the gate line 331 and the gate line 33N. While signals are alternately supplied to the gate line on the side and the gate line on the side close to the first gate line 331, signals are sequentially supplied to the gate lines. Accordingly, in the present embodiment as well, as in the first embodiment, the display 1 is positioned approximately at the center of the N pixel lines when displaying an image in which a plurality of pixel lines are arranged in the vertical direction. The H-th pixel line is displayed first, and the pixel line closer to the N-th pixel line and the pixel line closer to the first pixel line are alternately displayed toward the first pixel line and the N-th pixel line. Sequentially display each pixel line.

  Also in the present embodiment, the time difference between the time points when the display 1 displays the first pixel line and the Nth pixel line becomes very small, and image disturbance occurs at the boundary between the two displays 1 arranged vertically. do not do. Further, when switching the image to be displayed on the multi-display device, it is possible to prevent the position of the pixel displaying the image from being shifted between adjacent pixel lines for a long time. Therefore, also in the present embodiment, the multi-display device can display an image without disturbance, and can prevent the occurrence of image shift even when displaying a moving image.

  Note that the configuration of the gate driver 12 in the first and second embodiments is an example, and as long as the order in which the pixel lines are displayed is the order shown in the first and second embodiments, the configuration of the gate driver 12 is the other configuration. May be. For example, the gate driver 12 may have a configuration in which wirings between the plurality of level shifters and the plurality of supply units are different from the conventional one.

(Embodiment 3)
FIG. 12 is a block diagram illustrating a configuration of the gate driver 12 according to the third embodiment. The configuration other than the gate driver 12 of the multi-display device is the same as that of the first embodiment. From the timing controller 15, a clock signal is input to each shift register, a trigger signal is input to the first shift register 41, and a trigger signal is sequentially input from the second shift register 42 to the Nth shift register 4N. It has come to be. The shift register 41 inputs a signal to the first level shifter 51, the level shifter 51 inputs a signal to the supply unit 61, and the supply unit 61 supplies a signal to the first gate line 331. Therefore, in the display 1 according to the present embodiment, a signal is first supplied to the gate line 331, and the first pixel line is first displayed among the N pixel lines.

  The second shift register 42 is connected to the Nth level shifter 5N. Therefore, the shift register 42 inputs a signal to the level shifter 5N, and finally the signal is supplied to the Nth gate line 33N. The third shift register 43 is connected to the second level shifter 52. Therefore, the shift register 43 inputs a signal to the level shifter 52 and finally a signal is supplied to the second gate line 332. Although not shown, the fourth shift register is connected to the (N−1) th level shifter 5 (N−1). The (N-1) th shift register 4 (N-1) is connected to the Hth level shifter 5H, and the Nth shift register 4N is connected to the (H + 1) th level shifter 5 (H + 1). For this reason, the signal is supplied to the gate line 33H second from the end, and finally the signal is supplied to the gate line 33 (H + 1). Thus, the gate driver 12 first supplies a signal to the gate line 331 at one end of the N gate lines wired in parallel, and then supplies the signal to the gate line 33N at the other end. From the gate line 331 and the gate line 33N toward the central gate line, signals are alternately supplied to the gate line on the side close to the gate line 331 on one end and the gate line on the side close to the gate line 33N on the other end. However, a signal is supplied to each gate line. A signal is supplied to each gate line in the order as described above, each pixel line is displayed, and an image is displayed on the display 1.

  FIG. 13 is a timing chart schematically showing the timing of supplying signals to the gate lines in the multi-display device according to the third embodiment. The signal supply timing to each gate line in the first and second displays 1 arranged vertically is shown. The horizontal axis in the figure is time, and the state in which a signal is supplied to the gate line is indicated by high on the vertical axis. A signal is first supplied to the gate line 331 corresponding to the first pixel line, a signal is then supplied to the gate line 33N corresponding to the Nth pixel line, and the gate line 331 near the gate line 331 and the gate line 33N are supplied. While signals are alternately supplied to the closer gate lines, signals are sequentially supplied to the gate lines toward the central gate line. The display 1 sequentially displays pixel lines corresponding to the gate lines. Also in this embodiment, the gate line 331 and the gate line 33N are very close in timing for supplying signals. For this reason, the time difference between the time points when the Nth pixel line displayed on the first display 1 and the first pixel line 1 displayed on the second display 1 are displayed is very small.

  FIG. 14 is a schematic diagram illustrating how the display state of each pixel changes when an image is switched in the multi-display apparatus according to the third embodiment. FIG. 14A shows a state in which the first pixel line has changed from the state shown in FIG. 6A. First, the first pixel line changes. While the position of the pixel displaying the straight line on the first pixel line changes, the position of the pixel displaying the straight line on the other pixel line does not change. Pixels displaying a straight line between the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1 at the boundary between the first and second displays 1 Is out of position. FIG. 14B shows a state where the pixel line has changed second. Following the first pixel line, the Nth pixel line changes. At this time, the displacement of the pixel position between the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1 is eliminated.

  FIG. 14C shows a state where the pixel line is changed third. Subsequently, the second pixel line changes. Similarly, a pixel line closer to the first pixel line and a pixel line closer to the Nth pixel line alternately change from the first pixel line and the Nth pixel line toward the central pixel line. However, each pixel line changes sequentially. FIG. 14D shows a state in which the pixel line has changed in the (N−2) th. From the first pixel line to the (H-1) pixel line, and further from the (H + 2) pixel line to the Nth pixel line, the position of the pixel displaying a straight line on the pixel line is changed. FIG. 14E shows a state where the pixel line has changed in the (N-1) th. The Hth pixel line changes. Next, as shown in FIG. 6B, the (H + 1) th pixel line changes, and the image switching is completed.

  As shown in FIG. 14, although the Nth pixel line displayed on the first display 1 and the first pixel line displayed on the second display 1 are close to each other, the image is displayed when the image is switched. The displacement of the position of the pixel being eliminated is eliminated in a very short time. In addition, the displacement of the position of the pixel displaying the image can be eliminated in a very short time between other adjacent pixel lines. Therefore, it is possible to prevent the position of the pixel displaying an image from being shifted between adjacent pixel lines for a long time.

  As described above in detail, the multi-display device according to the present embodiment first displays the first pixel line, then displays the Nth pixel line on each display 1, and then displays the first pixel line and the Nth pixel line. Each pixel line is sequentially displayed while alternately displaying a pixel line closer to the first pixel line and a pixel line closer to the Nth pixel line from the pixel line toward the center pixel line. Thus, also in this embodiment, the order of displaying each pixel line is different from the conventional one, and the time difference between the time points when the display 1 displays the first pixel line and the Nth pixel line is very small. For this reason, in the boundary part of the two displays 1 arranged vertically, although the Nth pixel line of one display 1 and the first pixel line of the other display 1 are close to each other, image disturbance does not occur. In addition, when switching the image to be displayed on the multi-display device, such as when displaying a moving image, the position of the pixel displaying the image between the adjacent pixel lines at the boundary portion of the display 1 is prevented from shifting for a long time. . Therefore, also in the present embodiment, the multi-display device can display an image without disturbance, and can prevent the occurrence of image shift even when displaying a moving image.

  The configuration of the gate driver 12 in the third embodiment is an example, and the configuration of the gate driver 12 may be other configurations as long as the order in which the pixel lines are displayed is the order shown in the third embodiment. For example, the gate driver 12 may have a configuration in which the mutual connection of a plurality of shift registers is different from the conventional one, and the wiring between the plurality of level shifters and the plurality of supply units is different from the conventional one. May be.

  In the above first to third embodiments, an example in which the number N of pixel lines and gate lines is an even number is shown, but N may be an odd number. When N is an odd number, (N + 1) / 2 = H. The order of alternately displaying the pixel lines closer to the first pixel line and the pixel lines closer to the Nth pixel line shown in the first to third embodiments is an example, and the multi-display device is reversed. The pixel lines may be displayed in this order. For example, in the first and second embodiments, the H-th pixel line is displayed first, then the (H + 1) -th pixel line is displayed, and then the (H-1) -th pixel line is displayed. The multi-display device may display each pixel line in the order of displaying the (H−1) th pixel line next to the Hth pixel line and then displaying the (H + 1) th pixel line. For example, in the third embodiment, the first pixel line is displayed first, and then the Nth pixel line is displayed. However, the multi-display apparatus first displays the Nth pixel line, and then displays the Nth pixel line. You may display each pixel line in the order which displays a 1st pixel line. In the first to third embodiments, an example is shown in which the order in which the pixel lines closer to the first pixel line and the pixel lines closer to the Nth pixel line are alternately displayed is the same in all the displays 1. However, the multi-display device may reverse the order in which each pixel line is displayed between the vertically adjacent displays 1. For example, first pixel lines are displayed on the first display 1 first, then each pixel line is displayed in the order in which the Nth pixel line is displayed, and the Nth pixel line is displayed first on the second display 1. Next, the pixel lines may be displayed in the order in which the first pixel lines are displayed. In this case, the time difference between the time points when the Nth pixel line of the first display 1 and the first pixel line of the second display 1 are displayed becomes smaller, and the occurrence of image shift is further reduced.

  Further, in the first to third embodiments, the configuration in which the configuration of the gate driver 12 is different from the conventional configuration is shown. However, the multi-display device displays pixel lines by a method different from the method of changing the configuration of the gate driver 12. The form which made the order to do differ from the past may be sufficient. In the first to third embodiments, the form in which an image is displayed using the liquid crystal panel 11 has been described. However, the multi-display apparatus may be any display that displays an image by sequentially displaying a plurality of pixel lines. A form having a display different from the display using the liquid crystal panel may be used.

  As described above, the multi-display device according to the present invention includes at least a plurality of displays (1) each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction. In a multi-display device that is arranged in the vertical direction and each display (1) sequentially displays each pixel line when displaying an image, each display (1) has a plurality of pixel lines when displaying an image. The order in which each is sequentially displayed is different from the order in which the pixel line at one end is displayed first and the pixel line at the other end is displayed last.

  In the multi-display device according to the present invention, each display (1) first displays a specific pixel line excluding the pixel lines at both ends of the plurality of pixel lines at the time of displaying an image. Each pixel line is displayed sequentially from the pixel toward the pixel lines at both ends.

  In the multi-display device according to the present invention, each display (1) has a plurality of elements (31, 32) for displaying each pixel included in an image arranged in a matrix and corresponds to each pixel line. A circuit (110) including a plurality of signal lines (331 to 33N) respectively connected to the plurality of elements (31, 32) and the plurality of elements (31, 31) to each of the plurality of signal lines (331 to 33N). And a driver (12) for supplying a signal for operating 32), and the driver (12) is connected to a plurality of elements (31, 32) corresponding to the specific pixel line when displaying an image. First, a signal is supplied to the signal line (33H) and sequentially supplied to each signal line toward the signal lines (331, 33N) connected to the plurality of elements (31, 32) corresponding to the pixel lines at both ends. Supply signal Characterized in that are configured to.

  In the multi-display device according to the present invention, each display (1) first displays a pixel line at one end of the plurality of pixel lines and then displays a pixel line at the other end when displaying an image. From the pixel lines at both ends toward the pixel line on the center side, the pixel lines close to the one end and the pixel lines close to the other end are alternately displayed, and each pixel line is sequentially displayed. It is characterized by being.

  In the multi-display device according to the present invention, each display (1) has a plurality of elements (31, 32) for displaying each pixel included in an image arranged in a matrix and corresponds to each pixel line. A circuit (110) including a plurality of signal lines (331 to 33N) respectively connected to the plurality of elements (31, 32) and the plurality of elements (31, 31) to each of the plurality of signal lines (331 to 33N). And a driver (12) for supplying a signal for operating 32), and the driver (12) is connected to a plurality of elements (31, 32) corresponding to the pixel line at the one end when displaying an image. The first signal is supplied to the signal line (331), the signal is next supplied to the signal line (33N) connected to the plurality of elements (31, 32) corresponding to the pixel line at the other end, Compatible with pixel lines From the signal line (331, 33N) connected to the plurality of elements (31, 32) to the signal line connected to the plurality of elements (31, 32) corresponding to the central pixel line, Signals are alternately transmitted to the signal lines connected to the plurality of elements (31, 32) corresponding to the near pixel line and the signal lines connected to the plurality of elements (31, 32) corresponding to the pixel line near the other end. It is characterized in that the signal is sequentially supplied to each signal line while supplying the signal.

  The display (1) according to the present invention is a display that sequentially displays each pixel line in order to display an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction. In 1), the order in which each of the plurality of pixel lines is sequentially displayed is different from the order in which the pixel line at one end is displayed first and the pixel line at the other end is displayed last. And

  In the image display method according to the present invention, a plurality of displays (1) each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged at least in the vertical direction. Each display (1) is a multi-display device that sequentially displays each pixel line when displaying an image. In the method of displaying an image, each display (1) has both ends of the plurality of pixel lines. Specific pixel lines other than the pixel line are displayed first, and each pixel line is sequentially displayed from the specific pixel line toward the pixel lines at both ends.

  In the image display method according to the present invention, a plurality of displays (1) each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged at least in the vertical direction. Each display (1) is a multi-display device that sequentially displays each pixel line when displaying an image. In the method for displaying an image, each display (1) is one end of the plurality of pixel lines. The first pixel line, the second pixel line next, and the pixel lines near the one end and the pixel lines near the other end from the pixel lines at both ends toward the central pixel line. Each pixel line is sequentially displayed while being alternately displayed.

  In the present invention, in the multi-display device, a plurality of displays (1) for displaying an image in which a plurality of pixel lines are arranged in the vertical direction are arranged at least in the vertical direction. In each display (1), the display order of each of the plurality of pixel lines is set to an order different from the order in which the pixel line at one end is displayed first and the pixel line at the other end is finally displayed. Thereby, the time difference between the time points when the pixel lines at both ends are displayed becomes small. Although the pixel lines at both ends are close to each other at the boundary portion between the two displays (1) arranged vertically, the time difference between the time points when the pixel lines at both ends are displayed is small, so that the image is not disturbed. In particular, when displaying a moving image on a multi-display device, no image shift occurs at the boundary between the two displays (1).

  In the present invention, in each display (1), the multi-display device first displays specific pixel lines except for both ends of the plurality of pixel lines, and sequentially displays each pixel line toward the pixel lines at both ends. Is displayed. Thereby, the time difference in which each of the pixel lines at both ends is displayed is reduced.

  In the present invention, each display (1) includes a circuit (110) in which a plurality of elements (31, 32) for displaying each pixel is arranged, and a plurality of elements (31, 31) corresponding to each pixel line. Each pixel line is displayed by supplying a signal for operating each element (31, 32) to a plurality of signal lines (331 to 33N) respectively connected to 32). The display (1) supplies a signal to a signal line (33H) connected to a plurality of elements (31, 32) corresponding to a specific pixel line and displays a plurality of pixels corresponding to the pixel lines at both ends when displaying an image. Signals are sequentially supplied to the signal lines toward the signal lines (331, 33N) connected to the elements (31, 32). Thereby, the display (1) displays a specific pixel line first, and displays each pixel line sequentially toward the pixel lines at both ends.

  In the present invention, in each display (1), the multi-display device displays the pixel line at one end first among the plurality of pixel lines, displays the pixel line at the other end next, and starts from the pixel lines at both ends. Each pixel line is sequentially displayed toward the central pixel line. Thereby, the time difference in which each of the pixel lines at both ends is displayed is reduced.

  In the present invention, each display (1) includes a circuit (110) in which a plurality of elements (31, 32) for displaying each pixel is arranged, and a plurality of elements (31, 31) corresponding to each pixel line. Each pixel line is displayed by supplying a signal for operating each element (31, 32) to a plurality of signal lines (331 to 33N) respectively connected to 32). The display (1) supplies a signal to the signal line (331) connected to the plurality of elements (31, 32) corresponding to the pixel line at one end, and then corresponds to the pixel line at the other end when displaying an image. A signal is supplied to the signal line (33N) connected to the plurality of elements (31, 32), and sequentially toward the signal line connected to the plurality of elements (31, 32) corresponding to the central pixel line. Thus, a signal is supplied to each signal line. Thereby, the display (1) displays the pixel line at one end first, displays the pixel line at the other end next, and sequentially displays each pixel line toward the central pixel line.

DESCRIPTION OF SYMBOLS 1 Display 11 Liquid crystal panel 110 Active matrix circuit 12 Gate driver 13 Source driver 21 Image processing part 331-33N Gate line 41-4N Shift register 51-5N Level shifter 61-6N Supply part

Claims (6)

A plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged in at least the vertical direction. In a multi-display device that sequentially displays lines,
Each display
A plurality of elements for displaying each pixel included in the image are arranged in a matrix, and the number of pixel lines included in the image is N, and the first to Nth pixel lines are arranged in order in the vertical direction. A circuit including first to N-th signal lines respectively connected to a plurality of elements corresponding to each of
A driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines;
The driver is
First to Nth supply units for supplying the operation signal to each of the first to Nth signal lines;
First to Nth shift registers,
An nth shift register in which n is an odd number, where H is an integer that is N / 2 or (N + 1) / 2, n is an integer that is 1 or more and N or less, is (H− (n−1) / 2). The nth shift register connected to the (H− (n−1) / 2) th supply unit for supplying the operation signal to the signal line, and n is an even number, is (H + n / 2). Connected to the (H + n / 2) th supply section for supplying the operation signal to the signal line of
When an image is displayed, a trigger signal is sequentially input to the first to Nth shift registers, and an nth shift register in which n is an odd number is configured such that when the trigger signal is input, H- (n-1) / 2) supply unit supplies the operation signal to the (H- (n-1) / 2) signal line, and the nth shift register, where n is an even number, When the trigger signal is input, the operation signal is supplied to the (H + n / 2) signal line by the (H + n / 2) supply unit, thereby the Hth pixel line. Is displayed first, and each pixel line is sequentially displayed from the H-th pixel line toward the first pixel line and the N-th pixel line. A plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged in at least the vertical direction. In a multi-display device that sequentially displays lines,
Each display
A plurality of elements for displaying each pixel included in the image are arranged in a matrix, and the number of pixel lines included in the image is N, and the first to Nth pixel lines are arranged in order in the vertical direction. A circuit including first to N-th signal lines respectively connected to a plurality of elements corresponding to each of
A driver for supplying an operation signal for operating each of the plurality of elements to each of the first to Nth signal lines;
The driver is
First to Nth supply units for supplying the operation signal to each of the first to Nth signal lines;
First to Nth shift registers connected in a one-to-one relationship to the first to Nth supply units;
The shift register of (H− (n−1) / 2) where n is an odd number, where H is an integer of N / 2 or (N + 1) / 2, n is an integer of 1 to (N−1), The (H + (n + 1) / 2) th shift register is connected to the (H + n / 2) th shift register, where n is an even number, and is connected to the (H−n / 2) th shift register.
When an image is displayed, a trigger signal is first input to the H-th shift register, and the trigger signal is input to the (H- (n-1) / 2) shift register where n is an odd number. In this case, the trigger signal is input to the (H + (n + 1) / 2) th shift register, and the (H- (n-1) / 2) th supply unit is supplied to the (H- (n-1) / 2) th supply unit. The operation signal is supplied to the signal line 2), and the (H + n / 2) shift register in which n is an even number has the (H−n / 2) th shift register when the trigger signal is input. By inputting the trigger signal to the shift register and causing the (H + n / 2) supply unit to supply the operation signal to the (H + n / 2) signal line, the Hth pixel line is displayed first, From the H-th pixel line toward the first pixel line and the N-th pixel line Multi-display device according to claim sequentially to each pixel line are displayed. In a display that sequentially displays each pixel line in order to display an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction,
A plurality of elements for displaying each pixel included in the image are arranged in a matrix, and the number of pixel lines included in the image is N, and the first to Nth pixel lines are arranged in order in the vertical direction. A circuit including first to N-th signal lines respectively connected to a plurality of elements corresponding to each of
A driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines;
The driver is
First to Nth supply units for supplying the operation signal to each of the first to Nth signal lines;
First to Nth shift registers,
An nth shift register in which n is an odd number, where H is an integer that is N / 2 or (N + 1) / 2, n is an integer that is 1 or more and N or less, is (H− (n−1) / 2). The nth shift register connected to the (H− (n−1) / 2) th supply unit for supplying the operation signal to the signal line, and n is an even number, is (H + n / 2). Connected to the (H + n / 2) th supply section for supplying the operation signal to the signal line of
When an image is displayed, a trigger signal is sequentially input to the first to Nth shift registers, and an nth shift register in which n is an odd number is configured such that when the trigger signal is input, H- (n-1) / 2) supply unit supplies the operation signal to the (H- (n-1) / 2) signal line, and the nth shift register, where n is an even number, When the trigger signal is input, the operation signal is supplied to the (H + n / 2) signal line by the (H + n / 2) supply unit, thereby the Hth pixel line. Is displayed first, and each pixel line is sequentially displayed from the H-th pixel line toward the first pixel line and the N-th pixel line. In a display that sequentially displays each pixel line in order to display an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction,
A plurality of elements for displaying each pixel included in the image are arranged in a matrix, and the number of pixel lines included in the image is N, and the first to Nth pixel lines are arranged in order in the vertical direction. A circuit including first to N-th signal lines respectively connected to a plurality of elements corresponding to each of
A driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines;
The driver is
First to Nth supply units for supplying the operation signal to each of the first to Nth signal lines;
First to Nth shift registers connected in a one-to-one relationship to the first to Nth supply units;
The shift register of (H− (n−1) / 2) where n is an odd number, where H is an integer of N / 2 or (N + 1) / 2, n is an integer of 1 to (N−1), The (H + (n + 1) / 2) th shift register is connected to the (H + n / 2) th shift register, where n is an even number, and is connected to the (H−n / 2) th shift register.
When an image is displayed, a trigger signal is first input to the H-th shift register, and the trigger signal is input to the (H- (n-1) / 2) shift register where n is an odd number. In this case, the trigger signal is input to the (H + (n + 1) / 2) th shift register, and the (H- (n-1) / 2) th supply unit is supplied to the (H- (n-1) / 2) th supply unit. The operation signal is supplied to the signal line 2), and the (H + n / 2) shift register in which n is an even number has the (H−n / 2) th shift register when the trigger signal is input. By inputting the trigger signal to the shift register and causing the (H + n / 2) supply unit to supply the operation signal to the (H + n / 2) signal line, the Hth pixel line is displayed first, From the H-th pixel line toward the first pixel line and the N-th pixel line Display characterized in that it is sequentially displayed each pixel line. A plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged in at least the vertical direction. In a method of displaying an image on a multi-display device that sequentially displays lines,
Each display
A plurality of elements for displaying each pixel included in the image are arranged in a matrix, and the number of pixel lines included in the image is N, and the first to Nth pixel lines are arranged in order in the vertical direction. A circuit including first to N-th signal lines respectively connected to a plurality of elements corresponding to each of
A driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines;
The driver is
First to Nth supply units for supplying the operation signal to each of the first to Nth signal lines;
First to Nth shift registers,
When H is an integer that is N / 2 or (N + 1) / 2 and n is an integer that is greater than or equal to 1 and less than or equal to N, a trigger signal is sequentially input to the first to Nth shift registers at the time of image display, The n-th shift register, where n is an odd number, is connected to the (H- (n-1) / 2) -th supply unit (H- (n-1) / 2) when the trigger signal is input. to supply the operating signal to the signal lines, a shift register of the n n is an even number, when the trigger signal is input, the (H + n to supply part of the (H + n / 2) / 2) by supplying the operation signal to the signal line, the H-th pixel line is displayed first, and sequentially from the H-th pixel line toward the first pixel line and the N-th pixel line. An image display method characterized by displaying each pixel line on the screen. A plurality of displays each displaying an image in which a plurality of pixel lines each having a plurality of pixels arranged in the horizontal direction are arranged in the vertical direction are arranged in at least the vertical direction. In a method of displaying an image on a multi-display device that sequentially displays lines,
Each display
A plurality of elements for displaying each pixel included in the image are arranged in a matrix, and the number of pixel lines included in the image is N, and the first to Nth pixel lines are arranged in order in the vertical direction. A circuit including first to N-th signal lines respectively connected to a plurality of elements corresponding to each of
A driver for supplying an operation signal for operating the plurality of elements to each of the first to Nth signal lines;
The driver is
First to Nth supply units for supplying the operation signal to each of the first to Nth signal lines;
First to Nth shift registers connected in a one-to-one relationship to the first to Nth supply units;
When H is an integer that is N / 2 or (N + 1) / 2, and n is an integer that is greater than or equal to 1 and less than or equal to (N−1), a trigger signal is first input to the Hth shift register when an image is displayed. The odd (H− (n−1) / 2) shift register inputs the trigger signal to the (H + (n + 1) / 2) shift register when the trigger signal is input, The operation signal is supplied to the (H− (n−1) / 2) signal line by the (H− (n−1) / 2) supply unit, and n is an even number (H + n / 2). The shift register inputs the trigger signal to the (H−n / 2) th shift register when the trigger signal is input, and supplies the (H + n / 2) th supply to the (H + n / 2) th supply unit. of by supplying the operation signal to the signal line, a pixel line of the H is first displayed, the first H The image display method characterized by sequentially displaying each pixel line toward the prime line to the pixel line of the first pixel line and the N.

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