JP6573803B2 - Semiconductor wafer dividing method - Google Patents

Description

  The present invention relates to a method for dividing a semiconductor wafer.

  Conventionally, plasma etching is used to cut and divide a plate-like object such as a semiconductor substrate made of silicon or the like (see, for example, Patent Document 1). In the method described in Patent Document 1, a resist film is coated in a region other than the area corresponding to the street, and the back surface is ground in a state where a protective member is attached to the surface, thereby forming a semiconductor substrate with a finished thickness. Thereafter, the method described in Patent Document 1 attaches a support member to the back surface and removes the protective member from the surface to expose the resist film. In the method described in Patent Document 1, plasma etching is performed from the front surface to the back surface of a region corresponding to a street to divide the semiconductor substrate into individual devices.

JP 2006-114825 A

  A pattern made of metal or the like, for example, a dummy pattern for TEG (Test Element Group) or CMP (Chemical Mechanical Polishing) may be formed on the street of the semiconductor substrate. Usually, the TEG and the dummy pattern are formed in line symmetry along the center line of the street. Since TEG and dummy patterns made of metal or the like are difficult to dry etch, when dividing a semiconductor substrate on which TEG or dummy patterns are formed on the street, a laser is applied to the TEG or dummy pattern before dry etching. It is removed by irradiation or cutting with a cutting blade. When a semiconductor substrate having a TEG or a dummy pattern formed on a street is divided, heat input by a laser or damage by a cutting blade is added.

  In order to solve this problem, there has been proposed a method of forming a dividing groove by dry-etching empty spaces on both sides of a street of a pattern made of metal or the like formed along the street. However, this method has a problem in that the empty space for dry etching is reduced as viewed from the plasma, so that the etching rate is reduced and the productivity cannot be improved.

  Therefore, the present invention has been made in view of such a point, and an object thereof is to provide a semiconductor wafer dividing method capable of improving processing quality while suppressing a decrease in etching rate.

In order to solve the above-described problems and achieve the object, the semiconductor wafer dividing method according to the present invention has a plurality of regions defined by streets formed in a lattice pattern on the surface of the semiconductor substrate. A method for dividing a semiconductor wafer in which a plurality of devices are formed, comprising a preparation step of preparing a semiconductor wafer having a metal pattern on one end side of the street and a space on the other end side, A step of forming an etching mask having an opening in a region corresponding to the space, an etching step of etching only the semiconductor substrate along the street through the etching mask to a finished thickness of the device, and after the etching step, Holding the front surface side of the semiconductor wafer, grinding the back surface and dividing it into individual devices; Characterized in that it obtain.

The semiconductor wafer dividing method of the present invention is a semiconductor wafer dividing method in which a plurality of regions are defined by streets formed in a lattice shape on the surface of a semiconductor substrate, and a plurality of devices are formed in the partitioned regions. A step of preparing a semiconductor wafer having a metal pattern on one end side of the street and a space on the other end side, and a grinding step of grinding the back surface of the semiconductor wafer to leave the finished thickness; and Forming an etching mask having an opening in a region corresponding to the space on the back surface, and etching only the semiconductor substrate along the street through the etching mask to form a processing groove to divide into individual devices; And an etching process.

  Since the method for dividing a semiconductor wafer according to the present invention etches the space disposed on the other end side of the street, the processing quality can be improved while suppressing a decrease in the etching rate.

FIG. 1 is a perspective view of a semiconductor wafer to be processed by the semiconductor wafer dividing method according to the embodiment. FIG. 2 is a plan view of the main part of the semiconductor wafer shown in FIG. 3 is an enlarged plan view showing a portion III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a flowchart of a method for dividing a semiconductor wafer according to the first embodiment. FIG. 6 is a cross-sectional view showing an example of an etching apparatus used in the etching process of the semiconductor wafer dividing method according to the first embodiment. FIG. 7 is a cross-sectional view showing an outline of a mask process of the semiconductor wafer dividing method according to the first embodiment. FIG. 8 is a cross-sectional view illustrating an outline of an etching process of the semiconductor wafer dividing method according to the first embodiment. FIG. 9 is a cross-sectional view before the dividing step of the semiconductor wafer dividing method according to the first embodiment. FIG. 10 is a cross-sectional view after the dividing step of the semiconductor wafer dividing method according to the first embodiment. FIG. 11 is a flowchart of a method for dividing a semiconductor wafer according to the second embodiment. FIG. 12 is a cross-sectional view of the semiconductor wafer dividing method according to the second embodiment before a grinding step. FIG. 13 is a cross-sectional view illustrating an outline of a mask process of the method for dividing a semiconductor wafer according to the second embodiment. FIG. 14 is a cross-sectional view illustrating an outline of an etching process of the method for dividing a semiconductor wafer according to the second embodiment. FIG. 15 is a flowchart of a method for dividing a semiconductor wafer according to the third embodiment. FIG. 16 is a cross-sectional view of the semiconductor wafer dividing method according to the third embodiment before the grinding step. FIG. 17 is a cross-sectional view illustrating an outline of a mask process of the semiconductor wafer dividing method according to the third embodiment. FIG. 18 is a cross-sectional view illustrating an outline of the etching process of the method for dividing a semiconductor wafer according to the third embodiment. FIG. 19 is a diagram showing a change in etching rate with respect to the width of the etching region in the etching process of the product of the present invention and the comparative example.

  DESCRIPTION OF EMBODIMENTS Embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. The constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the structures described below can be combined as appropriate. Various omissions, substitutions, or changes in the configuration can be made without departing from the scope of the present invention.

Embodiment 1
A method for dividing a semiconductor wafer according to the first embodiment will be described with reference to the drawings. 1 is a perspective view of a semiconductor wafer to be processed by the semiconductor wafer dividing method according to the embodiment, FIG. 2 is a plan view of the main part of the semiconductor wafer shown in FIG. 1, and FIG. FIG. 4 is an enlarged plan view showing a portion III in FIG. 2, and FIG. 4 is a cross-sectional view taken along line IV-IV in FIG.

The semiconductor wafer dividing method according to the first embodiment (hereinafter simply referred to as a dividing method) is a method for processing the semiconductor wafer W shown in FIG. 1 and is a dividing method for dividing the semiconductor wafer W into individual devices D. . The semiconductor wafer W as a processing target to be divided into the individual devices D by the processing method according to the embodiment is, for example, a disk-shaped semiconductor wafer or an optical device wafer using silicon, sapphire, gallium, or the like as a base material. is there. As shown in FIGS. 1 and 2, the semiconductor wafer W is divided into a plurality of regions by streets S formed in a lattice pattern on the surface WS of the semiconductor substrate WA, and a plurality of devices D are formed in the divided regions. It has been done. The device D is a low dielectric constant insulating film (Low-k film) formed of an inorganic film such as SiN or SiO ₂ or an organic film such as a polyimide film or a parylene film on the surface WS of the semiconductor substrate WA. ) Are stacked.

The device D is an active device such as a transistor or an LSI (Large Scale Integration), or a passive device such as an electric resistance or a capacitor. In the first embodiment, as shown in FIG. 4, the device D includes a first layer L1 composed of a low dielectric constant insulating film (Low-k film) on the surface WS of the semiconductor substrate WA, and SiO _2. The configured second layer L2 and the third layer L3 composed of SiN are sequentially stacked. Each of the layers L1, L2, and L3 is provided with a guard ring GR that is provided on the outer side of the device D, that is, on the outer edge of the street S, and extends along the outer edge of the device D. The guard ring GR is made of metal and is for protecting the device D.

  In the first embodiment, the semiconductor wafer W is provided with a TEG 100 (Test Element Group) on the street S, which is a metal pattern for finding a problem in designing and manufacturing the device D. As shown in FIG. 3, the TEG 100 is provided corresponding to each device D, and includes an inspection pad 101 made of metal for finding a design and manufacturing problem of the device D, and an inspection pad 101. A plurality of dummy pads 102 provided around and made of metal are provided. The size of the inspection pad 101 is uniquely determined by the device D. In the first embodiment, the dummy pad 102 is embedded in the first layer L1 and the second layer L2 and provided on the second layer L2. The dummy pad 102 is for making the thickness of the semiconductor wafer W uniform when the back surface WR on the back side of the front surface WS of the semiconductor wafer W is ground and polished.

  Further, in the semiconductor wafer W, the TEG 100 is arranged near one device D on the street S between the devices D adjacent to each other. In the first embodiment, the TEG 100 is disposed across the center line P (indicated by a one-dot chain line in FIGS. 2 and 3) in the width direction of the three S, and is provided near one device D. Further, the semiconductor wafer W is provided with an etching region ER having a space of 5 μm or more and 30 μm or less between the TEG 100 and the guard ring GR of the other device D. The width of the etching region ER is desirably 10 μm or more and 20 μm or less. The etching region ER is a region where the surface WS of the semiconductor substrate WA where the TEG 100 is not formed is exposed. Thus, in the semiconductor wafer W, the TEG 100 that is a metal pattern is disposed on one end side in the width direction of the street S, and the etching region ER that is a space is disposed on the other end side.

  A dividing method according to the first embodiment will be described with reference to the drawings. FIG. 5 is a flowchart of a method for dividing a semiconductor wafer according to the first embodiment. FIG. 6 is a cross-sectional view illustrating an example of an etching apparatus used in an etching process of the method for dividing a semiconductor wafer according to the first embodiment. FIG. 7 is a cross-sectional view showing an outline of the mask process of the semiconductor wafer dividing method according to the first embodiment, and FIG. 8 is a cross-sectional view showing an outline of the etching process of the semiconductor wafer dividing method according to the first embodiment. FIG. 9 is a sectional view before the dividing step of the semiconductor wafer dividing method according to the first embodiment, and FIG. 10 is a sectional view after the dividing step of the semiconductor wafer dividing method according to the first embodiment.

  As shown in FIG. 5, the dividing method according to the first embodiment includes a preparation step ST1, a masking step ST2, an etching step ST3, and a dividing step ST4.

  The preparation step ST1 is a step of preparing the semiconductor wafer W having the above-described configuration. In the preparation step ST1, a semiconductor wafer W is prepared. After the preparation process ST1, the process proceeds to the mask process ST2.

  The mask process ST2 is a process of forming an etching mask EM having an opening in a region corresponding to the etching region ER on the surface WS side of the semiconductor substrate WA of the semiconductor wafer W. The etching mask EM is made of a resist having corrosion resistance against an etching gas or the like in the etching process. In the mask process ST2, for example, an etching mask EM is formed on the entire surface WS side of the semiconductor wafer W, and then exposed and developed through a negative or positive mask corresponding to the etching region ER of the street S. Unnecessary portions of the resist are removed from the etching region ER. For exposure, g-line (wavelength λ = 436 nm) may be used, h-line (λ = 405 nm) or i-line (λ = 365 nm) may be used, or an LED light source may be used. After the mask process ST2, on the surface WS side of the semiconductor wafer W, as shown in FIG. 7, the etching region ER is exposed, and the region excluding the etching region ER (that is, the device D and the TEG 100) is formed by the etching mask EM. It is covered. The etching mask EM is composed of a phenol novolac resist or a carbon resist. For the etching mask EM, a resist may be formed in multiple layers in order to improve the etching selectivity of the etching region ER of the surface WS of the semiconductor substrate WA with respect to the etching mask EM. After the mask process ST2, the process proceeds to the etching process ST3.

  The etching step ST3 is a step of etching the semiconductor wafer W along the street S to the finished thickness T (shown in FIG. 8) of the device D through the etching mask EM. In the etching step ST3, for example, the semiconductor wafer W is accommodated in the housing 21 through the opening 22 of the housing 21 of the etching apparatus 20 shown in FIG. Then, the back surface WR of the semiconductor substrate WA of the semiconductor wafer W is attracted and held by the electrostatic force on the suction holding member 25 of the lower electrode 24 connected to the high frequency power source 23. Next, the refrigerant is circulated from a refrigerant supply means (not shown) into a cooling passage (not shown) in the lower electrode 24, the exhaust device 27 is operated to evacuate the atmosphere in the housing 21 through the exhaust port 28, and the gas supply means 29 Then, an etching gas is injected into the housing 21 toward the surface WS side of the semiconductor wafer W through the nozzle 31 of the upper electrode 30 connected to the high frequency power supply 32. At this time, the inside of the housing 21 is maintained at a predetermined pressure. Then, high frequency power is applied from the high frequency power supply 32 to the upper electrode 30 in a state where the etching gas is injected. As a result, a plasma discharge is generated between the lower electrode 24 and the upper electrode 30, high frequency power is supplied from the high frequency power source 23 to the lower electrode 24, and ions in the plasma are drawn. As shown in FIG. The etching region ER of the surface WS of W is etched to form a groove R extending from the surface WS of the device D to the finished thickness T along the etching region ER on the surface WS of the semiconductor substrate WA of the semiconductor wafer W.

  The etching gas used in the etching process ST3 is appropriately selected according to the material of the semiconductor wafer W. For example, a gas containing a halogen element, a basic gas, and a mixed gas thereof, or a CxFy-based gas or a CxHyFz-based gas may be used as the etching gas. In the etching step ST3, a rare gas such as Ar or He may be supplied from the gas supply unit 29 as a plasma support gas.

  In the first embodiment, when the semiconductor wafer W is a so-called 300 mm wafer in the etching step ST3, the high-frequency power source 32 capable of applying high-frequency power of 13.56 MHz and 3 kW to the upper electrode 30 and the frequency of 2 MHz and 300 W are used. A high frequency power source 23 capable of applying high frequency power to the lower electrode 24 is used.

In the first embodiment, in the etching step ST3, SF ₆ is supplied as an etching gas at a flow rate of 1500 (cc / min) and Ar (argon) is supplied at a flow rate of 1000 (cc / min), and the upper electrode 30 is supplied with a high-frequency power of 3 kW. And an etching step of applying high frequency power of 300 W to the lower electrode 24, and C ₄ F ₈ as an etching gas at a flow rate of 1000 (cc / min) and Ar (argon) at a flow rate of 500 (cc / min). The protective film deposition step of applying 3 kW high frequency power to the upper electrode 30 and applying 0 W high frequency power to the lower electrode 24 is repeated alternately. In the etching process ST3, an etching step and a protective film deposition (deposition) step are alternately repeated to etch the etching region ER of the surface WS of the semiconductor substrate WA of the semiconductor wafer W, and to increase the width along the etching region ER. Forms a constant groove R.

  Thus, in the etching step ST3, a groove R having a constant width from the surface WS of the device D to the finished thickness T of the semiconductor wafer W is formed in the etching region ER of the street S. In the etching process ST3, since the protective film is formed on the inner surface of the groove R in the protective film deposition step, etching can be suppressed even if the side surface of the device D is exposed. Then, after forming the groove R, the etching mask EM is removed by ashing using oxygen or nitrogen plasma. In the first embodiment, in the etching step ST3, a support substrate (not shown) may be attached to the back surface WR of the semiconductor wafer W, and the surface WS of the semiconductor wafer W may be etched. After the etching process ST3, the process proceeds to the dividing process ST4.

  The division step ST4 is a step of dividing the semiconductor wafer W into individual devices D by holding the front surface WS side of the semiconductor wafer W and grinding the back surface WR after the etching step ST3. In the dividing step, first, as shown in FIG. 9, a protective tape TG for protecting the device D is attached to the surface WS side of the semiconductor wafer W, that is, the surface WS of the device D. Then, the surface WS of the semiconductor wafer W is placed on a chuck table of a grinding apparatus (not shown) with the protective tape TG facing down, and the back surface WR of the semiconductor substrate WA of the semiconductor wafer W is exposed and held by suction on the chuck table. Thereafter, a grinding wheel that rotates about the axis of the grinding apparatus is positioned on a chuck table that rotates about the axis. Then, while supplying the grinding water to the back surface WR of the semiconductor wafer W through a nozzle (not shown) in the grinding wheel, the grinding wheel is gradually lowered and fed to the back surface WR of the semiconductor wafer W by grinding.

  The back surface WR of the semiconductor wafer W is ground with a grinding wheel to thin the semiconductor wafer W to a finished thickness T. When the thickness of the semiconductor wafer W reaches the finished thickness T, the grinding wheel is separated from the chuck table and the suction holding of the semiconductor wafer W on the chuck table is released. When the thickness of the semiconductor wafer W reaches the finished thickness T, the depth of the groove R reaches the finished thickness T, so that the groove R is exposed to the back surface WR of the semiconductor wafer W. In the dividing step ST4, the semiconductor wafer W is divided into individual devices D by exposing the grooves R to the back surface WR of the semiconductor wafer W as shown in FIG. The divided device D is picked up from the protective tape TG by a well-known collet after the protective tape TG is expanded and the interval between the devices D is expanded to about 30 μm.

  According to the dividing method according to the first embodiment, the TEGs 100 provided in each street S of the semiconductor wafer W are arranged near one device D among the devices D adjacent to each other, and the other device D is connected to each street S. An etching region ER in which the surface WS of the semiconductor substrate WA where the TEG 100 is not formed is exposed is provided. The width of the etching region ER is 5 μm or more and 10 μm or less, and the TEG 100 is disposed across the center line P of the street S. For this reason, the dividing method can etch the etching region ER without decreasing the etching rate in the etching step ST3, and the semiconductor wafer W without increasing the thickness of the central portion of the street S in the dividing step ST4. Can be thinned to a uniform finished thickness T. Therefore, the dividing method according to the first embodiment can improve the processing quality while suppressing a decrease in the etching rate.

  Further, according to the dividing method according to the first embodiment, since the TEG 100 provided on each street S of the semiconductor wafer W is disposed across the center line P of the street S, the width of the etching region ER is etched. The width of the street S can be prevented from being increased while the width enables the reduction in the etching rate in the step ST3 to be suppressed. As a result, according to the dividing method according to the first embodiment, it is possible to suppress a decrease in the number of devices D formed on the semiconductor wafer W while suppressing a decrease in the etching rate.

[Embodiment 2]
A method for dividing a semiconductor wafer according to the second embodiment will be described with reference to the drawings. FIG. 11 is a flowchart of a semiconductor wafer dividing method according to the second embodiment, FIG. 12 is a cross-sectional view of the semiconductor wafer dividing method according to the second embodiment before a grinding step, and FIG. 13 is the second embodiment. FIG. 14 is a cross-sectional view showing an outline of a mask process of the semiconductor wafer dividing method according to the first embodiment, and FIG. 14 is a cross-sectional view showing an outline of an etching process of the semiconductor wafer dividing method according to the second embodiment. 11 to 14, the same parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The semiconductor wafer dividing method according to the second embodiment is a method for processing a semiconductor wafer W, as in the first embodiment, and is a dividing method for dividing the semiconductor wafer W into individual devices D. As shown in FIG. 11, the dividing method according to the second embodiment includes a preparation step ST1, a grinding step ST10, a mask step ST2-2, and an etching step ST3-2.

  The preparation step ST1 is a step of preparing the semiconductor wafer W as in the first embodiment. After the preparation process ST1, the process proceeds to the grinding process ST10.

  The grinding step ST10 is a step of grinding the back surface WR of the semiconductor wafer W while leaving the finished thickness T. In the grinding step ST10, first, as shown in FIG. 12, a support substrate SS for protecting the device D is attached to the surface WS side of the semiconductor wafer W, that is, the surface WS of the device D. Then, with the support substrate SS facing down, the surface WS of the semiconductor wafer W is placed on a chuck table of a grinding apparatus (not shown), and the back surface WR of the semiconductor substrate WA of the semiconductor wafer W is exposed and held on the chuck table by suction. Thereafter, a grinding wheel that rotates about the axis of the grinding apparatus is positioned on a chuck table that rotates about the axis. Then, while supplying the grinding water to the back surface WR of the semiconductor wafer W through a nozzle (not shown) in the grinding wheel, the grinding wheel is gradually lowered and fed to the back surface WR of the semiconductor wafer W by grinding.

  The back surface WR of the semiconductor wafer W is ground with a grinding wheel to thin the semiconductor wafer W to a finished thickness T. When the thickness of the semiconductor wafer W reaches the finished thickness T, the grinding wheel is separated from the chuck table and the suction holding of the semiconductor wafer W on the chuck table is released. After the grinding process ST10, the process proceeds to the mask process ST2-2.

  The mask process ST2-2 is a process of forming an etching mask EM having an opening in a region corresponding to the etching region ER on the back surface WR of the semiconductor substrate WA. The etching mask EM is made of a resist having corrosion resistance against an etching gas or the like in the etching process. In the mask process ST2-2, as shown in FIG. 13, as in the first embodiment, an etching mask EM having an opening in a region corresponding to the etching region ER of the back surface WR of the semiconductor substrate WA is formed. After the mask process ST2-2, the process proceeds to the etching process ST3-2.

  The etching step ST3-2 is a step of forming a processing groove PR (shown in FIG. 14) penetrating the semiconductor substrate WA along the street S through the etching mask EM and dividing the semiconductor wafer W into individual devices D. is there. In the etching step ST 3-2, the support substrate SS attached to the surface WS side of the semiconductor wafer W, that is, the surface WS of the device D is sucked and held by the suction holding member 25 of the lower electrode 24, and the semiconductor wafer W The back surface WR is opposed to the upper electrode 30. In the etching step ST 3-2, similarly to the first embodiment, a high frequency power is applied from the high frequency power sources 23 and 32 to the lower electrode 24 and the upper electrode 30 to correspond to the etching region ER of the back surface WR of the semiconductor wafer W. As shown in FIG. 14, a processed groove PR penetrating the semiconductor substrate WA of the semiconductor wafer W is formed. In the etching step ST <b> 3-2, as shown in FIG. 14, the semiconductor wafer W is divided into individual devices D by passing the semiconductor substrate WA of the semiconductor wafer W through the processing groove PR. Then, the etching mask EM is removed by ashing, and the divided device D is picked up by a known collet.

  According to the dividing method according to the second embodiment, as in the first embodiment, an etching region ER having a width not smaller than 5 μm and not larger than 10 μm is formed on each street S of the semiconductor wafer W, and the TEG 100 is formed. It is disposed across the center line P of the street S. For this reason, the division | segmentation method can suppress that the etching rate in etching process ST3-2 falls, and can suppress that processing quality falls. Further, according to the dividing method according to the second embodiment, since the TEG 100 is disposed across the center line P of the street S as in the first embodiment, the number of devices D formed on the semiconductor wafer W is increased. Can be reduced.

[Embodiment 3]
A method for dividing a semiconductor wafer according to the third embodiment will be described with reference to the drawings. FIG. 15 is a flowchart of a semiconductor wafer dividing method according to the third embodiment, FIG. 16 is a cross-sectional view of the semiconductor wafer dividing method according to the third embodiment before a grinding step, and FIG. FIG. 18 is a cross-sectional view showing an outline of a mask process of a semiconductor wafer dividing method according to the present invention, and FIG. 18 is a cross-sectional view showing an outline of an etching process of the semiconductor wafer dividing method according to the third embodiment. 15 to 18, the same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

  The method for dividing a semiconductor wafer according to the third embodiment is a method for processing a semiconductor wafer W as in the first and second embodiments, and is a method for dividing the semiconductor wafer W into individual devices D. As shown in FIG. 15, the dividing method according to the third embodiment includes a preparation step ST1, a grinding step ST10, a mask step ST2-3, and an etching step ST3-3.

  The preparation step ST1 is a step of preparing the semiconductor wafer W as in the first and second embodiments. After the preparation process ST1, the process proceeds to the grinding process ST10. The grinding step ST10 is a step of grinding the back surface WR of the semiconductor wafer W while leaving the finished thickness T as in the second embodiment. After the grinding process ST10, the process proceeds to the mask process ST2-3.

  The mask process ST2-3 is a process of forming an etching mask EM having an opening in a region corresponding to the etching region ER on the surface WS side of the semiconductor substrate WA of the semiconductor wafer W, as in the first embodiment. In the mask process ST2-3, the support substrate SS is attached to the back surface WR of the semiconductor substrate WA of the semiconductor wafer W, and the support substrate SS attached to the front surface WS side of the semiconductor substrate WA of the semiconductor wafer W is removed. In the mask process ST2-3, as shown in FIG. 17, as in the first embodiment, an etching mask EM having an opening in a region corresponding to the etching region ER on the surface WS side of the semiconductor substrate WA of the semiconductor wafer W is formed. . After the mask process ST2-3, the process proceeds to the etching process ST3-3.

  The etching step ST3-3 is a step of forming a processing groove PR (shown in FIG. 18) penetrating the semiconductor substrate WA along the street S via the etching mask EM, and dividing the semiconductor wafer W into individual devices D. is there. In the etching step ST3-3, the support substrate SS attached to the back surface WR of the semiconductor substrate WA of the semiconductor wafer W is sucked and held by the suction holding member 25 of the lower electrode 24, and the surface WS of the semiconductor wafer W is set to the upper electrode. 30. In the etching step ST3-3, as in the first embodiment, high frequency power is applied to the lower electrode 24 and the upper electrode 30 from the high frequency power sources 23 and 32 to etch the etching region ER of the surface WS of the semiconductor wafer W. As shown in FIG. 18, a processing groove PR penetrating the semiconductor substrate WA of the semiconductor wafer W is formed. In the etching step ST3-3, as shown in FIG. 18, the semiconductor wafer W is divided into individual devices D by passing the semiconductor substrate WA of the semiconductor wafer W through the processing groove PR. Then, the etching mask EM is removed by ashing, and the divided device D is picked up by a known collet.

  According to the dividing method according to the third embodiment, as in the first and second embodiments, an etching region ER having a width of 5 μm or more and 10 μm or less in which the TEG 100 is not formed on each street S of the semiconductor wafer W is formed. The TEG 100 is disposed across the center line P of the street S. For this reason, the division | segmentation method can suppress that the etching rate in etching process ST3-3 falls, and can suppress that processing quality falls. Further, according to the dividing method according to the third embodiment, the TEG 100 is disposed across the center line P of the street S as in the first and second embodiments, and thus is formed on the semiconductor wafer W. A decrease in the number of devices D can be suppressed.

  Next, the inventors of the present invention confirmed the effect of the present invention. The results are shown in Table 1 and FIG. FIG. 19 is a diagram showing a change in etching rate with respect to the width of the etching region in the etching process of the product of the present invention and the comparative example.

  Comparative Example 1 in Table 1 divides a semiconductor wafer W whose etching region ER has a width of 3 μm into individual devices D by the dividing method according to Embodiment 1, and Comparative Example 2 has a semiconductor whose etching region ER has a width of 50 μm. The wafer W is divided into individual devices D by the dividing method according to the first embodiment, and the product 1 of the present invention converts the semiconductor wafer W having an etching region ER width of 5 μm into individual devices D by the dividing method according to the first embodiment. In the product 2 of the present invention, the semiconductor wafer W having an etching region ER width of 20 μm is divided into individual devices D by the dividing method according to the first embodiment, and the product 3 of the present invention has a width of 30 μm in the etching region ER. The semiconductor wafer W was divided into individual devices D by the dividing method according to the first embodiment. Table 1 shows the etching rate in the etching step ST3 of Comparative Example 1, Comparative Example 2, Invention Product 1 and Invention Product 2, and the number of devices D that can be formed on the semiconductor wafer W. FIG. 19 shows the etching rate of the etching step ST3 of the dividing method according to the first embodiment when the width of the etching region ER of the semiconductor wafer W made of silicon is changed in the semiconductor substrate WA.

  According to Table 1 and FIG. 19, although the comparative example 1 has many devices D, the etching rate of the etching process ST3 is slow, and the comparative example 2 has a fast etching rate of the etching process ST3, but the number of devices D. There were few. Compared to Comparative Example 1 and Comparative Example 2, it was found that the inventive product 1, the inventive product 2 and the inventive product 3 have a high etching rate in the etching step ST3 and a large number of devices D. . Further, as shown in FIG. 19, the etching rate increases as the width of the etching region ER increases. However, according to FIG. 19, the etching raids of the products 2 and 3 of the present invention hardly change. It has been found that Invention 2 is most desirable. Therefore, this invention product 1-this invention product 3 suppresses that the number of the devices D formed in the semiconductor wafer W reduces by making the width | variety of the etching area | region ER into 5 micrometers or more and 30 micrometers or less. Although it is possible, it has been found that the etching rate in the etching step ST3 can be suppressed from decreasing and the processing quality can be suppressed from decreasing. Furthermore, the product 2 of the present invention makes it possible to suppress the decrease in the number of devices D formed on the semiconductor wafer W by setting the width of the etching region ER to 10 μm or more and 20 μm or less. It has been clarified that the etching rate in the etching step ST3 can be prevented from being lowered and the processing quality can be prevented from being lowered.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

W Semiconductor wafer WA Semiconductor substrate WS Front surface WR Back surface S Street D Device T Finished thickness EM Etching mask ER Etching area (space)
PR machined groove 100 TEG (metal pattern)
ST1 Preparation process ST2, ST2-2, ST2-3 Mask process ST3, ST3-2, ST3-3 Etching process ST4 Dividing process ST10 Grinding process

Claims (2)

A method for dividing a semiconductor wafer, wherein a plurality of regions are defined by streets formed in a lattice pattern on the surface of a semiconductor substrate, and a plurality of devices are formed in the partitioned regions,
A preparation step of preparing a semiconductor wafer in which a metal pattern on one end side of the street and a space on the other end side are disposed,
Forming an etching mask having an opening in a region corresponding to the space on the surface side;
Etching process that etches only the semiconductor substrate along the street through the etching mask to the finished thickness of the device;
After the etching step, holding the front surface side of the semiconductor wafer, grinding the back surface and dividing into individual devices;
A method for dividing a semiconductor wafer comprising: A method for dividing a semiconductor wafer, wherein a plurality of regions are defined by streets formed in a lattice shape on the surface of a semiconductor substrate, and a plurality of devices are formed in the partitioned regions,
Preparing a semiconductor pattern in which a metal pattern is provided on one end side of the street and a space is provided on the other end side;
A grinding step of grinding the back surface of the semiconductor wafer to leave the finished thickness; and
Forming an etching mask having an opening in a region corresponding to the space on the back surface;
An etching step of etching only the semiconductor substrate along the street through the etching mask to form a processing groove and dividing it into individual devices;
A method for dividing a semiconductor wafer comprising:

Images