JP6547158B2 - Light detection element and solid-state imaging device - Google Patents

Description

  The present invention relates to a light detection element and a solid-state imaging device, and more particularly to a solid-state imaging device having a global shutter function and a light detection element having a light detection element and a photogate structure suitable as pixels of the solid-state imaging device.

In the CMOS image sensor, a rolling shutter operation is basic, but a CMOS image sensor having a global shutter function has been proposed (see Patent Document 1).
However, in the case of a conventional CMOS image sensor having a global shutter function as described in Patent Document 1, a narrow gap between the gate electrode for the global shutter and the transfer gate electrode, typically about 0.1 μm or less If not formed, potential dips or potential barriers are formed between the gate electrode for the global shutter and the transfer gate electrode, which causes a problem in that charge transfer is hindered. This problem is a difficult problem to solve when using a normal CMOS process.

JP, 2009-268083, A

  In view of the above problems, according to the present invention, there is provided a light detecting element and a light detecting element capable of reliably securing a potential difference for charge transfer while maintaining low noise current performance with low dark current and easy manufacturing process. It is an object of the present invention to provide a solid-state imaging device using the pixel as a pixel.

In order to solve the above problems, according to a first aspect of the present invention, photoelectric conversion is provided by (a) a base portion comprising a semiconductor layer of the first conductivity type, and (b) above the base portion. First transfer control means for controlling the accumulation and transfer of the signal charge, and (c) a buffer diode portion comprising a pn junction provided on the upper portion of the base portion adjacent to the first transfer control means; (d) second transfer control means provided on the upper portion of the base portion adjacent to the buffer diode portion and controlling transfer of signal charges by the insulated gate structure, and (e) adjacent to the second transfer control means A gist of the present invention is a light detection element including: a charge detection region provided on an upper portion of the base portion and detecting a signal charge transferred by the second transfer control unit, the charge detection region comprising the semiconductor region of the second conductivity type.
A second aspect of the present invention is a solid-state imaging device in which a pixel array is configured by arranging a plurality of the light detection elements defined in the first aspect of the present invention as pixels.

  According to the present invention, a photodetection element is used which can ensure a potential difference for charge transfer while ensuring low dark current and low noise performance, and which is easy to manufacture, and this photodetection element as a pixel A solid-state imaging device can be provided.

FIG. 1 (a) is a view exemplarily showing the outline of the main part of the light detection element according to the first embodiment of the present invention, and FIG. 1 (b) is the first embodiment shown in FIG. 1 (a). It is a figure which shows the potential profile of the light detection element which concerns on FIG. It is a schematic plan view which shows schematic structure of the principal part of the light detection element which concerns on 1st Embodiment shown in FIG. It is another typical top view which shows schematic structure of the principal part of the light detection element which concerns on 1st Embodiment shown in FIG. FIG. 7 is a view for explaining the charge transfer operation of the light detection element according to the first embodiment shown in FIG. 1 by a change in potential profile. FIG. 5 is a diagram for explaining a subsequent change of the potential profile of the light detection element according to the first embodiment shown in FIG. 1 in order to explain the charge transfer operation following the change of the potential profile shown in FIG. 4. FIG. 7 is a diagram showing a potential profile in the depth direction in the buried channel region and the barrier region when a binary voltage is applied to the storage gate electrode of the light detection element according to the first embodiment shown in FIG. 1. It is a schematic plan view explaining the outline of the principal part of the whole structure of the solid-state imaging device which can carry out global shutter operation which makes a light detection element concerning a 1st embodiment shown in Drawing 1 a unit pixel. FIG. 8 (a) is a view exemplarily showing the outline of the main part of the light detection element according to the second embodiment of the present invention, and FIG. 8 (b) is the second embodiment shown in FIG. 8 (a) It is a figure which shows the potential profile of the light detection element which concerns on a form. It is a schematic plan view which shows schematic structure of the principal part of the light detection element which concerns on 2nd Embodiment shown in FIG. FIG. 9 is another schematic plan view showing the schematic configuration of the main part of the light detection element according to the second embodiment shown in FIG. 8; It is a figure which shows the cross-section of the light detection element which had the photogate electrode which concerns on a comparative example examined before implement | achieving the light detection element which concerns on 2nd Embodiment.

  Next, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is needless to say that parts having different dimensional relationships and proportions are included among the drawings.

  As known to those skilled in the art, the "first conductivity type" in a semiconductor means either p-type or n-type, and the "second conductivity type" means the opposite conductivity type of the first conductivity type. . That is, if the “first conductivity type” is p-type, the “second conductivity type” is n-type, and if the “first conductivity type” is n-type, the “second conductivity type” is p-type. In the following description, for convenience of explanation, the case where the “first conductivity type” is p-type, the “second conductivity type” is n-type, and the signal charge is an electron is discussed, but it is merely a matter of choice. The present invention is not limited to the selection for the convenience of the description. The “first conductivity type” is defined as n-type, the “second conductivity type” is defined as p-type, and the polarity of the voltage applied to each part is reversed. Of course, even when the signal charge is a hole, the technical idea of the present invention is applicable and the same argument can be made.

Further, the directions of “left and right” and “upper and lower” in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. Thus, for example, if the paper is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". Of course.
Furthermore, the first and second embodiments described below illustrate an apparatus and method for embodying the technical idea of the present invention, and various light detection elements, and the light detection elements are described. The present invention is applicable to various solid-state imaging devices such as an imaging device for high-speed moving images used and an imaging device for still images for imaging high-speed phenomena without blurring. Further, the technical idea of the present invention does not specify the material, shape, structure, arrangement and the like of the components to the following, and the technical idea of the present invention is described in the claims. Various changes can be made within the scope.

First Embodiment
As shown in FIG. 1A, the light detection element according to the first embodiment of the present invention is provided on a base portion 11 formed of a semiconductor layer of the first conductivity type (p type) and on the upper portion of the base portion 11. Adjacent to the first transfer control means (14, 15, 16) for controlling accumulation and transfer of the photoelectrically converted signal charge by the insulated gate structure, and the first transfer control means (14, 15, 16) The buffer diode portion D2 comprising a pn junction and provided on the upper portion of the base portion 11, and provided on the upper portion of the base portion 11 adjacent to the buffer diode portion D2 controls transfer of signal charges by the insulated gate structure. The second transfer control means (19, 23) and the second transfer control means (19, 23) are provided adjacent to the upper portion of the base 11 and transferred by the second transfer control means (19, 23) The second conductivity type (n And a charge detecting region 20 composed of a semiconductor region of).

  Although the case where a semiconductor substrate of the first conductivity type (p type) is used as the “base portion 11” is illustrated in FIG. 1A, the semiconductor substrate of the first conductivity type is used instead of the semiconductor substrate. Alternatively, a two-layer structure in which the first conductivity type epitaxial growth layer having a lower impurity density than the semiconductor substrate is formed may be realized, and the epitaxial growth layer may be adopted as the base portion 11 composed of the first conductivity type semiconductor layer. Even if an epitaxial growth layer of the first conductivity type (p type) is formed on a semiconductor substrate of the second conductivity type (n type) and the epitaxial growth layer is adopted as the base portion 11 composed of the semiconductor layer of the first conductivity type. Good.

  If a first conductivity type (p type) epitaxial growth layer is formed to form a pn junction on a second conductivity type (n type) semiconductor substrate, the input light has a second conductivity type in the case of a long wavelength. The carrier by light generated in the semiconductor substrate of the second conductivity type does not enter the epitaxial growth layer of the first conductivity type because of the potential barrier due to the built-in potential of the pn junction. 2 Carriers generated in the deep of the semiconductor substrate of the conductivity type can be positively discarded. This makes it possible to prevent carriers generated at a deep position from diffusing back and leaking into adjacent pixels. This has the effect of preventing color mixing particularly in the case of a single plate color image sensor mounted with RGB color filters.

  A photoelectric conversion diode comprising a pn junction of a first buried type region 13 of a first conductivity type (p type) and a second buried layer region 12 of a second conductivity type (n type) on the surface side of the base portion 11 A portion D1 is formed, and photoelectric conversion is performed in the photoelectric conversion diode portion D1 to generate signal charges, and the signal charges (electrons) are accumulated in the second buried layer region 12. As shown in the plan views of FIGS. 2 and 3, the photoelectric conversion diode D1 is adjacent to the first transfer control means (14, 15, 16) in a direction different from that of the buffer diode D2 on the plane pattern. It is arranged.

A storage gate electrode 14 is formed adjacent to the photoelectric conversion diode portion D1 so as to form an insulated gate structure in which various insulating films such as a silicon oxide film (SiO ₂ film) are used as a gate insulating film. That is, the storage gate electrode 14 constitutes a part of the insulated gate structure of the first transfer control means (14, 15, 16). The first transfer control means (14, 15, 16) comprises a barrier region 16 formed of a semiconductor region of the first conductivity type adjacent to the photoelectric conversion diode portion D1, and between the barrier region 16 and the buffer diode portion D2. And a buried channel region 15 formed of a semiconductor region of the second conductivity type. That is, the barrier region 16 is formed adjacent to the photoelectric conversion diode D1 on the surface side of the base portion 11 under the storage gate electrode 14 and buried from the photoelectric conversion diode D1 via the barrier region 16 Channel region 15 is formed.

The photoelectric conversion is also performed while holding the signal charge in the buried channel region 15. Therefore, as shown in FIG. 1A, the charge is generated in the well region 23 having a higher impurity density than that of the base portion 11 so that the charge generated in the deep portion of the base portion 11 is not mixed into the signal charge in the buried channel region 15. It is desirable to cover the channel region 15, the barrier region 16, the third buried layer region 18, the fourth buried layer region 17, and the like.
Adjacent to buried channel region 15, buffer diode portion D2 is formed of a third buried layer region 18 of the first conductivity type (p type) and a fourth buried layer region 17 of the second conductivity type (n type). A read gate electrode 19 is formed which is formed and adjacent to the buffer diode portion D2 to constitute a second transfer control means. Similar to the storage gate electrode 14, the read gate electrode 19 also has an insulating gate structure using various insulating films as gate insulating films.

Although not shown in FIG. 1, a gate is formed between read gate electrode 19 and well region 23, between storage gate electrode 14 and barrier region 16, between storage gate electrode 14 and buried channel region 15. An insulating film is inserted. As the gate insulating film, if the base portion 11 is silicon (Si), a silicon oxide film adopted for the MOS structure is suitable, but the present invention is not limited to the silicon oxide film, and other than silicon oxide film It is possible to use various insulating films such as a silicon nitride film (Si ₃ N ₄ film) of For example, it may be an insulating film having a multilayer structure such as an ONO film consisting of a three-layer laminated film of silicon oxide film / silicon nitride film / silicon oxide film. Furthermore, strontium oxide (SrO) film, aluminum oxide (Al ₂ O ₃ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium oxide (HfO 2) film, zirconium Strontium (Sr) such as oxide (ZrO ₂ ) film, tantalum oxide (Ta ₂ O ₅ ) film, bismuth oxide (Bi ₂ O ₃ ) film, etc., aluminum (Al), magnesium (Mg), yttrium (Y) A single layer film or multilayer film of an oxide containing at least one element of hafnium (Hf), zirconium (Zr), tantalum (Ta), bismuth (Bi), or a silicon nitride containing these elements It can be used as an insulating film. Further, the present invention is not limited to the case where the base portion 11 is silicon (Si), and other semiconductor materials such as germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc. I do not care.

  Adjacent to the read gate electrode 19, a charge detection region 20 (FD) formed of a semiconductor region of the second conductivity type (n type) with high impurity density is formed in a floating state. By applying a high (H) level voltage to the read gate electrode 19 while the low (L) level voltage is applied to the storage gate electrode 14, the signal charge stored in the buried channel region 15 is a charge. It can be read out to the detection area 20.

  As can be understood from the plan views of FIGS. 2 and 3, adjacent to the left side of the photoelectric conversion diode portion D1 shown in FIG. 1 in a direction different from the first transfer control means (14, 15, 16) on the plane pattern. In addition, discharge control means (21, 11) are provided to control the transfer of charge by means of an insulated gate structure. Furthermore, an electric charge formed of an n-type semiconductor region is provided on the upper part of the base 11 adjacent to the left side of the discharge control means (21, 11) and receives the charge transferred by the discharge control means (21, 11). A discharge area 22 is arranged.

  As shown in FIG. 1A, the cross section of the element isolation insulating film 31 thicker than the gate insulating film is exposed on the right side of the charge detection region 20 and on the left side of the charge discharge region 22. The element isolation insulating film 31 may also be formed of a silicon oxide film, or may be formed of an insulating film other than the silicon oxide film. On the planar pattern, the boundary between the end of the element isolation insulating film 31 and the base portion 11 is continuous on the back side of the paper surface of FIG. 1A so as to form a closed polygon topology. That is, the element isolation insulating film 31 is disposed on the planar pattern so as to surround the charge detection region 20 and the charge discharge region 22, and provided on the element isolation insulating film 31 so as to expose a part of the surface of the base portion 11. The window portion defines the occupied area of the active region 30a shown in FIG. 2 or the active region 30b shown in FIG.

A binary voltage of high (H) level and low (L) level is applied to the storage gate electrode 14. As shown in FIG. 1B, when a high (H) level voltage (first potential) is applied to the storage gate electrode 14, the potentials of both the barrier region 16 and the buried channel region 15 are both photoelectric The potential becomes deeper than the potential φ _pd of the conversion diode portion D1. Also, as shown in FIG. 1B, since the potential φ _gs (H) of the buried channel region 15 is deeper than the barrier region 16 by the potential difference Vsb, the signal charge stored in the photoelectric conversion diode portion D1 is a barrier. The data is transferred to the buried channel region 15 via the region 16. Since the potential _gs (H) of the buried channel region 15 can be made sufficiently deeper than the potential _{pd of the} photoelectric conversion diode unit D1, charge transfer from the photoelectric conversion diode unit D1 to the buried channel region 15 is facilitated.

On the other hand, when a low (L) level voltage (second potential) is applied to the storage gate electrode 14, as shown in FIG. 1 (b), the potential difference in the buried channel region 15 is higher than that in the barrier region 16. While maintaining the potential 浅_gs (L) which is deeper by Vsa, the potential of the barrier region 16 becomes shallower than the potential _{pd pd} of the photoelectric conversion diode section D1 and prevents backflow of signal charges accumulated in the buried channel region 15. . Furthermore, when a low (L) level voltage is applied to the storage gate electrode 14, both the buried channel region 15 and the barrier region 16 have a pinning operation in which the semiconductor surface is filled with holes (see FIG. 6 for details) (Described later), the surface is inactivated, and the dark current can be significantly reduced.

As shown in FIG. 1A, the charge detection region 20 of the light detection element is connected to the gate electrode of the amplification transistor TA _ij constituting the read buffer amplifier. The drain electrode of the amplification transistor TA _ij is connected to the power supply VDD, and the source electrode is connected to the drain electrode of the selection transistor TS _ij for pixel selection. The source electrode of the selection transistor TS _ij is connected to the read signal line B _j , and the control signal S (i) for selecting the horizontal line is supplied to the gate electrode. By setting selection control signal S (i) to high (H) level, selection transistor TS _ij is turned on, and the current corresponding to the potential of charge detection region 20 amplified by amplification transistor TA _ij is read signal line B. It flows to _j . Further, the charge detection region 20 is connected to the source electrode of the reset transistor TR _ij constituting the read buffer amplifier. The drain electrode of the reset transistor TR _ij is connected to the power supply VDD, and the reset signal R (i) is supplied to the gate electrode. The reset signal R (i) is set to the high (H) level to discharge the charge accumulated in the charge detection area 20, and the charge detection area 20 is reset.

  As described above, the buffer diode portion D2 is formed between the storage gate electrode 14 and the read gate electrode 19, and the impurity density and thickness of the third buried layer region 18 and the fourth buried layer region 17 are appropriate. By setting the potential distribution as shown in the potential distribution diagram of FIG. 1 (b), dips or barriers of potential in the transfer path can be formed even if the gap between the storage gate electrode 14 and the read gate electrode 19 is not narrow. It can be prevented from being formed, and good charge transfer becomes possible. That is, according to the light detection element according to the first embodiment, the buffer diode portion D2 is formed between the first transfer control means (14, 15, 16) and the second transfer control means (19, 23). Therefore, even if the storage gate electrode 14 and the read gate electrode 19 are not formed with a narrow gap, potential dip or formation of a potential barrier is prevented. For example, the space between the storage gate electrode 14 and the read gate electrode 19 may be about 0.1 to 0.5 μm, which facilitates the manufacturing process.

  Further, according to the light detection element according to the first embodiment, the difference between the potential of the photoelectric conversion diode unit D1 and the potential of the buried channel region 15 and the potential of the buried channel region 15 and the potential of the charge detection region 20 are The difference is sufficiently secured by applying a binary voltage of high (H) level and low (L) level to the first transfer control means (14, 15, 16) to facilitate charge transfer. . Furthermore, when charge is accumulated in the buried channel region 15, the dark current is significantly reduced by the surface of both the barrier region 16 and the buried channel region 15 being subjected to pinning operation.

  Similarly, a light shielding plate 24 in which the upper surfaces of the buried channel region 15, the barrier region 16, the third buried layer region 18, the fourth buried layer region 17, the charge detection region 20, the charge discharge region 22, etc. By covering with the above, it is possible to prevent the influence of the incident light on the signal charge held in the buried channel region 15. A discharge gate electrode 21 (GR) is formed adjacent to the photoelectric conversion diode portion D1 in a direction different from the storage gate electrode 14 side, and the charge discharge region 22 (VD) has the same straight line via the discharge gate electrode 21. Arranged in a shape. By appropriately setting the gate voltage of the discharge gate electrode 21, the incident light becomes strong and the signal charge photoelectrically converted by the photoelectric conversion diode portion D 1 becomes excessive before overflowing to the buried channel region 15. Excess signal charge can be discharged to the charge discharging region 22 through the gate electrode 21, and blooming can be prevented. Further, by setting the gate voltage of the discharge gate electrode 21 to a sufficiently high voltage, the signal charge accumulated in the photoelectric conversion diode section D1 can be emptied at the start of photoelectric conversion.

  FIG. 2 shows an example of a plane pattern of the light detection element according to the first embodiment shown in FIG. 1, and the charge discharge area 22 forming a rectangular plane pattern, the discharge forming a rectangular (rectangular) plane pattern Gate electrode 21, photoelectric conversion diode portion D1 forming a hexagonal planar pattern, storage gate electrode 14 including rectangular embedded channel region 15 in a rectangular (rectangular) planar pattern, rectangular planar pattern The buffer diode portion D2, the read gate electrode 19 having a rectangular planar pattern, and the charge detection region 20 having a rectangular planar pattern are arranged in a straight line from the left to the right inside the active region 30a. As shown in FIG. 2, the barrier region 16, the buried channel region 15 and the buffer diode part D <b> 2 are disposed inside the well region 23 on the plane pattern. Therefore, the cross-sectional view seen from the direction of IA-IA in FIG. 2 corresponds to FIG.

  FIG. 3 also shows an example of a plane pattern of the light detection element according to the first embodiment shown in FIG. 1, and a step sectional view seen from the IB-IB direction in FIG. 3 corresponds to FIG. As shown in FIG. 3, a charge discharging region 22 forming a rectangular plane pattern, a discharge gate electrode 21 forming a triangle plane pattern, a photoelectric conversion diode portion D1 forming a polygon plane pattern, and a trapezoid plane pattern are formed. A storage gate electrode 14 including a trapezoidal embedded channel region 15 inside, a buffer diode portion D2 forming a trapezoidal planar pattern, a read gate electrode 19 forming a triangular planar pattern, and a charge detection region 20 forming a rectangular planar pattern Inside the active region 30b, it is disposed in a bent topology so that a diagonal direction from the upper left direction to the lower right direction is used as a main route. As shown in FIG. 3, the barrier region 16, the buried channel region 15 and the buffer diode part D <b> 2 are disposed inside the well region 23 on a plane pattern. According to the topology of the planar pattern as shown in FIG. 3, the transfer path can be taken relatively long, which is advantageous for reducing the area of the active region 30b.

--- Charge transfer operation of the light detection element of the first embodiment ---
The charge transfer operation of the light detection element according to the first embodiment shown in FIG. 1 will be described in more detail using FIG. 4 and FIG.
(A) First, as shown in the potential profile of FIG. 4A, the potential GR of the discharge gate electrode 21 is set to the high (H) level while the potential SG of the storage gate electrode 14 is low (L) level, The potential of the channel immediately below the gate electrode 21 is deepened, and the channel is turned on to discharge the signal charge and the charge due to the dark current accumulated in the second embedded layer region 12 of the photoelectric conversion diode section D1.

(B) Next, as shown in the potential profile of FIG. 4B, while the potential SG of the storage gate electrode 14 is low (L) level, the potential TX of the read gate electrode 19 and the potential GR of the discharge gate electrode 21 are low. (L) level is set, the potential of the channel immediately below each of the read gate electrode 19 and the discharge gate electrode 21 is made shallow, and the channel is turned off, and the signal charge photoelectrically converted by the photoelectric conversion diode section D1 is It accumulates in the 2nd embedded layer field 12 of photoelectric conversion diode part D1.
(C) After accumulating the signal charges subjected to photoelectric conversion in the second embedded layer region 12 of the photoelectric conversion diode section D1 for a certain period, as shown in the potential profile of FIG. 4C, the potential of the storage gate electrode 14 By setting SG to a high (H) level voltage, the charge of the photoelectric conversion diode section D1 is transferred to the buried channel region 15.

(D) After the charge transfer to the buried channel region 15 is completed, the potential SG of the storage gate electrode 14 is returned to the low (L) level to embed the signal charge, as shown in the potential profile of FIG. The channel region 15 and the buffer diode portion D2 are held.
(E) In the charge read-out period, as shown in the potential profile of FIG. 5E, the potential TX of the read gate electrode 19 is increased while the potential SG of the storage gate electrode 14 is low (L) level, and the read gate The electrode 19 is turned on to read out the signal charge accumulated in the buried channel region 15 and the buffer diode portion D 2 to the charge detection region 20.

  FIG. 6 shows the depths of the barrier region 16 and the buried channel region 15 constituting the first transfer control means (14, 15, 16) in FIG. 1 as a parameter with the binary voltage applied to the storage gate electrode 14 as a parameter. It is the figure which showed vertical direction potential. Here, the potential distribution of the barrier region 16 is indicated by a broken line, and the potential distribution of the buried channel region 15 is indicated by a solid line. Further, the gate voltage of the low (L) level is V1, and the gate voltage of the high (H) level is V2. At the high (H) level voltage V2, the potential of the buried channel region 15 is formed deep, and a potential difference of Vsb is generated between the barrier region 16 and the buried channel region 15 to hold the signal charge. . On the other hand, at a low (L) level voltage V1 which is a negative voltage, a potential difference of Vsa occurs between the barrier region 16 and the buried channel region 15 to hold signal charges, and the surface potential of both regions is the base portion 11 The potential is lower than the potential of the potential, and holes are accumulated, resulting in a pinning operation. For this reason, the semiconductor surface of the base portion 11, which is a main source of dark current, is inactivated, and the dark current can be significantly reduced.

--- Solid-state imaging device according to the first embodiment ---
The solid-state imaging device (two-dimensional image sensor) according to the first embodiment of the present invention, as shown in FIG. 7, has the same semiconductor chip as the pixel array unit 5 and the peripheral circuit unit (51, 52, 55). It is integrated on top. The pixel array unit 5 is a light detection element whose outline is shown in FIG. 1A as a pixel X _ij (i = 1 to n; j = 1 to m: n and m are integers). , And a large number of the pixels X _ij are arranged in a two-dimensional matrix. Each pixel X _ij constitutes, for example, a rectangular imaging region.

The lower side portion of the pixel array section 5, the first pixel row _{X 11, X 12, X 13} , ......, X 1m direction; second pixel row _{X 21, X 22, X 23} , ......, X 2m direction; ......; i-th pixel row _Xi1 , _Xi2 , _Xi3 , ..., X _im direction; ......; (n-1) -th pixel row X _{(n-1) 1} , X _{(n-1) 2} , _{X (n1) 3, ......,} X (n1) m direction; the n-th pixel row _{X n1, X n2, X n3} , ......, and the column decoder circuit 55 is provided along the X _nm direction There is. Also, on the left side of the pixel array portion, the first pixel row X ₁₁ , X ₂₁ ,..., X _i1 ,..., X _{(n−1) 1} , X _n1 direction; the second pixel row X ₁₂ , X ₂₂ ,..., X _i2 ,..., X _{(n-1) 2} , X _n2 direction; the third pixel row X ₁₃ , X ₂₃ ,..., X _i3 , ..., X _{(n-1) 3} , X _n3 direction; ......; ......; ......; the m pixel column _{X 1m, X 2m, ......,} X im, ......, X (n-1) m, row along the X _nm direction decoder circuit 51, A row drive circuit 52 is provided.

The first pixel column X ₁₁ , X ₂₁ ,..., X _i1 ,..., X _{(n−1) 1} , X _{n 1} is provided with a column power supply line P ₁ , and the second pixel column X ₁₂ , X ₂₂ , ., X _i2 ,..., X _{(n-1) 2} , X _n2 are provided with a column power supply line P ₂ , and the third pixel column X ₁₃ , X _{23 ,. (n-1)} 3, the X _n3 is provided a column power supply line _{P 3, ......; ......; ......} ; the m pixel column _{X 1m, X 2m, ......,} X im, ......, X ( _{n-1) m,} the column power supply line P _m is provided on the X _nm, power lines P ₁ for each _{column, P 2, P 3, ......} , the entire pixel array unit 5 via the P _m power supply line VDD It is connected to the.

The unit pixels X _ij in the pixel array unit 5 are sequentially scanned by the column decoder circuit 55, the row decoder circuit 51, and the row drive circuit 52, and readout of pixel signals and an electronic shutter operation are performed. Row drive lines _{W 1, W 2, ......,} W i, ......, W (n-), W n is the first pixel row _{X 11, X 12, X 13} , ......, X 1m; second pixel row _{X 21, X 22, X 23} , ......, X 2m; ......; i-th pixel row _{X i1, X i2, X i3} , ......, X im; ......; (n-1) th pixel row X _{(n-1) 1} , X _{(n-1) 2} , X _{(n-1) 3} , ..., X _{(n-1) m} ; nth pixel row _Xn1 , _Xn2 , _Xn3 , ..., Driving line (first driving line) of the storage gate electrode 14 wired for each row for each of the pixels X _ij (i = 1 to n; j = 1 to m) arranged in X _nm respectively A drive line (second drive line) of read gate electrode 19, a drive line (third drive line) R (i) of reset transistor TR _ij , and a drive line (fourth drive line) S of select transistor TS _ij (I) is represented by representing one drive line.

The row decoder circuit 51, the first pixel row _{X 11, X 12, X 13} , ......, X 1m; second pixel row _{X 21, X 22, X 23} , ......, X 2m; ......; i-th pixel Rows X _i1 , X _i2 , X _i3 ,..., X _im ;...: (N−1) pixel rows X _{(n−1) 1} , X _{(n−1) 2} , X _{(n−1) 3} ,..., X _{(n-1) m} ; a specific pixel row among the _n- th pixel row X _n1 , X _n2 , X _n3 ,..., X _nm is selected, and selection is performed via the row drive circuit 52 to the pixel rows, corresponding to the pixel row selected, row drive lines _{W 1, W 2, ......,} W i, ......, W (n-), from one of W _n, respectively A drive signal is provided.

The first pixel row _{X 11, X 21, ......,} X i1, ......, X (n1) 1, the pixel signal V _sig1 by the read signal line B ₁ provided X _n1 is the second pixel column _{X 12, X 22, ......,} X i2, ......, X (n-1) 2, the pixel signal V _sig2 by the read signal line B ₂ provided in the X _n2 is the third pixel column X _13, X _{23, ......, X i3, ......} , X (n-1) 3, X n3 pixel signal V _sig3 by the read signal line B ₃ provided in the, ..., m-th pixel column X _{1 m,} X _2m, .., X _im ,..., X _{(n−1) m} and X _nm , the pixel signal V _sigm is read out by the read signal line B _m . The pixel signals V _sig1 , V _sig2 , V _sig3 ,..., V _sigm read from the read signal lines B ₁ , B ₂ , B ₃ ,..., B _m are signal processing circuits SP ₁ , SP ₂ , At SP ₃ ,..., SP _m , analog or analog and digital signal processing is performed. Thereafter, the signal for each column subjected to the signal processing by the signal processing circuits SP ₁ , SP ₂ , SP ₃ ,..., SP _m is read out to the output signal line 56 by the column decoder circuit 55. Finally, the signal is output to an external circuit outside the semiconductor chip.

--- Global shutter operation ---
In the configuration of the solid-state imaging device according to the first embodiment shown in FIG. 7, the global shutter operation is performed as follows:
(A) First, the row drive lines _{W 1, W 2, ......,} W i, ......, W (n-1), through the W _n, all the pixels _{X ij (i = 1~n; j} = 1 as the potential of the respective channel leading to the charge discharging region 22 of ~m) becomes the potential of the conducting state at the same time, by simultaneously applying a sufficiently high voltage to the discharge gate electrode 21 of all the pixels X _ij, of all the pixels X _ij The signal charge of each photoelectric conversion diode unit D1 and the charge due to dark current are discharged. Thereafter, the signal charge generated by the incident light is accumulated in the second embedded layer region 12 of each photoelectric conversion diode portion D1 of all the pixels X _ij .

(B) Next, a period of time photoelectric conversion in each of the photoelectric conversion diode section D1 of all pixels X _ij, the accumulated signal charges to the second buried layer region 12, all pixels X _ij simultaneously, each buried channel Transfer to area 15. At this time, the _{first of} the row drive lines W ₁ , W ₂ ,..., W _i ,..., W _(n−1) , W _n is applied to the respective storage gate electrodes 14 of all the pixels X _ij . A high (H) level voltage is simultaneously applied through the drive line.
(C) Next, the _first drive line out of the row drive lines W ₁ , W ₂ ,..., W _i ,..., W _(n−1) , W _n accumulates each of all the pixels X _ij A low (L) level voltage is applied to the gate electrode 14, and the surface potential of the semiconductor region directly below the storage gate electrode 14 is pinned to hold signal charges in the respective buried channel regions 15 of each pixel X _ij. Do.

(D) Thereafter, in the state of the respective potentials of the storage gate electrode 14 is the row (L) level voltage of each pixel X _ij, each of the read gate electrode 19 of each pixel X _ij, sequentially high for each row ( the H) level voltage is applied through a second drive line, the signal charges held in the respective buried channel region 15 of each pixel X _ij, each of the charge detection region 20 of each pixel X _ij Transfer to
(E) In each charge detection area 20 of each pixel X _ij , the reset level before the signal charge is transferred and the signal level after the signal charge is transferred are compared with each pixel X _ij (i = 1 to n). Read out to the read signal lines B ₁ , B ₂ , B ₃ ,..., B _m through the amplification transistor TA _ij and the selection transistor TS _ij integrated in the inside of j = ₁ to _m) .

As described above, in the solid-state imaging device according to the first embodiment, in all the pixels X _ij (i = 1 to n; j = 1 to m), the operation of generating signal charges in the exposure period is simultaneously performed. It can be implemented and becomes a global shutter operation. That is, according to the solid-state imaging device according to the first embodiment, the global shutter operation is possible, and the potential difference for charge transfer is reliably ensured while maintaining the performance of low residual image, low dark current and low noise. It is possible to provide a solid-state imaging device which is easy to manufacture.

Second Embodiment
The inventor has already examined a pixel for a CMOS image sensor having a photogate electrode as shown in FIG. In the case of the pixel structure shown in FIG. 11, a gap is generated between the photogate electrode (first MOS gate electrode) 64 for photoelectric conversion and the second MOS gate electrode 62 for charge transfer, and the gap is the same as the source / drain It was necessary to connect by the n layer 61 of high impurity density. In the case of the pixel structure shown in FIG. 11, the gate voltage of the second MOS gate electrode 62 is set to a high level, and the charge of the buried channel region 15 which becomes a part of the region directly below the first MOS gate electrode 64 is When transferring to the detection region 20, the potential of the n layer 61 is in a floating state, so the potential is not determined, and a large afterimage may occur.

  In view of the problem of the pixel structure shown in FIG. 11, in the light detection device according to the second embodiment of the present invention, as shown in FIG. 8, a base portion 11 made of a p-type semiconductor layer and First transfer control means (15, 23, 44) provided on the upper part to control accumulation and transfer of the photoelectrically converted signal charges by the insulated gate structure, and first transfer control means (15, 23, 44) Buffer diode portion D2 formed of a pn junction and provided on the upper portion of the base portion 11 adjacent to the upper surface of the base portion 11 and on the upper portion of the base portion 11 adjacent to the buffer diode portion D2; The second transfer control means (19, 23) is provided adjacent to the second transfer control means (19, 23) for controlling the second transfer control means (19, 23). Detect the signal charge transferred by) And a charge detecting region 20 of n-type semiconductor region.

  The first transfer control means (15, 23, 44) of the light detection element according to the second embodiment comprises a photogate electrode 44 which constitutes a part of an insulated gate structure, and photoelectric conversion immediately below the photogate electrode 44. A buried channel region formed of a part of the p-type well region 23 serving as a conversion region and an n-type semiconductor region provided immediately below the photogate electrode 44 between the photoelectric conversion region and the buffer diode portion D2. And 15, and photoelectrically converted in the inside of the first transfer control means (15, 23, 44) to generate signal charges.

  As shown in FIG. 8, in the light detection element according to the second embodiment, a fourth embedded layer region is provided between the photogate electrode 44 provided immediately above the photoelectric conversion region and the read gate electrode 19 for charge transfer. Since the buffer diode portion D2 including the 17 and the third buried layer regions 18 is formed and the potential is fixed, the gate voltage of the read gate electrode 19 is set to a high level, and the first transfer control means (14, 15 , 16) when transferring the signal charge of the buried channel region 15 to the charge detection region 20, a potential gradient in one direction is formed to enable good charge transfer and no residual image is generated. In the light detection element according to the second embodiment of the present invention, it is desirable to cover the light shielding plate 24 with the region excluding the photogate electrode 44 for photoelectric conversion and the buffer diode portion D2.

  FIG. 9 shows an example of a plane pattern of the light detection element according to the second embodiment shown in FIG. 8, which has a rectangular plane pattern and includes a photoelectric conversion region and a buried channel region 15 inside. The photogate electrode 44, the buffer diode portion D2 forming a rectangular planar pattern, the read gate electrode 19 forming a rectangular planar pattern, and the charge detection region 20 forming a rectangular planar pattern are disposed inside the active region 30c from left to right. , Are arranged in a straight line. As shown in FIG. 9, the photoelectric conversion region, the buried channel region 15 and the buffer diode portion D2 are disposed inside the well region 23 on the plane pattern. Therefore, a cross-sectional view seen from the direction of VIIIA-VIIIA in FIG. 9 corresponds to FIG.

  FIG. 10 also shows an example of a planar pattern of the light detection element according to the second embodiment shown in FIG. 8, and a cross-sectional view taken along the line VIIIB-VIIIB in FIG. 10 corresponds to FIG. As shown in FIG. 10, a rectangular shaped photogate electrode 44 with a corner cut off, including a rectangular buried channel region 15 with a lower right corner cut out, and a buffer diode having a trapezoidal planar pattern The portion D2, the read gate electrode 19 having a triangular planar pattern, and the charge detection region 20 having a rectangular planar pattern are disposed inside the active region 30d, with the diagonal direction from the upper left direction to the lower right direction as a main path. , Arranged in a folded topology. As shown in FIG. 10, the photoelectric conversion region, the buried channel region 15 and the buffer diode portion D2 are disposed inside the well region 23 on the plane pattern. According to the topology of the plane pattern as shown in FIG. 10, since the photoelectric conversion region can be taken relatively wide, it is advantageous for reduction of the area of the active region 30d.

  According to the light detection element of the second embodiment, the buffer diode portion D2 is formed between the first transfer control means (15, 23, 44) and the second transfer control means (19, 23). Therefore, even if the photogate electrode 44 and the read gate electrode 19 are not formed with a narrow gap, potential dip or formation of a potential barrier can be prevented. Further, the difference between the potential of the buried channel region 15 where the photoelectrically converted charges are stored and the potential of the charge detection region 20 applies a binary voltage to the first transfer control means (15, 23, 44). Therefore, the charge transfer is facilitated. Furthermore, when charge is accumulated in the buried channel region 15, the surface of both the photoelectric conversion region and the buried channel region 15 is subjected to pinning operation, whereby the dark current is significantly reduced.

  As in the case of the solid-state imaging device according to the first embodiment, a large number of pixels are arranged on a semiconductor chip, with the light detection elements according to the second embodiment described with reference to FIGS. Thus, the pixel array can be configured to configure a solid-state imaging device. According to the solid-state imaging device according to the second embodiment, even in the case of the pixel structure having the photogate electrode, charge transfer is performed while maintaining the performance of low residual image, low dark current and low noise. Thus, it is possible to provide a solid-state imaging device in which the potential difference for the device is reliably ensured and the manufacturing process is easy.

(Other embodiments)
As described above, although the present invention has been described by the first and second embodiments, it should not be understood that the description and the drawings, which form a part of this disclosure, limit the present invention. Various alternative embodiments, examples and operation techniques will be apparent to those skilled in the art from this disclosure.
In the description of the first and second embodiments already described, the first conductivity type is described as p-type and the second conductivity type is n-type, but the first conductivity type is n-type and the second conductivity type is p It will be easily understood that the same effect can be obtained by reversing the electrical polarity as a type. In the description of the first and second embodiments, signal charges subjected to processing such as transfer and storage are electrons, and in the potential diagram, the lower direction (depth direction) of the diagram is the positive direction of the potential (potential) However, when the electrical polarity is reversed, the charge to be processed is a hole, and the potential shape showing the potential barrier, potential valley, potential well, etc. in the light detection element is shown in the figure. The downward direction (depth direction) is expressed as the negative direction of the potential.

Also, in the description of the first and second embodiments already described, a two-dimensional solid-state imaging device (area sensor) has been described as an example, but the light detection element of the present invention is a pixel of the two-dimensional solid-state imaging device It should not be interpreted as limited to being used only for X _ij . For example, in the two-dimensional matrix shown in FIG. 1, a plurality of light detection elements may be arranged one-dimensionally as pixels X _ij of a one-dimensional solid-state imaging device (line sensor) with j = m = 1. It should be easily understood from the contents of the above disclosure.
Thus, it is a matter of course that the present invention includes various embodiments and the like which are not described herein. Accordingly, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of claims appropriate from the above description.

11: base portion 12: second embedded layer region 13: first embedded layer region 14: storage gate electrode 15: embedded channel region 16: barrier region 17: fourth embedded layer region 18: third embedded layer Region 19: read gate electrode 20: charge detection region 21: discharge gate electrode 22: charge discharge region 23: well region 24: light shielding plate 30a, 30b, 30c, 30d: active region 44: photogate electrode 5: pixel array portion 51 ... Row decoder circuit 52 ... Row drive circuit 55 ... Column decoder circuit 56 ... Output signal line 61 ... n layer 62 ... Second MOS gate electrode 64 ... First MOS gate electrode

Claims (9)

A base portion comprising a semiconductor layer of a first conductivity type;
A first buried region of the first conductivity type provided in a part of the upper portion of the base portion;
A second buried region of a second conductivity type selectively provided under the first buried region and forming a photoelectric conversion diode part with a pn junction with the first buried region;
A first conductive type provided in contact with one end of the second embedded region in the other part of the upper portion of the base portion, and a well region having a higher impurity density than the base portion;
It is provided in the upper part of the well region so as to set a local barrier region on the one end side, and controls accumulation and transfer of signal charges photoelectrically converted by the photoelectric conversion diode unit by an insulated gate structure. First transfer control means,
A buffer diode portion consisting of a pn junction provided on the top of the well region adjacent to the first transfer control means at a position separated from the barrier region ;
Second transfer control means provided adjacent to the buffer diode portion and on the other end side of the upper portion of the well region , and controlling transfer of the signal charge by an insulated gate structure;
And contact with the other end is provided with a further portion of the other of the upper portion of the base portion, for detecting the signal charges transferred by said second transfer control means, a semiconductor region of a second conductivity type Charge detection area,
And a light detecting element characterized by comprising: The first transfer control means
Further comprising the provided above the well region, buried channel region made of a semiconductor region of a second conductivity type between said buffer diode portion and the barrier region,
The light detecting element according to claim 1 , wherein an upper portion of the well region on the one end side is used as the barrier region . Discharge control means adjacent to the photoelectric conversion diode unit in a direction different from that of the first transfer control means on a plane pattern and controlling transfer of charges by an insulated gate structure;
A charge discharging region formed of a semiconductor region of a second conductivity type, provided on the upper portion of the base portion adjacent to the discharge control means, for receiving the charge transferred by the discharge control means;
Light detecting device according to claim 1 or 2, further comprising and. Applying a voltage of a first potential to the first transfer control means, and transferring the signal charge from the photoelectric conversion diode unit to the buried channel region;
A voltage of a second potential different from the first potential is applied to the first transfer control means, and the surfaces of the barrier region and the buried channel region are filled with charges of the opposite polarity to the signal charges to realize pinning operation. The light detection element according to claim 2 , wherein A base portion comprising a semiconductor layer of a first conductivity type;
A first buried region of the first conductivity type provided in a part of the upper portion of the base portion;
A second buried region of a second conductivity type selectively provided under the first buried region and forming a photoelectric conversion diode part with a pn junction with the first buried region;
A first conductive type provided in contact with one end of the second embedded region in the other part of the upper portion of the base portion, and a well region having a higher impurity density than the base portion;
It is provided in the upper part of the well region so as to set a local barrier region on the one end side, and controls accumulation and transfer of signal charges photoelectrically converted by the photoelectric conversion diode unit by an insulated gate structure. First transfer control means,
A buffer diode portion consisting of a pn junction provided on the top of the well region adjacent to the first transfer control means at a position separated from the barrier region ;
Second transfer control means provided adjacent to the buffer diode portion and on the other end side of the upper portion of the well region , and controlling transfer of the signal charge by an insulated gate structure;
And contact with the other end is provided with a further portion of the other of the upper portion of the base portion, for detecting the signal charges transferred by said second transfer control means, a semiconductor region of a second conductivity type Charge detection area,
What is claimed is: 1. A solid-state imaging device comprising: a plurality of pixels arranged in a plurality of pixels. The first transfer control means of each of the pixels
Further comprising the provided above the well region, buried channel region made of a semiconductor region of a second conductivity type between said buffer diode portion and the barrier region,
The light detecting element according to claim 1 , wherein an upper portion of the well region on the one end side is used as the barrier region .
A solid-state imaging device according to claim 5 , comprising: The pixel array constitutes a matrix,
At the end of the exposure period in which all the pixels in the pixel array simultaneously perform an imaging operation, the signal charges generated in the photoelectric conversion diode unit are simultaneously transferred to the buried channel region of the respective pixels. A first drive line provided for each row of the matrix so as to simultaneously apply a voltage to the first transfer control means of the pixel of
Applying a voltage to the second transfer control unit of each pixel in order to read out the signal charges accumulated in the embedded channel region of each pixel to the charge detection region sequentially for each row; A second drive line provided for each row;
A row drive circuit for supplying a voltage to the first and second drive lines;
The solid-state imaging device according to claim 6 , further comprising Discharge control means adjacent to the photoelectric conversion diode portions of the pixels in a direction different from the first transfer control means on a plane pattern and controlling transfer of charges by an insulated gate structure;
A charge discharging region formed of a semiconductor region of a second conductivity type, provided on the upper side of the base portion adjacent to the discharge control means of each of the pixels, for receiving the charge transferred by the discharge control means;
The solid-state imaging device according to claim 7 , further comprising Applying a voltage of a first potential to the first transfer control unit of each of the pixels, and transferring the signal charge from the photoelectric conversion diode unit to the buried channel region;
A voltage of a second potential different from the first potential is applied to the first transfer control means of each of the pixels, and the surfaces of the barrier region and the buried channel region are filled with charges of the opposite polarity to the signal charges. The solid-state imaging device according to claim 7 , wherein a pinning operation is realized in each of the pixels.

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