JP2010056345A - Amplification type solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplification type solid state imaging device for reducing crosstalk between pixels with visible rays of light, and for increasing sensitivity with infrared rays of light by extending the depletion layer of each pixel to the original depth. <P>SOLUTION: The amplification type solid state imaging device includes: a photoelectric conversion element PD<SB>ij</SB>having a first conductive charge generation layer 12 whose impurity concentration is 10<SP>14</SP>cm<SP>-3</SP>or less and is 10<SP>11</SP>cm<SP>-3</SP>or more and a second conductive surface embedded region 13 embedded in a portion of the upper part of the charge generation layer 12; a first conductive transfer channel formation well 19 and an amplifier circuit formation well 18 embedded in the other portion of the upper part of the charge generation layer 12; a charge detection region 16 configured of the second conductive semiconductor region embedded in a portion of the upper part of the transfer channel formation well 19 to which signal charge is transferred from the photoelectric conversion element; and a block layer 21 arranged at the bottoms of the transfer channel formation well 19 and the amplifier circuit formation well 18, and configured of the second conductive semiconductor region arranged so as to be brought into contact with the charge generation layer 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to an amplification type solid-state imaging device having an amplifier circuit in a pixel portion.

  In general, as an amplification type solid-state imaging device, a device having a pixel portion having an amplification function and a scanning circuit arranged around the pixel portion, and reading out pixel data from the pixel portion by the scanning circuit is widely used. ing.

  As an example of such an amplification type solid-state imaging device, there is known an APS (Active Pixel Sensor) type image sensor composed of CMOS, which is advantageous for integrating a pixel portion with a peripheral driving circuit and a signal processing circuit. Yes. Among the APS type image sensors, the four-transistor type combining the embedded photodiode and the charge transfer to the detection unit has a high image quality with little random noise and fixed noise, and is becoming mainstream in recent years.

In FIG. 22, a buried photodiode is constituted by the p ^- epi layer 112 having a relatively low impurity density and the n-type surface buried region 113, and one transfer transistor and three-transistor amplifier circuit 117 are arranged in one pixel region. 4 is a cross section of a four-transistor pixel configuration arranged. As shown in FIG. 22, a p ⁺ pinning layer 114 is formed on the n-type surface buried region 113, and charges are transferred from the buried photodiode to the charge detection floating diffusion region 116 via the transfer gate electrode 115. Amplified by the amplifier circuit 117. Since integration with the peripheral CMOS circuit portion is necessary, a CMOS logic device in which a p ^- epi layer 112 having a relatively low impurity density is formed on a p ⁺ substrate having a high impurity density is used. . impurity concentration of the p ⁺ substrate 11 is 1 × ¹⁰ 18 ^{cm -3} or more, p ^- impurity concentration of the epitaxial layer 112 is 1 × ¹⁰ 15 ^{cm -3} approximately, p ^- thickness c of the epitaxial layer 112 is about 5 [mu] m. In addition, each of the three transistors constituting the amplifier circuit 117 is normally provided with a source region 152 and a drain region 153 provided on a p ⁺ well 118 having a higher impurity density than the epi layer 112, and a source region 152 and a drain region 153. And a gate electrode 151 provided on the upper part of the channel between the two.

The power supply voltage that can be used by the CMOS image sensor is about 3V, and a potential difference is necessary to completely transfer charges from the n-type surface buried region 113 to the charge detection floating diffusion region 116. The junction bias voltage between region 113 and p ^- epi layer 112 is about 1V. In this case, the relationship between the depletion layer depth d from the silicon surface and the impurity density of the substrate is as shown in FIG. When the impurity density of the p ^- epi layer 112 is about 1 × 10 ¹⁵ cm ⁻³ , the depletion layer depth d is about 2 μm. On the other hand, the wavelength dependence of incident light of the penetration depth of incident light into silicon is as shown in FIG. Here, in red light having a wavelength of 600 nm of visible light, the penetration depth of incident light is 2.2 μm, and 40% of the incident light undergoes photoelectric conversion in the neutral region. The electric charge generated in the neutral region spreads in all directions by diffusion, and therefore leaks to adjacent pixels, which becomes crosstalk between pixels. Large crosstalk causes a reduction in resolution and color mixing in a color element using a color filter, resulting in a reduction in saturation.

Among the applications of CMOS image sensors are imaging with near-infrared light up to a wavelength of 1 μm, such as imaging at night and distance measurement. In this case, as is clear from FIG. 24, the light penetration depth exceeds 10 μm. For this reason, a considerable portion of incident light undergoes photoelectric conversion in the p ⁺ substrate 111 and many of them are recombined in the p ⁺ substrate 125 as indicated by reference numeral 125 in FIG. That is, the sensitivity is very low.

As a method for reducing crosstalk between pixels, a method using an n substrate 211 is known. This is shown in FIG. A p ^- well 213 is formed on an n substrate 211 near an impurity density of 2 × 10 ¹⁴ cm ⁻³ and an n-type epi layer 212 having a similar impurity density thereon, which is used in a CCD having a vertical overflow drain structure. As a result, a pixel portion similar to that shown in FIG. 22 is formed. Since the power supply voltage VD is applied to the n substrate 211, the p ^- well 213 under the n-type surface buried region 113 constituting the buried photodiode is completely depleted, and a curve 221 formed in the depletion layer. The depth f of the potential peak indicated by is about 2 μm from the silicon surface. The charges generated on the surface side from the potential peak 221 reach the n-type surface buried region 113 without spreading laterally in accordance with the depleted electric field. Further, the charges generated on the deeper side than the potential peak 221 are discharged to the n substrate 211 as indicated by reference numeral 225. As described above, the crosstalk component is greatly reduced. However, the method using the n substrate 211 has a problem that the sensitivity to infrared light is hardly obtained because charges generated in the deep part of silicon are discharged to the n substrate 211.

As a method of ensuring sensitivity in near infrared light and reducing crosstalk between pixels, proposals for forming an image sensor on a high resistance substrate have been proposed (see Patent Document 1 and Non-Patent Document 1). ). In Patent Document 1, a CCD image sensor is formed on a high-resistivity epilayer, whereas in Non-Patent Document 2, a CMOS image sensor is formed on a p ^-- epi layer 312 having a high resistivity as shown in FIG. Formed.

In FIG. 26, the p ⁻ -epi layer 312 having an extremely low impurity density of about 1 × 10 ¹² cm ⁻³ is formed on the p ⁺ substrate 111 having a high impurity density of 1 × 10 ¹⁸ cm ⁻³ or more. Is formed to have a thickness g of about 20 μm, and the p ⁻ -epi layer 312 and the n-type surface buried region 113 constitute a buried photodiode. One transfer transistor and a three-transistor amplifier circuit 117 are arranged in one pixel area to constitute a four-transistor pixel. As shown in FIG. 26, a p ⁺ pinning layer 114 is formed on the n-type surface buried region 113, and charges are transferred from the buried photodiode to the charge detection floating diffusion region 116 via the transfer gate electrode 115. Amplified by the amplifier circuit 117. Each of the three transistors constituting the amplifier circuit 117 includes a source region 152 and a drain region 153 provided on the p ⁺ well 118, and a gate electrode provided on the channel between the source region 152 and the drain region 153. 151. With this structure, if a reverse bias potential of about 1 V is applied to the n-type surface buried region 113 constituting the buried photodiode with respect to the p ⁻ -epi layer 312, in principle, the lower side of the buried photodiode Is depleted to near the p ⁺ substrate 111, and the generated charge is guided to the photodiode by the vertical electric field in the depletion layer even for infrared light having a light penetration depth exceeding 10 μm. At the same time, it is predicted that the spread in the horizontal direction will be suppressed and the crosstalk between pixels will be small.
US Pat. No. 6,608,337 J. et al. Janesick et al., "CMOS Minimal Array", Proc. SPIE 6295, August 2006

However, as a result of analyzing the structure of FIG. 26 by device simulation, the depletion layer under the n-type surface buried region 113 forming the buried photodiode has the impurity density of the p ^{− −} epi layer 312 of 1 under the above driving conditions. It was found that the film stretched by about 4 μm at × 10 ¹³ cm ⁻³ and only by about 5 μm at 1 × 10 ¹² cm ⁻³ . That is, the merit of using the p ⁻ -epi layer 312 having a very low impurity density is completely lost from the relationship between the ideal depletion layer depth d shown in FIG. 23 and the impurity density of the substrate. As a result of investigating the reason, since the impurity density ratio with the p ⁺ well 118 at the same potential as that of the p ⁻ -epi layer 312 and usually about 1 × 10 ¹⁷ cm ⁻³ is very large, It has been found that the p ⁻ -epi layer 312 fills holes that should be depleted. That is, in the p ⁻ -epi layer 312, the depletion layer approximation does not hold when there is a high impurity density layer of the same conductivity type having a large impurity density ratio adjacent thereto. This phenomenon becomes significant when the impurity density is 1 × 10 ¹⁴ cm ⁻³ or less. This is supported by the fact that the original depletion layer is formed when the surface p ⁺ well 118 is removed. However, for a CMOS image sensor, various transistors must be formed in the p ⁺ well 118 on the surface portion, and cannot be eliminated. The same phenomenon also occurs from the high impurity density p ⁺ substrate 111 side.

Further, as shown in FIG. 26, a p ⁻ -epi layer 312 having an extremely low impurity density is formed between the n-type surface buried region 113 forming the buried photodiode and the floating diffusion region 116 for charge detection, and a potential on the way Since the barrier is not formed, the channel of the transfer gate electrode 115 is punched through and cannot be closed. That is, charge cannot be accumulated in the photodiode. Further, since there is no potential barrier below the charge detection floating diffusion region 116 as well as below the n-type surface buried region 113, a part of the charge generated in the deep portion of the p ⁻ -epi layer 312 is Then, it flows directly into the charge detection floating diffusion region 116 and does not become an effective signal. That is, the sensitivity is lowered.

  Therefore, the present invention is an amplification type solid-state imaging device capable of extending the depletion layer of each pixel to the original depth, reducing crosstalk between pixels in visible light, and increasing sensitivity in infrared light. The purpose is to provide.

In order to achieve the above object, according to a first aspect of the present invention, (a) a semiconductor having a first conductivity type and an impurity density of 10 ¹⁴ cm ⁻³ or less and 10 ¹¹ cm ⁻³ or more and a thickness of 10 μm or more and 50 μm or less. A photoelectric conversion element comprising a charge generation layer comprising a layer and a surface buried region comprising a semiconductor region of the second conductivity type embedded in a part of the charge generation layer; (b) an upper part of the charge generation layer A transfer channel forming well and an amplifier circuit are embedded in the other part so as to surround the surface buried region on the planar pattern and have the first conductivity type and an impurity density of 10 ¹⁵ cm ⁻³ or more and 10 ¹⁸ cm ⁻³ or less. A well, and (c) a transfer channel forming region formed of a second conductivity type semiconductor region embedded in a part of the upper portion of the well, and (d) an amplifier circuit formation. Use part of the top of the well An amplification circuit that amplifies and reads out the potential of the charge detection region, and (e) a second conductivity type semiconductor provided at the bottom of each of the transfer channel formation well and the amplification circuit formation well and in contact with the charge generation layer And a charge generation layer is a common layer of the plurality of pixels, and at least one of the transfer channel formation well and the amplification circuit formation well is electrically connected between the plurality of pixels. The gist of the present invention is that it is an amplification type solid-state imaging device that functions as an inter-pixel separation region.

The second aspect of the present invention is: (a) a charge generation layer comprising a semiconductor layer having a first conductivity type and an impurity density of 10 ¹⁴ cm ⁻³ or less and 10 ¹¹ cm ⁻³ or more, and a thickness of 10 μm or more and 50 μm or less; (B) a photoelectric conversion element having a surface buried region made of a semiconductor region of the second conductivity type embedded in a part of the upper part of the charge generation layer, and (b) a plane on the other part of the upper part of the charge generation layer. A transfer channel formation well and an amplifier circuit formation well embedded in a pattern so as to surround the surface buried region and having an impurity density of 10 ¹⁵ cm ⁻³ or more and 10 ¹⁸ cm ⁻³ or less, and (c) a transfer channel A first and second charge detection region which is composed of a second conductivity type semiconductor region embedded in a part of the upper portion of the formation well, and in which signal charges are transferred from the photoelectric conversion element; Consists of a part of the upper part, the first And an amplification circuit that amplifies and reads out the potential of the second charge detection region, and (e) second conductivity provided at the bottom of each of the transfer channel formation well and the amplification circuit formation well and in contact with the charge generation layer. And a charge generation layer is a common layer of the plurality of pixels, and at least one of the transfer channel formation well and the amplifier circuit formation well is located between the plurality of pixels. The gist of the present invention is that it is an amplification type solid-state imaging device that functions as an inter-pixel separation region that is electrically separated.

  According to the present invention, the amplification type solid-state imaging device capable of extending the depletion layer of each pixel to the original depth, reducing crosstalk between pixels in visible light, and increasing sensitivity in infrared light. Can be provided.

  Next, first to fifth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Also, the following first to fifth embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the component parts. The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the technical scope described in the claims.

(First embodiment)
As shown in FIG. 1, the amplification type solid-state imaging device (two-dimensional image sensor) according to the first embodiment of the present invention includes a pixel array unit 1 and peripheral circuit units (2, 3, 4, 5). They are integrated on the same semiconductor chip. In the pixel array unit 1, a large number of pixels X _ij (i = 1 to m; j = 1 to n: m and n are integers) are arranged in a two-dimensional matrix, and a rectangular image is captured. It constitutes an area. A vertical shift register (vertical scanning circuit) 3 is provided on the left side of the pixel array unit 1 via a timing generation circuit 4, and a horizontal shift register (horizontal scanning circuit) 2 is provided on the lower side. A bias generation circuit 7 is provided on the lower side of the right side of 1. In FIG. 1, the internal structure is illustrated only for the pixel X _ij in i row and j column, but each pixel X _{11 to} X _1m ; X _{21 to} X _2m ;...; X _{i1 to} X _{im; ·····; X} n1 _{~X nm,} similar to the pixel _{X ij} of row i and column j, the detection circuit _{D 11 ~D 1m; D 21 ~D} 2m; ·····; D i1 ~ D _im ; Dn _{1 to} D _nm and amplifier circuit (voltage reading buffer amplifier) A _{11 to} A _1m ; A _{21 to} A _2m ; ...; A _{i1 to} A _im ; ...; A _{n1 to} A _nm . As shown in FIG. 2, the detection circuit D _ij (i = 1 to m; j = 1 to n: m and n are integers) is provided above the substrate 11 made of semiconductor (silicon). A photoelectric conversion element (embedded photodiode) PD _ij and a charge transfer unit (transfer gate electrode) 15 are provided.

The pixel X _ij in the pixel array unit 1 is sequentially scanned by the timing generation circuit 4, the vertical shift register (vertical scanning circuit) 3 driven by the timing generation circuit 4, and the horizontal shift register (horizontal scanning circuit) 2, and the pixel signal Reading and electronic shutter operation are executed. That is, in the amplifying solid-state imaging device according to a first embodiment of the present invention, each pixel row _X 11 _{to X} pixel array unit _{1 1m; X 21 ~X 2m;} ·····; X i1 ~X _im ;..; scanning in the vertical direction in units of X _{n1 to} X _nm , whereby each pixel row X _{11 to} X _1m ; X _{21 to} X _2m ; ...; X _{i1 to} X _im ; _{·····; X} n1 ~X the pixel rows _X 11 pixel signals of _{nm ~X n1; X 12 ~X n2} ; ·····; X 1j ~X nj; ·····; X 1m The pixel signal is read out by a vertical signal line provided every .about.X _nm .

Each pixel _{X 11 ~X 1m; X 21 ~X} 2m; ·····; X i1 ~X im; ·····; For reading a signal from the X n1 _{to X nm,} generally conventional CMOS image sensor It is similar to, the lower (output side) of the pixel array unit 1, a plurality of column processing circuit _{Q 1, Q 2, ·····,} Q j, ·····, the _{Q m,} respectively pixels X _{11 to} X _n1 ; X _{12 to} X _n2 ;... X _{1j to} X _nj ;..., X _{1m to} X _nm are arranged to constitute the signal processing unit 5 is doing. The pixel signals of the pixel columns X _{11 to} X _n1 read out from the pixel array unit 1 by the vertical signal lines are sequentially input to the column processing circuit Q ₁ of the signal processing unit 5 and subjected to a process for removing pixel specific noise. The Similarly, the pixel signals of the pixel columns X _{12 to} X _n2 are sequentially input to the column processing circuit Q ₂ of the signal processing unit 5 and subjected to a process for removing pixel specific noise. pixel signals _1j to X _nj, the signal processing unit is sequentially input to the column processing circuit Q _j of 5, removal processing of the pixel-specific noise is performed. Further, the pixel signals of the pixel columns X _{1m to} X _nm are sequentially input to the column processing circuit Q _m of the signal processing unit 5 and subjected to pixel specific noise removal processing. That is, since each unit pixel X _ij of the pixel array unit 1 includes a characteristic error inherent to the MOS transistor or the like constituting the unit pixel X _ij , a video signal is formed as it is from the pixel signal read from each unit pixel X _ij. Then, the characteristic variation between the pixels X _ij affects the video signal and appears as noise in the image.

FIG. 2 shows an embedded photodiode (photoelectric conversion element) PD _ij (i = 1 to m; j = j) of the pixel X _ij constituting the pixel array unit 1 of the amplification type solid-state imaging device according to the first embodiment of the present invention. 1 to n: m and n are each an integer.) Is a cross section schematically showing a schematic structure along the charge transfer direction from the transfer gate electrode 15 to the charge detection region 16 (FIG. This corresponds roughly to a cross-sectional view taken along the line AA in FIG. As shown in FIG. 2, a silicon substrate of the first conductivity type (p ⁺ type) having a high impurity density with an impurity density of 1 × 10 ¹⁷ cm ⁻³ or more and 10 ²¹ cm ⁻³ or less (hereinafter simply referred to as “substrate”). ) A charge generation layer 12 composed of an epi layer of the first conductivity type (p ^{− −} type) having an impurity density of 1 × 10 ¹⁴ cm ⁻³ or less and 10 ¹¹ cm ⁻³ or more is formed on the layer 11 with a thickness a Are formed to be 10 μm or more and 50 μm or less, and the pixels X _ij , X _{ij + 1} ,... Of the amplification type solid-state imaging device according to the first embodiment are configured. That is, an embedded photodiode (hereinafter abbreviated as “photodiode”) with the charge generation layer 12 having an extremely low impurity density as an anode region and the second conductivity type (n-type) surface buried region 13 as a cathode region. PD _ij , PD _{ij + 1} ,..., And a four-transistor pixel X _ij X _{ij + 1} ,..., Each having _one transfer transistor and three-transistor amplifier circuits A _ij , A _{ij + 1 ,.} Has been.

As shown in FIG. 2, a first conductivity type (p ⁺ -type) pinning layer 14 is formed on each n-type surface buried region 13, and photodiodes PD _ij , Charges are transferred from the PD _{ij + 1} ,... To the charge detection region 16 and amplified by the amplifier circuits A _ij , A _{ij + 1,.} Each of the three transistors (see FIG. 7) constituting each of the amplifier circuits A _ij , A _{ij + 1} ,... Is on a first conductivity type (p ⁺ type) well (amplifier circuit formation well) 18 having a high impurity density. For example, a second conductivity type (n ⁺ type) source region 52 and an n ⁺ type drain region 53, and a gate electrode 51 provided above the channel between the source region 52 and the drain region 53, Formed with. The pinning layer 14 is a layer that suppresses generation of carriers on the dark surface, and is used as a preferable layer for reducing dark current. Therefore, in applications (applications) where dark current is not a problem, the pinning layer 14 may be omitted structurally.

The pixel X _ij of the amplification type solid-state imaging device according to the first embodiment further has an impurity density of 10 ¹⁵ cm in the region below the charge detection region 16 and the transfer gate electrode 15 and between adjacent photodiodes PD _{ij + 1.} ^A first conductivity type (p-type) transfer channel formation well 19 having a depth of ^{−3 to} 10 ¹⁸ cm ⁻³ and deeper than the n-type surface buried region 13 is formed. The amplifying circuit forming well 18 and the transfer channel forming well 19 are commonly supplied with a ground potential via a p ⁺ type top contact region 20. In the pixel X _ij of the amplification type solid-state imaging device according to the first embodiment, most of the boundary between the amplification circuit formation well 18 and the transfer channel formation well 19 on the surface and the charge generation layer 12 with an extremely low impurity density is the most. A block layer 21 of the second conductivity type (n-type) is provided in the bottom portion that occupies the area to block diffusion and inflow of holes (carriers) from the amplification circuit formation well 18 and the transfer channel formation well 19 to the charge generation layer 12. Yes.

An insulating film (not shown) is formed on the pinning layer 14 and further on the transfer channel formation well 19 between the pinning layer 14 and the charge detection region 16. Similarly, the insulation film is also insulated on the amplification circuit formation well 18. A film (not shown) is formed. The transfer gate electrode 15 is provided on the insulating film between the pinning layer 14 and the charge detection region 16, and the gate electrode 51 is provided on the insulating film between the source region 52 and the drain region 53. The insulating film is preferably a silicon oxide film (SiO ₂ film), but has an insulated gate structure of an insulated gate transistor (MIS transistor) using various insulating films other than the silicon oxide film (SiO ₂ film). May be. For example, an ONO film composed of a three-layered film of silicon oxide film (SiO ₂ film) / silicon nitride film (Si ₃ N ₄ film) / silicon oxide film (SiO ₂ film) may be used. Furthermore, at least one element of strontium (Sr), aluminum (Al), magnesium (Mg), yttrium (Y), hafnium (Hf), zirconium (Zr), tantalum (Ta), and bismuth (Bi) is contained. Oxides containing or silicon nitride containing these elements can be used as the insulating film.

The impurity density of the amplification circuit formation well 18 and the transfer channel formation well 19 is 1 × 10 ¹⁷ cm ⁻³ and the thickness is about 1 μm, and the impurity density of the block layer 21 is 1 × 10 ¹⁶ cm ⁻³ and the thickness is 0.4 μm. As a result of the device simulation, the depletion layer under the photodiode PD _ij has an impurity density of the charge generation layer 12 of about 15 μm at 1 × 10 ¹³ cm ⁻³ and about 25 μm at 1 × 10 ¹² cm ^−3. Thus, it has been found that diffusion inflow of holes (carriers) from the amplification circuit formation well 18 and the transfer channel formation well 19 to the charge generation layer 12 can be substantially blocked. Here, the potential of the block layer 21 is floating, and the Fermi level is approximately 0V. Further, when the impurity density of the substrate 11 is about 1 × 10 ¹⁸ cm ⁻³ and the charge generation layer 12 having an extremely low impurity density is formed thereon, the impurity density of the charge generation layer 12 is 1 × 10 ¹³ cm ^−3. Then, it was confirmed that the diffusion of holes (carriers) from the substrate 11 does not affect the formation of the depletion layer if the thickness is 15 μm or more and 1 × 10 ¹² cm ⁻³ if the thickness is 25 μm or more. In FIG. 2, reference numeral 22 denotes a curve indicating the position of a potential peak, reference numerals 23 _j−1 , 23 _j , and 23 _{j + 1} denote potential contour lines, and CTP denotes a charge drift path.

If the potential of the blocking layer 21 is fixed to a positive fixed potential instead of floating, the effect of blocking the diffusion and inflow of holes is further enhanced. 18, 19, and 20 show a method of fixing the potential of the block layer 21. 18 is a diagram schematically showing the periphery of the pixel array portion 1 in FIG. 1. FIG. 19 is an enlarged view of the corner portion C, and FIG. 20 is a cross-sectional view seen from the XX-XX direction of FIG. is there. In FIG. 19, since the block layer 21 exists below the amplification circuit formation well 18 and the transfer channel formation well 19, they are connected in a lattice pattern in the pixel area 1. Therefore surrounds the periphery of the pixel area in the well 81 of the deep second conductivity type (n-type), as well as connecting the deep well 81 in the block layer 21 as shown in FIG. 20, the well 81 the second conductivity type (n ⁺ If the contact layer 82 of the type is fixed to the fixed potential V _bias via the surface wiring (not shown), the block layer 21 becomes the fixed potential V _bias . That is, in silicon, a well 81 connected to the block layer 21, a contact layer 82 provided in the well 81, a surface wiring connected to the contact layer 82, and a connection to the surface wiring. The power supply circuit (not shown) constitutes means for fixing the potential of the block layer (block layer potential fixing means). However, the value of the fixed potential V _bias is set lower than the potential at which the block layer 21 is depleted so that a second conductivity type (n-type) channel is formed.

In FIG. 21, the impurity densities of the amplifier circuit formation well 18, the block layer 21, and the charge generation layer 12 are 1 × 10 ¹⁷ cm ⁻³ , 1 × 10 ¹⁶ cm ^−3, and 1 × 10 ¹³ cm ⁻³ , respectively. FIG. 6 is a potential diagram for explaining the effect when the potential of the block layer 21 is fixed. As shown in FIG. 21A, the potential of the holes in the path from the amplifier circuit formation well 18 through the block layer 21 to the charge generation layer 12 is V _B1 = 0.24 V when there is no block layer 21. However, when there is a block layer 21 as shown in FIG. 21B and this block layer 21 is in a floating state, V _B2 = 0.76V. Furthermore, as shown in FIG. 21 (c), there is a block layer 21, and if a bias, for example, a fixed potential V _bias = 0.5V is applied to the block layer 21, the voltage further increases to V _B3 = 1.26V, and hole injection It can be seen that can be further blocked.

  However, if the potential of the block layer 21 is fixed to the positive fixed potential Vbias, a part of the photoelectrically converted signal charge is absorbed by the block layer 21 and does not reach the surface buried region 13, resulting in a decrease in sensitivity. When the minimum potential (that is, the saturation potential) of the embedded region 13 is Vpd (min), it is necessary to satisfy Vbias <Vpd (min). On the other hand, if the potential of the block layer 21 is floating, the sensitivity is not lowered.

3 is a cross section in the direction in which the photodiodes PD _ij−1 , PD _ij , PD _{ij + 1} ,... Here, the pixel separation portion between the photodiode PD _ij−1 and the photodiode PD _ij and between the photodiode PD _ij and the photodiode PD _{ij + 1} has the same impurity density as that of the amplification circuit formation well 18. 10 ¹⁷ cm ⁻³ and a thickness of about 1 μm. In FIG. 3, a state is considered in which a charge close to saturation is accumulated in the center photodiode PD _ij , and the charge accumulation in the photodiodes PD _ij−1 and PD _{ij + 1} adjacent to both sides is small. At this time, the potential of the photodiode PD _ij is shallow, and the potentials of the photodiodes PD _ij−1 and PD _{ij + 1} are deep.

FIG. 4 shows a potential distribution in the charge flow path A between the photodiode PD _ij and the photodiode PD _{ij + 1} shown in FIG. In FIG. 4, the potential barrier from the photodiode PD _ij to the photodiode PD _{ij + 1} is represented by V1. When the potential of the photodiode PD _ij decreases too much, V1 decreases, and electric charge overflows from the photodiode PD _ij to the photodiode PD _{ij + 1} , and blooming occurs. To avoid this, as shown in FIG. 5, the signal TX applied to the transfer gate electrode 15 is such that the potential value Φ _TX (off) when the transfer transistor is off is positive. As a result, the potential Φ _PD (sat) when the photodiode PD _ij is saturated is also limited to a positive value, the state of the distribution curve F3 in FIG. 4 is avoided, the state of F2 is maintained, and the potential barrier V1 is secured. Is done.

FIG. 6 shows a planar positional relationship between the n-type surface buried region 13, the p-type amplifier circuit forming well 18 and the transfer channel forming well 19 constituting the photodiodes PD _ij , PD _{ij + 1} ,... Shown in FIG. Illustrate. Although not shown in FIG. 6, the n-type block layer 21 exists at the bottom of the p-type amplifier circuit well 18 and transfer channel formation well 19 as can be seen from FIG. The pattern occupies the combined shape of the amplification circuit formation well 18 and the transfer channel formation well 19 region. Further below that, there is a charge generation layer 12.

FIG. 7 shows an example of the amplifier circuit A _ij arranged in the amplifier circuit formation well 18 and the transfer channel formation well 19. As shown in FIG. 7, the charge detection region 16 includes a gate electrode of a signal readout transistor (amplification transistor) TA _ij constituting the amplification circuit A _ij and a reset transistor by surface wiring via a contact plug (not shown). A source electrode of TR _ij is connected. The drain electrode of the reset transistor TR _{ij and} the drain electrode of the signal readout transistor (amplification transistor) TA _ij are connected to the power supply V _DD respectively, and the source electrode of the signal readout transistor (amplification transistor) TA _ij is the switching transistor TS for pixel selection. It is connected to the drain electrode of _ij . The reset signal R _{i is set} to the high (H) level (R _i = “1”) to the reset gate electrode of the reset transistor TR _ij to discharge the charges accumulated in the charge detection region 16 respectively. Reset. The source electrode of the pixel selection switching transistor TS _ij is connected to the _j vertical signal lines B _j, and the vertical selection signal S _{i of i} horizontal lines is driven to the gate electrode by the timing generation circuit 4 so as to be vertical. It is given from the shift register (vertical scanning circuit) 3. For example, in FIG. 6, the n ⁺ -type source region 52 and the n ⁺ -type drain region 53 provided on the amplifier circuit formation well 18 and the channel between the source region 52 and the drain region 53 are provided. if the gate electrode 51 constitute a reset transistor _{TR ij,} by three ^{n +} -type region of the left reset transistor _{TR ij} in FIG. 6, the signal read-out transistor (amplification transistor) TA _ij and the switching transistor TS _ij Although a series circuit is configured, the present invention is not limited to this, and the layout of the amplifier circuit A _ij can have various topologies. Although depending on the circuit topology, for example, if the circuit configuration is such that the n ⁺ -type drain region 53 and the n ⁺ region adjacent to the left side of the drain region 53 are connected to the common power supply wiring V _DD , the drain region 53 And the n ⁺ region adjacent to the left side of the drain region 53 may be configured as a continuous and integral region.

As shown in FIG. 1, a constant current transistor T _{LNj serving as} a common load is connected to the j-th column vertical signal line B _j of the pixel array unit 1, for example, an amplifying circuit A _{ij in the} i-th row and j-th column. When, by the constant-current transistor _{T Lnj,} a source follower circuit is formed, the output _{V outj} of the source follower circuit is read out to the column processing circuit _{Q j.} Although not shown, the vertical signal line of another row _{B 1, B 2, ·····,} B j-1, B j + 1, ·····, similarly to _{B m,} the common Constant current transistors T _LN1 , T _LN2 ,..., T _LNj−1 , T _{LNj + 1} ,..., T _LNm are connected to form a source follower circuit. output _{V out1, V out2, ·····,} V outj-1, V outj + 1, ·····, V outm are each column processing circuit _{Q 1, Q 2, ·····,} Q j- ₁ , Q _{j + 1} ,..., Q _m are read out. In the case of the vertical signal line B _j shown in FIG. 7, the i row vertical selection signal S _{i is set} to the high level (S _i = “1”) at the gate electrode of the pixel selection switching transistor TS _ij of the amplifier circuit A _ij. A signal is applied to make the switching transistor TS _ij conductive, and a constant voltage Vb is applied from the bias generation circuit 7 to the gate electrode of the constant current transistor T _LNj , thereby amplifying the signal readout transistor (amplification transistor) TA _ij . The charges accumulated in the charge detection region 16 thus read out are read out of the pixel array unit 1 as the output V _outj of the source follower circuit.

Other examples of the planar positional relationship between the n-type surface buried region 13 and the p-type amplifier circuit forming well 18 and the transfer channel forming well 19 constituting the photodiodes PD _ij , PD _{ij + 1} ,... Shown in FIG. Is illustrated in FIG. In FIG. 6, n-type surface buried regions 13 constituting the photodiodes PD _{i, j} , PD _{i, j + 1} , PD _{i + 1, j} , PD _{i + 1, j + 1} ,. Although the transfer channel forming well 19 is in contact, there is a slight gap in FIG. 8, and only the p ⁺ -type pinning layer 14 exists in this portion. If the gap is small, hole diffusion into the charge generation layer 12 can be suppressed to a small extent. Although not shown in FIG. 8, the block layer 21 exists at the bottom of the amplification circuit formation well 18 and the transfer channel formation well 19 as can be seen from FIG. The pattern occupies the shape of the transfer channel formation well 19 region. Further below that, there is a charge generation layer 12. Note that the pixel layout according to the present invention is not limited to FIGS. 6 and 8, and other topologies that maintain the above relationship are possible.

In the pixel X _ij , X _{ij + 1} ,... Of the amplification type solid-state imaging device according to the first embodiment shown in FIG. 2, when the charge generation layer 12 as a whole has a very low impurity density, the depletion layer grows very deeply. Therefore, even if infrared light that penetrates deep into the charge generation layer 12 undergoes photoelectric conversion in the depletion layer and the generated charge moves directly upward due to the upward electric field, the incident light at the incident angle θ ₁ Obliquely incident light becomes a signal to adjacent pixels, resulting in crosstalk between pixels. Fortunately, the refractive index of silicon is as large as 3.73 for infrared light with a wavelength of 850 nm, and the incident light is incident obliquely at an incident angle θ ₁ from the air layer (refractive index 1) above the photoelectric conversion element to the Si layer through the SiO ₂ layer. Are pulled back in the vertical direction, and the emission angle (refraction angle) θ ₂ <θ ₁ is satisfied. This is shown in FIGS. For example, if the pixel size is 5.6 μm and the penetration depth into the silicon is 17 μm (this corresponds to the case of infrared light having a wavelength of 850 nm), the limit that the signal charge does not leak into the adjacent pixels The exit angle (refractive angle) θ ₂ of the laser beam is 10 degrees, and the incident angle θ ₁ from the air layer is 40 degrees. For this reason, the thickness of the charge generation layer 12 having an extremely low impurity density is preferably about 20 μm, and the deeper region is desirably used as the substrate 11 having a high impurity density to suppress diffusion. That is, it is desirable that the thickness of the epi layer forming the charge generation layer 12 with an extremely low impurity density is about 20 μm, and the lower side is the substrate 11 with a high impurity density.

In the amplification type solid-state imaging device according to the first embodiment, as the value of the impurity density of the charge generation layer 12 of each pixel X _ij , X _{ij + 1} ,..., The minority carrier diffusion length L _diff can be about several μm. Impurity density is desirable. Minority carrier diffusion length L _diff in the p-type high impurity density region is

L _diff = (D _n τ _n ) ^1/2 (1)
τ _n = 1 / (C _p p ² ) (2)

It is represented by Here, D _n is a minority carrier (electron) diffusion coefficient, C _p is an Auger coefficient, and p is a majority carrier (hole) impurity density. Here, considering the case of the impurity density p = 10 ¹⁸ , 3 × 10 ¹⁸ , 10 ¹⁹ cm ⁻³ , D _n = 7.5, 5.0, 3.3 cm ² / s, but C _p = 10 ^-30 to 10 ⁻³¹ cm ⁶ / s (DK Schroder, “Carrier Lifetimes in Silicon, American Institute of Electronics and Electrical Engineers (IEEE), Transactions on Electron devices (Vol. 44, p160-170, 1997)), L _diff = 26 to 71, 7 to 19, 1.7 to 4.7 μm. to prevent crosstalk, by placing a substrate 11 of high impurity density above 10 ¹⁸ cm ^-3 impurity density in the bottom of the charge generating layer 12 of very low impurity concentration, to suppress the diffusion of generated charge Desirable.

In the amplification type solid-state imaging device according to the first embodiment, as shown in FIG. 2, the charge generation layer 12 below the photodiodes PD _ij−1 , PD _{ij + 1} of the respective pixels X _ij , X _{ij + 1 ,.} When the impurity density is 1 × 10 ¹³ cm ⁻³ or less and the depth of the depletion layer edge is 15 μm or more, most of the charge generation layer 12 is depleted. Therefore, as shown in FIG. 24, it is possible to maintain sufficient sensitivity even for near-infrared light having a wavelength of 800 nm or more that penetrates 10 μm or more into silicon. Further, the generated charges are led to the photodiodes PD _ij , PD _{ij + 1} ,... By the vertical electric field in the depletion layer and become effective sensitivity, and the spread in the horizontal direction is suppressed and crosstalk between pixels is also suppressed. Few.

Further, according to the amplification type solid-state imaging device according to the first embodiment, the p-type is provided between the n-type surface buried region 13 and the charge detection region 16 constituting the respective photodiodes PD _ij , PD _{ij + 1,.} Therefore, the channel immediately below the transfer gate electrode 15 is not punched through and can be turned on / off by the gate voltage TX. That is, charges can be accumulated until the potential of the photodiodes PD _ij , PD _{ij + 1} ,... Becomes the off potential of the transfer transistor. In addition, since the p-type transfer channel formation well 19 is provided below the charge detection region 16, the charge generated in the deep portion of the charge generation layer 12 is prevented from flowing into the charge detection region 16, and is supplied to the charge drift path CTP. And the n-type surface buried regions 13 constituting the photodiodes PD _ij , PD _{ij + 1,.} That is, the sensitivity is improved. Furthermore, since the amplifier circuit formation well 18 and the p-type transfer channel formation well 19 are commonly fixed to the ground potential by the top contact region 20, the transfer transistor formed by the transfer gate electrode 15 even when the entire charge generation layer 12 is depleted. And the amplifier circuits A _ij , A _{ij + 1} ,... Can be stably operated.

-First Modification of First Embodiment-
As a method for making the off potential of the transfer transistor positive, the following method is possible. FIG. 9 is a diagram showing a well structure in the channel portion of the transfer transistor. The p-type transfer channel formation well 19 is formed so that the center of the thickness is located near the junction depth of the n-type surface buried region 13, and a block layer 21 is formed at the bottom of the p-type transfer channel forming well 19. The diffusion to the charge generation layer 12 is prevented. A p ^{− −} type cap layer 17 having an extremely low impurity density is provided on the p type transfer channel forming well 19 so that the transfer channel forming well 19 is not formed on the silicon surface. The cap layer 17 leaves the channel surface portion directly below the transfer gate electrode 15 as a p-layer having an extremely low impurity density, so that the channel potential immediately below the transfer gate electrode 15 is set by making the charge detection region 16 near the power supply potential. Is pulled to a positive potential, and the off potential of the transfer transistor can be made positive.

-Second modification of the first embodiment-
Another method for making the transfer transistor off-potential positive is shown in FIG. The p-type transfer channel forming well 19 is formed so that the center of the thickness is located near the junction depth of the n-type surface buried region 13, and a block layer 21 is formed at the bottom of the silicon surface. An n-type cap layer 29 is formed in the part. As a result, a buried channel structure is formed immediately below the transfer gate electrode 15, and the channel potential can be made positive even when the gate potential is zero. However, the channel directly under the transfer gate electrode 15 is an implantable, p-type transfer channel forming wells between n-type surface-embedded region 13 and the charge detecting region 16 constituting the photodiode PD _ij The presence of 19 prevents punch-through between the two. In Japanese Patent No. 3403601, a photodiode and a transfer transistor are formed on the normal p layer 112 shown in FIG. 22, and a barrier p layer shallower than the n layer forming the photodiode is formed on the channel portion of the transfer transistor, and on the barrier p layer. Discloses a technique for forming an n-layer, but it is intended for complete transfer and does not make the channel potential at the OFF state positive in order to prevent blooming.

(Second Embodiment)
In the amplification type solid-state imaging device according to the first embodiment, in order to prevent crosstalk between pixels with infrared light that penetrates deeply into silicon, an impurity density of 10 ¹⁸ cm ⁻³ or higher is high. It has been described that it is desirable to suppress the diffusion of the generated charges by arranging the p ⁺ type substrate 11 at the bottom of the charge generation layer 12 with an extremely low impurity density, but the amplification according to the second embodiment of the present invention In the solid-state solid-state imaging device, as another method for invalidating charges generated in the deep part of the substrate and preventing crosstalk, as shown in FIG. 13, an n-type substrate (hereinafter referred to as “n substrate”) 26 is used. A method of using will be described.

The structure of each pixel X _ij , X _{ij + 1} ,... Of the amplification type solid-state imaging device according to the second embodiment shown in FIG. 13 is the same as that of FIG. 2 except that the p ⁺ type substrate 11 is replaced with the n substrate 26. The configuration is the same, and the operation above the charge generation layer 12 is basically the same as in FIG.

However, in the amplification type solid-state imaging device according to the second embodiment, in the charge generation layer 12 with an extremely low impurity density, the peak of the potential indicated by the curve 22 in the depletion layer is the surface when the potential of the n substrate 26 is increased. The n substrate 26 and the charge generation layer 12 have the same potential (ground potential) or a value close thereto. The n substrate 26 has an impurity density as low as 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁵ cm ^{−3 in} order to prevent electrons on the n substrate 26 side from diffusing and flowing into the charge generation layer 12. Is desirable.

  As a conventional technique using an n substrate, a low impurity density p layer is formed on a low impurity density n substrate as disclosed in, for example, Japanese Patent Application Laid-Open No. 09-331058, and a CCD ( There is an example in which a charge-coupled device is formed, but a vertical overflow that applies a reverse bias potential of about 15 V to the n substrate and discharges excessive charges generated in the photoelectric conversion element in the p layer to the n substrate side. The drain structure is a technique different from the structure for preventing crosstalk in the amplification type solid-state imaging device according to the second embodiment.

(Third embodiment)
In the amplification type solid-state imaging device according to the third embodiment of the present invention, still another structure for preventing crosstalk between pixels due to obliquely incident light will be described.

  In an amplification type solid-state imaging device, a microlens is usually used to increase the proportion of light incident on a photodiode (photoelectric conversion element). Here, since the incident angle is vertical at the center of the light receiving section, but obliquely incident at the periphery, a method of shifting the position of the microlens 155 as shown in FIG. 27 according to the incident angle of light is known. (See JP 05-328233 A).

  In FIG. 27A showing the center of the light receiving portion, the center of the microlens 155 coincides with the center of the n-type surface buried region 113 constituting the photodiode (photoelectric conversion element). In FIG. 27 (b) showing the peripheral portion that is obliquely incident, the center of the microlens 155 is shifted by ΔXa from the center of the n-type surface buried region 113, so that the light collection center position on the silicon surface by the microlens 155 is obtained. F is matched with the center position of the photodiode.

On the other hand, in the amplification type solid-state imaging device according to the third embodiment of the present invention, infrared incident light penetrates deeply into the charge generation layer 12 having an extremely low impurity density. In FIG. 14A showing the center of the light receiving portion, the center of the microlens 155 coincides with the center position of the n-type surface buried region 13 constituting the photodiode, but FIG. 14B showing the peripheral portion where oblique incidence occurs. Then, the center of the microlens 155 is separated from the center of the n-type surface buried region 13.

ΔXb> ΔXa (3)

And the condensing center position F on the silicon surface by the microlens 155 is shifted in the direction of oblique incidence from the center position of the photodiode (shifted to the left in FIG. 14B). That is, the shift amount ΔXb in the peripheral portion of the microlens 155 is set larger than the normal shift amount ΔXa shown in FIG. Thereby, the charges generated in the deep part of the charge generation layer 12 having an extremely low impurity density can also remain in the same pixel region.

(Fourth embodiment)
For example, as disclosed in Japanese Patent Application Laid-Open No. 2002-64751, many proposals have already been made for an amplification type solid-state imaging device including a temporary charge holding unit in a pixel. However, the amplification type solid-state imaging device provided with the conventional charge holding unit has a problem that the signal charge of the charge holding unit becomes turbid due to incident light or charge inflow from the periphery.

The amplification type solid-state imaging device according to the fourth embodiment of the present invention shown in FIGS. 15 and 16 includes a temporary charge holding unit in the pixel, and the signal charge of the charge holding unit is incident light or charges from the surroundings. This is to improve the problem of turbidity due to inflow (FIG. 16 is a cross-sectional view seen from the direction BB in FIG. 15). As shown in FIG. 16, the first conductivity type (p ⁺ type) having a high impurity density of 1 × 10 ¹⁷ cm ⁻³ or more and 10 ²¹ cm ⁻³ or less and having an impurity density of 1 × 10 ¹⁷ cm ⁻³ or less. p ^{- -} type) impurity density of 1 × ¹⁰ 14 ^{cm -3} or less at, 10 ¹¹ cm ^-3 or more electrode thickness a charge generation layer 12 having a low impurity density is 10μm or more, and formed so as to be 50μm or less The pixels X _ij , X _{ij + 1} ,... Of the amplification type solid-state imaging device according to the fourth embodiment are configured.

Each pixel X _ij , X _{ij + 1} ,... Is embedded in the charge generation layer 12 and a part of the upper portion of the charge generation layer 12, and the second conductivity type (n-type) surface embedded region (light receiving) that receives light. The cathode region) 13 and the charge generation layer 12 are embedded in a part of the upper portion of the charge generation layer 12 so as to be spaced apart from the surface buried region 13 and have a higher impurity density than the surface buried region 13 and are generated by the surface buried region 13. A charge accumulation region 73 of a second conductivity type (n ⁺ type) that accumulates signal charges and a charge detection region 16 that receives signal charges accumulated by the charge accumulation region 73 are provided. The surface buried region 13 and the charge generation layer (anode region) 12 immediately below the surface buried region 13 constitute a photodiode (photoelectric conversion element) PD _ij . The charge storage region (cathode region) 73 and the transfer channel formation well (anode region) 19 immediately below the charge storage region 73 constitute a charge storage diode (charge storage element) CS _ij .

As can be seen from FIG. 15, a high impurity density p ⁺ type amplifier circuit formation well 18 and a transfer channel formation well 19 are embedded on the charge generation layer 12, and the charge accumulation region 73 shown in FIG. The charge detection region 16 is provided on the surface of the transfer channel formation well 19. Similar to the amplification type solid-state imaging device according to the first embodiment, the transfer channel forming well 19 constituting the pixel X _ij of the amplification type solid-state imaging device according to the fourth embodiment has an impurity density of 10 ¹⁵ cm ⁻³ or more. This is a p-type region that is 10 ¹⁸ cm ⁻³ or less and deeper than the n-type surface buried region 13. The amplifying circuit forming well 18 and the transfer channel forming well 19 are commonly supplied with a ground potential via a p ⁺ type top contact region 20. As shown in FIG. 15, each of the three transistors (see FIG. 7) constituting the amplifier circuit A _ij is disposed on the amplifier circuit formation well 18, and for example, an n ⁺ type source region 52 and an n ⁺ type The drain region 53 and the gate electrode 51 provided on the channel between the source region 52 and the drain region 53 are formed. For example, in FIG. 15, the n ⁺ -type source region 52 and the n ⁺ -type drain region 53 provided on the amplifier circuit formation well 18 and the channel between the source region 52 and the drain region 53 are provided. If the gate electrode 51 constitutes the reset transistor TR _ij , the n ⁺ -type drain region 54 and the n ⁺ -type source / drain shared region 56 provided on the amplifier circuit formation well 18, the drain region 54 and the source A signal readout transistor (amplification transistor) TA _ij is connected to the n ⁺ -type source / drain shared region 56 and the n ⁺ -type source region 58 at the gate electrode 55 provided above the channel between the drain shared regions 56, A gate electrode 57 provided on the upper part of the channel between the source / drain shared region 56 and the source region 58; Switch ing transistor TS _ij is constituted is not limited to this, the layout of the amplifier circuit A _ij can be variously topologies. For example, the n ⁺ -type drain region 53 and the n ⁺ -type drain region 54 and the n ⁺ -type drain region 54 are connected to the common power supply wiring V _DD , and may be configured as a continuous and integral region. Furthermore, as a countermeasure when receiving very bright light, as shown in FIG. 16, a discharge drain region 67 is provided in the transfer channel formation well 19 in contact with the left side of the surface buried region 13. The discharge drain region 67 can overflow the signal charge from the surface buried region 13 and discharge it to the discharge drain region 67.

Similar to the amplification type solid-state imaging device according to the first embodiment, the pixel X _ij of the amplification type solid-state imaging device according to the fourth embodiment includes the amplification circuit formation well 18, the transfer channel formation well 19, and the charge generation layer 12. The n-type block layer 21 is provided at the boundary between the amplifying circuit forming well 18 and the transfer channel forming well 19, and from the amplifying circuit forming well 18 and the transfer channel forming well 19 to the charge generation layer 12. The diffusion inflow of holes (carriers) is blocked.

A p ⁺ type pinning layer 14 is disposed on the surface buried region 13. A p ⁺ -type pinning layer 74 is disposed on the charge storage region 73. The pinning layer 14 and the pinning layer 74 are layers that suppress generation of carriers on the dark surface, and are used as preferable layers for reducing dark current. In applications (applications) where dark current is not a problem, the pinning layer 14 and the pinning layer 74 may be omitted from the structure.

The plan view of FIG. 15 is a top view of the upper surface of the silicon region as seen through the gate electrodes 66, 62, 15, 57, 55, 51. Although the channel forming well 19 is illustrated so as to surround the photodiode PD _ij and the charge storage diode (charge storage element) CS _ij , as can be seen from the cross-sectional view of FIG. 16, the charge storage diode ( The transfer channel formation well 19 exists below the charge storage element CS _ij , and the charge storage diode (charge storage element) CS _ij is buried above the transfer channel formation well 19. For this reason, the transfer channel forming well 19 is provided around the photodiode PD _ij as a planar pattern cut at a level deeper than the bottom of the charge storage diode (charge storage element) CS _ij and at a level parallel to the upper surface of the silicon region. It is comprised so that it may surround.

As the planar pattern of the uppermost surface of the silicon region shown in FIG. 15, the pinning layer 14 actually appears on the upper surface of the region of the rectangular photodiode PD _ij surrounded by the transfer channel formation well 19 to form the transfer channel. A pinning layer 74 appears on the upper surface of the region of the rectangular charge storage diode (charge storage element) CS _ij surrounded by the well 19. Further, in the plan view of FIG. 15, since the amplification circuit formation well 18 is disposed above the transfer channel formation well 19, the planar pattern on the uppermost surface of the silicon region includes a rectangular photodiode PD _ij , charge storage. The p layer covers the silicon surface region except for the region of the diode (charge storage element) _CSij , the charge detection region 16, the source / drain regions 52, 53, 54, 56, 58, the discharge drain region 67, and the like. Become. On the other hand, as a horizontal level pattern at a position deeper than the bottom of the charge storage diode (charge storage element) CS _ij , the p layer is surrounded by a well other than the rectangular photodiode PD _ij region.

On the pinning layer 14 and the pinning layer 74, on the transfer channel formation well 19 between the pinning layer 14 and the pinning layer 74, and on the transfer channel formation well 19 between the pinning layer 74 and the charge detection region 16 An insulating film (not shown) is formed. As the insulating film, a silicon oxide film is suitable, but as described in the first embodiment, various insulating films other than the silicon oxide film can be used. On the insulating film, the signal charge is transferred from the surface buried region 13 to the charge storage region 73 by controlling the potential of the first transfer channel formed between the surface buried region 13 and the charge storage region 73. A transfer gate electrode (storage transfer gate electrode) 62 is arranged to constitute a first potential control means, and the surface transfer region 13, the charge storage region 73 and the transfer gate electrode 62 constitute a first transfer transistor. . Further, the signal charge is transferred from the charge storage region 73 to the charge detection region 16 by controlling the potential of the second transfer channel formed between the charge storage region 73 and the charge detection region 16 on the insulating film. A transfer gate electrode (read transfer gate electrode) 15 is disposed to constitute a second potential control means, and the charge storage region 73, the charge detection region 16 and the transfer gate electrode 15 constitute a second transfer transistor. Further, an excessive charge is discharged from the surface buried region 13 to the drain region 67 by controlling the potential of the drain channel formed between the surface buried region 13 and the drain region 67 on the insulating film. The drain gate electrode 66 is disposed, and the surface buried region 13, the drain drain region 67, and the drain gate electrode 66 constitute a drain transistor. The discharge transistor resets the photodiode PD _ij or overflows only excess charge. In the plan view of FIG. 15, the amplifier circuit formation well 18 disposed above the transfer channel formation well 19 functions as the other transistor formation portion 68.

A light shielding layer 75 made of metal or the like is formed on the charge storage diode (charge storage element) CS _ij to prevent light from entering. The charges held in the charge storage diode (charge storage element) CS _ij are read out to the charge detection region 16 through the transfer gate electrode 15. On the other hand, the charge of the photodiode PD _ij is directly discharged to the discharge drain region 67 by the discharge gate electrode 66.

With this configuration, according to the amplification type solid-state imaging device according to the fourth embodiment, 1V about bias voltage between the n-type surface-embedded region 13 and the charge generation layer 12 constituting the photodiode PD _ij is By being applied, a depletion layer of 10 μm or more is formed in the charge generation layer 12, and high infrared sensitivity and low crosstalk are ensured. The electrons photoelectrically converted in the charge generation layer 12 are directed to the photodiode PD _ij along the charge drift path CTP and are prevented from flowing into the charge storage diode (charge storage element) CS _ij . That is, it is avoided that the charge held in the charge storage diode (charge storage element) CS _ij is turbid by the photoelectric conversion charge during the holding period. The fact that the charge storage diode (charge storage element) CS _ij has a diode structure having the pinning layer 74 makes it possible to minimize the generation of dark current here, and in the charge storage diode (charge storage element) CS _ij It is also avoided that the retained charge becomes turbid with the dark current charge.

With the above operation, according to the amplification type solid-state imaging device according to the fourth embodiment, it is possible to temporarily store pixel information without being affected by incident light in the charge storage diode (charge storage element) CS _ij. In addition, the photoelectric conversion accumulation operation such as the batch exposure operation and the read operation can be controlled independently.

(Fifth embodiment)
In the TOF type distance sensor that measures the distance from the time of flight (TOF) of light, since infrared light is usually used, a structure that can increase the infrared sensitivity is desirable. Accordingly, a TOF type distance sensor will be described as an amplification type solid-state imaging device according to the fifth embodiment of the present invention.

As shown in the cross-sectional structure of FIG. 17, the pixels X _ij , X _{ij + 1} ,... Of the amplification type solid-state imaging device according to the fifth embodiment of the present invention are the first conductivity type (p ⁺ type) and the impurity density is 1. A substrate 11 of × 10 ¹⁸ cm ⁻³ or more and a thickness of b = 10 μm or more are arranged on the substrate 11 and have a first conductivity type (p ⁻ -type) and an impurity density of 1 × 10 ¹⁴ cm ⁻³ or less. The charge generation layer 12 and a second conductivity type (n-type) surface buried region 33 disposed on the charge generation layer 12 are provided. An insulating film 34 is provided on the surface buried region 33, and a light receiving gate electrode 35 is disposed at the center on the insulating film 34, and first transfer gate electrodes are disposed on the left and right sides of the light receiving gate electrode 35. 37 and the second transfer gate electrode 36 are arranged.

In the case where the insulating film 34 is formed of a thermal oxide film, the thickness of the thermal oxide film may be about 150 nm or more and about 1000 nm or less, preferably about 200 nm or more and about 400 nm or less. In the case where the insulating film 34 is a dielectric film other than the thermal oxide film, an equivalent thickness calculated by the relative dielectric constant ε _r (ε _r = 3.8 at 1 MHz) of the thermal oxide film may be used. For example, if a CVD oxide film having a relative dielectric constant ε _r = 4.4 is used, the thickness obtained by multiplying the above thickness by 4.4 / 3.8 = 1.16 is set to a relative dielectric constant ε _r = 7. If a silicon nitride (Si ₃ N ₄ ) film is used, a thickness obtained by multiplying the above thickness by 7 / 3.8 = 1.84 may be adopted. However, it is preferable to use an oxide film (SiO ₂ film) formed by standard CMOS technology, and using a field oxide film in CMOS technology is suitable for simplifying the manufacturing process.

Although not plan view so as to surround the surface buried region 33 similarly to FIG. 15, a first conductivity type ^{(p +} -type) impurity density of 1 × ¹⁰ 17 ^{cm -3,} the about 1μm thick The transfer channel forming well 19 is disposed. Similarly to the plan view of FIG. 15, an amplification circuit formation well 18 is disposed above the transfer channel formation well 19, and the amplification circuit formation well 18 includes three transistors (FIG. 7) constituting the amplification circuit _Aij . Reference.) Is placed. A top contact region 20 is provided in at least one of the amplification circuit formation well 18 and the transfer channel formation well 19, and the amplification circuit formation well 18 and the transfer channel formation well 19 are fixed to the ground potential in the top contact region 20. Further, an n-type block layer 21 is formed at the bottom of the amplifier circuit formation well 18 and the transfer channel formation well 19, and serves as a hole diffusion blocking layer for the charge generation layer 12.

Each of the pixels X _ij of the amplification type solid-state imaging device according to the fifth embodiment includes the insulating film 34 directly under the light receiving gate electrode 35 in the center, the surface buried region 33, the charge generation layer 12, and the substrate 11. , X _{ij + 1} ,... Constitutes a photogate structure serving as a photoelectric conversion element. Actually, a part of the charge generation layer 12 of the first conductivity type (p type) located immediately below the light receiving gate electrode 35 functions as a main charge generation region of the photoelectric conversion element (photogate structure). . Carriers (electrons) generated in the charge generation region are injected into a part of the surface buried region 33 immediately above the charge generation region.

  The insulating film 34 extends from directly under the light receiving gate electrode 35 to below the left and right first transfer gate electrodes 37 and the second transfer gate electrode 36. The surface buried region 33 is disposed so as to extend right and left to below the first transfer gate electrode 37 and the second transfer gate electrode 36. That is, the first transfer gate electrode 37 in the surface buried region (other part of the surface buried region) 33 adjacent to the right side of the surface buried region 33 immediately below the light receiving gate electrode 35 (just above the charge generation region). A portion located immediately below the first transfer channel functions as a first transfer channel. On the other hand, in the surface buried region (other part of the surface buried region) 33 adjacent to the left side of the surface buried region 33 immediately below the light receiving gate electrode 35 (just above the charge generation region), the second transfer gate electrode 36 is formed. The portion located immediately below the second transfer channel functions as a second transfer channel.

  Further, as shown in FIG. 17, the first charge detection region 52a for accumulating the signal charges transferred by the first transfer gate electrode 37 is transferred by the second transfer gate electrode 36 into the right transfer channel formation well 19. A second charge detection region 52b for accumulating the signal charge is disposed inside the left transfer channel formation well 19. In FIG. 17, the first reset gate electrode 51a is further adjacent to the right side of the first charge detection region 52a, and the first reset source region 53a is opposed to the first charge detection region 52a via the first reset gate electrode 51a. Is arranged. On the other hand, the transfer channel forming well 19 on the left side of FIG. 17 is adjacent to the second charge detection region 52b, and is connected to the second charge detection region via the second reset gate electrode 51b and the second reset gate electrode 51b. A second reset source region 53b facing 52b is further arranged. The first charge detection region 52a, the first reset gate electrode 51a, and the first reset source region 53a form a MOS transistor that serves as a first reset transistor. The second charge detection region 52b, the second reset gate electrode 51b, A MOS transistor to be a second reset transistor is formed by the two reset source regions 53b. For each of the first reset gate electrode 51a and the second reset gate electrode 51b, all the control signals R are set to the high (H) level, and the charges accumulated in the first charge detection region 52a and the second charge detection region 52b are changed. The air is discharged to the first reset source region 53a and the second reset source region 53b, respectively, and the first charge detection region 52a and the second charge detection region 52b are reset.

  The first transfer gate electrode 37 and the second transfer gate electrode 36 cause the potentials of the first and second transfer channels to electrostatically pass through the insulating films 34 formed above the first and second transfer channels, respectively. And the signal charges are alternately transferred to the second conductivity type (n-type) first charge detection region 52a and the second charge detection region 52b through the first and second transfer channels, respectively. The first charge detection region 52a and the second charge detection region 52b are semiconductor regions having a higher impurity density than the surface buried region 33, respectively. As is apparent from FIG. 17, the surface buried region 33 is formed so as to be in contact with the left and right first charge detection regions 52a and second charge detection regions 52b.

In FIG. 17, reference numeral 22 indicates the position of the depletion layer end, reference numerals 23 _j-1 and 23 _j indicate potential contour lines, and CTP indicates a charge drift path.

The amplification type solid-state imaging device according to the fifth embodiment of the present invention is configured by arranging the pixels X _ij , X _{ij + 1} ,... As shown in FIG. In the amplification type solid-state imaging device according to the fifth embodiment of the present invention, in each pixel X _ij , X _{ij + 1} ,..., The light receiving gate electrode 35, the first transfer gate electrode 37, and By applying a driving voltage of several volts to the second transfer gate electrode 36, a depletion layer of 10 μm or more is formed in the charge generation layer 12, and high infrared sensitivity and low crosstalk are ensured. Further, the potential of the transfer channel formation well 19 can be stabilized by the top contact region 20 on the surface.

  In the example of FIG. 17, the case where the photoelectric conversion element has a photogate structure of a MOS structure through a thick insulating film 34 has been described, but the present invention is applied when the photoelectric conversion element of FIG. 17 is replaced with a photodiode. Of course, it is also possible.

(Other embodiments)
As described above, the present invention has been described according to the first to fifth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the description of the first to fifth embodiments already described, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type is n-type and the second conductivity type is n-type. Even in the case of the p-type, it can be easily understood that the same effect can be obtained if the electrical polarity is reversed (in this case, if attention is paid to the photodiodes PD _ij , PD _{ij + 1,.} It will not be necessary to explain that the first main electrode region becomes the cathode region and the p-type second main electrode region becomes the anode region.)

  In the description of the first to fifth embodiments, the case where silicon is used as the semiconductor material has been described. However, even in the case of other semiconductors such as germanium (Ge) and gallium arsenide (GaAs), the semiconductor material is used. The technical idea of the present invention can be similarly applied if the relative dielectric constant is appropriately modified in consideration of the impurity density of the intrinsic semiconductor.

  Further, for example, in the description of the first embodiment, the two-dimensional solid-state imaging device (area sensor) has been exemplarily described. However, in the two-dimensional matrix shown in FIG. It should be easily understood from the contents of the above disclosure that a plurality of semiconductor distance measuring elements may be arranged one-dimensionally as pixels of a three-dimensional solid-state imaging device (line sensor).

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a typical top view explaining the layout on the semiconductor chip of the amplification type solid-state imaging device (two-dimensional solid-state imaging device) concerning the 1st embodiment of the present invention. It is a figure which shows the structure of the pixel part of the amplification type solid-state imaging device of 1st Embodiment shown in FIG. ). It is a figure which shows the structure of the pixel part of the amplification type solid-state imaging device shown in FIG. 2 in another cross section. It is a figure which shows potential distribution in the electric charge transfer path | route between the pixels of the amplification type solid-state imaging device which concerns on 1st Embodiment. It is a figure which shows potential distribution in the path | route from the photodiode which comprises the pixel of the amplification type solid-state imaging device which concerns on 1st Embodiment to an electric charge detection area | region. It is a top view which paid its attention to four pixels of the amplification type solid-state imaging device concerning a 1st embodiment. It is a circuit diagram which shows the specific example of the 3 transistor amplifier circuit arrange | positioned at each pixel of the amplification type solid-state imaging device which concerns on 1st Embodiment. It is another top view which paid its attention to four pixels of the amplification type solid-state imaging device concerning a 1st embodiment. It is a figure which shows the well structure in the channel part of the transfer transistor arrange | positioned at each pixel of the amplification type solid-state imaging device which concerns on the 1st modification of the 1st Embodiment of this invention. It is a figure which shows the well structure in the channel part of the transfer transistor arrange | positioned at each pixel of the amplification type solid-state imaging device which concerns on the 2nd modification of the 1st Embodiment of this invention. It is a schematic diagram which shows a mode that light penetrate | invades into silicon | silicone with respect to the light which inclines into an amplification type solid-state imaging device with the incident angle (theta) ₁ by the outgoing angle (refraction angle) (theta) ₂ <(theta) ₁ . Is a diagram showing the angle of the light obliquely incident at an incident angle theta ₁ to the light receiving portion surface of the amplifying solid-state imaging device, the relationship between the angle of light traveling in the silicon at the emission angle (refraction angle) θ _{2 <θ 1} . It is a figure which shows the structure of the pixel part of the amplification type solid-state imaging device concerning the 2nd Embodiment of this invention in a cross section. It is a figure which shows the formation position of the micro lens in the amplification type solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is a top view of an amplification type solid imaging device provided with a charge storage diode (charge storage element) in a pixel of an amplification type solid imaging device concerning a 4th embodiment of the present invention. It is sectional drawing seen from the BB direction of the pixel of the amplification type solid-state imaging device shown in FIG. It is a figure which shows the structure of the pixel part in the distance sensor which is an amplification type solid-state imaging device concerning the 5th Embodiment of this invention in a cross section. 1 is a plan view schematically showing the periphery of a pixel array unit 1 of an amplification type solid-state imaging device according to a first embodiment of the present invention. It is a top view which expands and shows the corner part C of FIG. It is sectional drawing seen from the XX-XX direction of FIG. It is a potential diagram explaining the effect when the potential of the block layer 21 is fixed. It is sectional drawing of the pixel part of the conventional amplification type solid-state imaging device. It is a figure which shows the relationship between the impurity density of a board | substrate, and the depletion layer depth. It is a figure which shows the relationship between an incident light wavelength and the penetration depth in a silicon | silicone. It is sectional drawing of the pixel part of the other conventional amplification type solid-state imaging device. It is sectional drawing of the pixel part of another conventional amplification type solid-state imaging device. It is a figure which shows the formation position of the micro lens in the conventional amplification type solid-state imaging device.

Explanation of symbols

A _ij ... amplifier circuit B _j ... vertical signal line CS _ij ... charge storage diode (charge storage element)
CTP ... Charge drift path D _ij ... Detection circuit PD _ij ... Photodiode (embedded photodiode)
Q _j ... column processing circuit TR _ij ... reset transistor TS _ij ... switching transistor TR _ij ... reset transistor X _ij ... pixel 1 ... pixel array section 4 ... timing generation circuit 5 ... signal processing section 7 ... bias generation circuit 11 ... substrate 12 ... Charge generation layer 13 ... Surface buried region 14 ... Pinning layer 15 ... Transfer gate electrode 16 ... Charge detection region 17 ... Cap layer 18 ... Amplification circuit formation well 19 ... Transfer channel formation well 20 ... Top contact region 21 ... Block layer 22 ... Curve showing peak of potential 26 ... n substrate 29 ... cap layer 33 ... surface buried region 34 ... insulating film 35 ... light receiving gate electrode 36 ... second transfer gate electrode 37 ... first transfer gate electrode 51 ... gate electrode 51a ... first 1 reset gate electrode 51b 2nd reset gate electrode 5 2, 58 ... Source region 52a ... First charge detection region 52b ... Second charge detection region 53, 54 ... Drain region 53a ... First reset source region 53b ... Second reset source region 55, 57 ... Gate electrode 56 ... Source electrode Shared drain region 62 ... Transfer gate electrode 66 ... Discharge gate electrode 67 ... Discharge drain region 68 ... Transistor formation part 73 ... Charge storage region 74 ... Pinning layer 75 ... Light shielding layer 81 ... Well 82 ... Contact layer 112 ... Epi layer 112 ... p Layer 113 ... Surface buried region 114 ... Pinning layer 115 ... Transfer gate electrode 116 ... Charge detection floating diffusion region 117 ... Transistor amplifier circuit 117 ... Amplifier circuit 118 ... Well 125 ... Substrate 151 ... Gate electrode 152 ... Source region 153 ... Drain Area 155 ... micro lens 211 ... n substrate 12 ... n-type epitaxial layer 213 ... well 221 ... depletion layer end 312 ... epilayer

Claims (10)

A charge generation layer comprising a semiconductor layer of the first conductivity type and having an impurity density of 10 ¹⁴ cm ⁻³ or less and 10 ¹¹ cm ⁻³ or more and a thickness of 10 μm or more and 50 μm or less, and embedded in a part of the upper part of the charge generation layer A photoelectric conversion element having a surface buried region made of a second conductivity type semiconductor region;
Another portion of the upper portion of the charge generation layer is embedded so as to surround the surface buried region on a planar pattern, and is transferred with an impurity density of 10 ¹⁵ cm ⁻³ or more and 10 ¹⁸ cm ⁻³ or less in the first conductivity type. A channel formation well and an amplification circuit formation well;
A charge detection region comprising a semiconductor region of a second conductivity type embedded in a part of an upper portion of the transfer channel forming well, wherein a signal charge is transferred from the photoelectric conversion element;
An amplification circuit configured using a part of the upper part of the amplification circuit formation well, and amplifying and reading out the potential of the charge detection region;
A plurality of pixels including a block layer made of a semiconductor region of a second conductivity type provided at the bottom of each of the transfer channel formation well and the amplification circuit formation well and in contact with the charge generation layer; The charge generation layer is a common layer of the plurality of pixels, and at least one of the transfer channel formation well and the amplification circuit formation well functions as an inter-pixel isolation region that electrically isolates the plurality of pixels. A feature of the amplification type solid-state imaging device.   The amplification type solid-state imaging device according to claim 1, further comprising a light-shielding charge storage element in the transfer channel forming well. A charge generation layer comprising a semiconductor layer of the first conductivity type and having an impurity density of 10 ¹⁴ cm ⁻³ or less and 10 ¹¹ cm ⁻³ or more and a thickness of 10 μm or more and 50 μm or less, and embedded in a part of the upper part of the charge generation layer A photoelectric conversion element having a surface buried region made of a second conductivity type semiconductor region;
Another portion of the upper portion of the charge generation layer is embedded so as to surround the surface buried region on a planar pattern, and is transferred with an impurity density of 10 ¹⁵ cm ⁻³ or more and 10 ¹⁸ cm ⁻³ or less in the first conductivity type. A channel formation well and an amplification circuit formation well;
A first and second charge detection region comprising a second conductivity type semiconductor region embedded in a part of the upper portion of the transfer channel forming well, wherein signal charges are transferred from the photoelectric conversion element;
An amplifying circuit configured using a part of the upper part of the amplifying circuit forming well, and amplifying and reading out the potentials of the first and second charge detection regions,
A plurality of pixels including a block layer made of a semiconductor region of a second conductivity type provided at the bottom of each of the transfer channel formation well and the amplification circuit formation well and in contact with the charge generation layer; The charge generation layer is a common layer of the plurality of pixels, and at least one of the transfer channel formation well and the amplification circuit formation well functions as an inter-pixel isolation region that electrically isolates the plurality of pixels. A feature of the amplification type solid-state imaging device. 4. The substrate according to claim 1, further comprising a substrate made of a semiconductor having a first conductivity type and an impurity density of 10 ¹⁷ cm ⁻³ or more and 10 ²¹ cm ⁻³ or less on a lower surface of the charge generation layer. The amplification type solid-state imaging device according to item. 4. The substrate according to claim 1, further comprising a substrate made of a semiconductor having a second conductivity type and having an impurity density of 10 ¹³ cm ⁻³ or more and 10 ¹⁵ cm ⁻³ or less on a lower surface of the charge generation layer. 2. The amplification type solid-state imaging device according to item 1. The pixel is
An insulating film provided on the surface of the transfer channel forming well;
A transfer gate electrode provided on the insulating film between the photoelectric conversion element and the charge detection region;
The surface buried region, the charge detection region, and the transfer gate electrode transfer signal charges from the surface buried region to the charge detection region via a transfer channel provided above the transfer channel formation well. The amplification type solid-state imaging device according to claim 1, wherein a transfer transistor is configured.   The amplification type solid-state imaging device according to claim 6, wherein the potential of the transfer channel when the transfer transistor is off is positive.   The amplification type solid-state imaging device according to claim 6, further comprising a contact region for fixing a potential of the transfer channel in the transfer channel formation well. The pixel is
An insulating film provided on the surface of the transfer channel forming well;
A first transfer gate electrode provided on the insulating film between the photoelectric conversion element and the first charge detection region;
A second transfer gate electrode provided on the insulating film between the photoelectric conversion element and the second charge detection region;
The surface buried region, the first charge detection region, and the first transfer gate electrode from the surface buried region through the first transfer channel provided on the transfer channel formation well. A first transfer transistor configured to transfer a signal charge to the first charge detection region;
The surface buried region, the second charge detection region, and the second transfer gate electrode, from the surface buried region through the second transfer channel provided on the transfer channel forming well. The amplification type solid-state imaging device according to claim 3, wherein a second transfer transistor configured to transfer a signal charge to the second charge detection region is configured.   The amplification type solid-state imaging device according to claim 1, further comprising means for fixing a potential of the block layer.