JP6534677B2 - スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ - Google Patents

スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ Download PDF

Info

Publication number
JP6534677B2
JP6534677B2 JP2016553573A JP2016553573A JP6534677B2 JP 6534677 B2 JP6534677 B2 JP 6534677B2 JP 2016553573 A JP2016553573 A JP 2016553573A JP 2016553573 A JP2016553573 A JP 2016553573A JP 6534677 B2 JP6534677 B2 JP 6534677B2
Authority
JP
Japan
Prior art keywords
chip
power supply
fet
supply system
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016553573A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017511976A5 (enExample
JP2017511976A (ja
Inventor
ディンカー ジョシ ラジェヴ
ディンカー ジョシ ラジェヴ
Original Assignee
日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本テキサス・インスツルメンツ合同会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ合同会社
Publication of JP2017511976A publication Critical patent/JP2017511976A/ja
Publication of JP2017511976A5 publication Critical patent/JP2017511976A5/ja
Application granted granted Critical
Publication of JP6534677B2 publication Critical patent/JP6534677B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H10W90/811—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H10W70/411—
    • H10W70/424—
    • H10W70/461—
    • H10W70/468—
    • H10W70/479—
    • H10W70/481—
    • H10W74/129—
    • H10W90/00—
    • H10W70/65—
    • H10W74/111—

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Dc-Dc Converters (AREA)
JP2016553573A 2014-02-20 2015-02-20 スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ Active JP6534677B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/185,502 US9136256B2 (en) 2014-02-20 2014-02-20 Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips
US14/185,502 2014-02-20
PCT/US2015/016739 WO2015127159A1 (en) 2014-02-20 2015-02-20 Converter having partially thinned leadframe with stacked chips and interposer

Publications (3)

Publication Number Publication Date
JP2017511976A JP2017511976A (ja) 2017-04-27
JP2017511976A5 JP2017511976A5 (enExample) 2018-04-05
JP6534677B2 true JP6534677B2 (ja) 2019-06-26

Family

ID=53798782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016553573A Active JP6534677B2 (ja) 2014-02-20 2015-02-20 スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ

Country Status (5)

Country Link
US (2) US9136256B2 (enExample)
EP (1) EP3108503B1 (enExample)
JP (1) JP6534677B2 (enExample)
CN (1) CN106030788B (enExample)
WO (1) WO2015127159A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8587099B1 (en) * 2012-05-02 2013-11-19 Texas Instruments Incorporated Leadframe having selective planishing
US10312184B2 (en) 2015-11-04 2019-06-04 Texas Instruments Incorporated Semiconductor systems having premolded dual leadframes
US20200135632A1 (en) * 2018-10-24 2020-04-30 Texas Instruments Incorporated Die isolation on a substrate
CN109545697B (zh) * 2018-12-26 2024-06-18 桂林电子科技大学 半导体封装方法及半导体封装结构
US10964629B2 (en) 2019-01-18 2021-03-30 Texas Instruments Incorporated Siderail with mold compound relief

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3609684B2 (ja) * 2000-03-28 2005-01-12 三洋電機株式会社 半導体装置およびその製造方法
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
DE102005055761B4 (de) * 2005-11-21 2008-02-07 Infineon Technologies Ag Leistungshalbleiterbauelement mit Halbleiterchipstapel in Brückenschaltung und Verfahren zur Herstellung desselben
US20080036078A1 (en) 2006-08-14 2008-02-14 Ciclon Semiconductor Device Corp. Wirebond-less semiconductor package
US8263434B2 (en) 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US20120326287A1 (en) * 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US20120200281A1 (en) * 2011-02-07 2012-08-09 Texas Instruments Incorporated Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing
US20120228696A1 (en) * 2011-03-07 2012-09-13 Texas Instruments Incorporated Stacked die power converter
US8669650B2 (en) * 2011-03-31 2014-03-11 Alpha & Omega Semiconductor, Inc. Flip chip semiconductor device
US9508633B2 (en) 2011-08-22 2016-11-29 Texas Instruments Incorporated High performance power transistor having ultra-thin package
US20130082383A1 (en) 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
US9184122B2 (en) * 2012-06-06 2015-11-10 Stats Chippac Ltd. Integrated circuit packaging system with interposer and method of manufacture thereof

Also Published As

Publication number Publication date
EP3108503B1 (en) 2019-04-10
WO2015127159A1 (en) 2015-08-27
CN106030788B (zh) 2019-03-08
US20150348890A1 (en) 2015-12-03
US20150235999A1 (en) 2015-08-20
JP2017511976A (ja) 2017-04-27
US9136256B2 (en) 2015-09-15
EP3108503A4 (en) 2017-11-22
EP3108503A1 (en) 2016-12-28
CN106030788A (zh) 2016-10-12
US9355946B2 (en) 2016-05-31

Similar Documents

Publication Publication Date Title
JP6509885B2 (ja) 半導体チップの端子を有するｄｃ−ｄｃコンバータ
US9425132B2 (en) Stacked synchronous buck converter having chip embedded in outside recess of leadframe
JP6053752B2 (ja) カスタマイズされた占有面積を有する極薄パワートランジスタ及び同期バックコンバータ
CN108155168B (zh) 电子器件
CN115985868A (zh) 具有双侧冷却的功率模块封装
JP6534677B2 (ja) スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ
CN107546191A (zh) 具有单列直插引线模块的半导体功率器件及其制备方法
US20220293525A1 (en) Packaged half-bridge circuit
CN101421840A (zh) 具有双暴露表面的封装式半导体装置及其制造方法
CN120221420A (zh) 半导体结构及其制备方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20160823

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180219

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180219

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190508

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190529

R150 Certificate of patent or registration of utility model

Ref document number: 6534677

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250