JP6506814B2 - Solid-state imaging device and camera - Google Patents

Description

  The present invention relates to a solid-state imaging device and a camera.

  Patent Document 1 relates to a solid-state imaging device, which describes a manufacturing method for reliably achieving separation of signal charges between photoelectric conversion regions. In the manufacturing method, a first pixel isolation region is formed by introducing an impurity into a semiconductor substrate, a first epitaxial growth layer is formed on the surface of the semiconductor substrate, and a first pixel is penetrated through the first epitaxial growth layer. A second pixel isolation region is formed to abut on the isolation region.

  Patent Document 2 relates to a solid-state imaging device, in which a method of manufacturing a solid-state imaging device which suppresses generation of dark current in an accumulation layer without mixing even if the unit pixel is miniaturized is disclosed. Is described. In the manufacturing method, a photodiode is formed on an n-type semiconductor layer disposed on an n-type semiconductor via a silicon oxide film, and a p-type pixel isolation region is formed to surround the photodiode, Form the front side p + accumulation layer. In the manufacturing method, thereafter, ions are implanted into the n-type semiconductor layer from the back surface side to form the back surface p + accumulation layer.

JP, 2009-111118, A JP, 2006-93587, A

  In the case where a separation region for separating charge storage regions formed in a semiconductor layer from each other is formed only by ion implantation through one of two surfaces of the semiconductor layer (hereinafter referred to as an ion implantation surface), The further away from the injection surface, the wider the separation area may be. This is because, in order to implant ions into a region (that is, a deep region) far from the ion implantation surface, high implantation energy is required, thereby expanding the region into which ions are implanted. The phenomenon that the width of the separation region becomes wider as the distance from the ion implantation surface is increased hinders the densification of the charge storage region or pixel.

  The present invention has been made with the above problem recognition in mind, and provides a manufacturing method that is advantageous for increasing the density of charge storage regions or pixels, and a solid-state imaging device having a structure that is advantageous for manufacturing using the manufacturing method. With the goal.

One aspect of the present invention relates to a solid-state imaging device including a semiconductor layer having a first surface and a second surface, wherein the solid-state imaging device is disposed between the first surface and the second surface, A plurality of charge storage region pairs each including a plurality of charge storage regions, a transfer gate disposed on the side of the first surface to transfer charge, and one microlens storing the plurality of charge storages A plurality of microlenses disposed on the side of the second surface so as to be allocated to one charge storage region pair of the region pair, and the plurality of charge storage regions of the one charge storage region pair A first separation portion including the separation region extending from the second surface toward the first surface and the plurality of charge storage region pairs, and the second surface to the first surface And a second separation part extending continuously toward the , The depth of the separation region from the second surface is smaller than the depth of the second separation unit from the second surface.

  According to the present invention, a manufacturing method that is advantageous for increasing the density of charge storage regions or pixels and a solid-state imaging device having a structure that is advantageous for manufacturing using the manufacturing method are provided.

Sectional drawing which shows typically the structure of the solid-state imaging device of 1st, 2nd embodiment. FIG. 2 is a plan view schematically showing the configuration of a solid-state imaging device according to the first and second embodiments. FIG. 7 is a view for explaining the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 7 is a view for explaining the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 7 is a view for explaining the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 7 is a view for explaining the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 7 is a view for explaining the method of manufacturing a solid-state imaging device according to the second embodiment; FIG. 7 is a view for explaining the method of manufacturing a solid-state imaging device according to the second embodiment; FIG. 7 is a view for explaining the method of manufacturing a solid-state imaging device according to the second embodiment; The figure for demonstrating the solid-state imaging device of 3rd Embodiment, and its manufacturing method. The figure for demonstrating 4th Embodiment and its manufacturing method. The figure for demonstrating 5th Embodiment and its manufacturing method.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional view schematically showing a configuration of a solid-state imaging device 100 according to a first embodiment of the present invention. FIG. 2 is a plan view schematically showing the configuration of the solid-state imaging device 100 according to the first embodiment of the present invention. FIG. 1 is a cross-sectional view taken along the line X-X 'of FIG.

  The solid-state imaging device 100 includes a semiconductor layer 101 having a first surface F1 and a second surface F2, a plurality of charge storage regions 103 disposed in the semiconductor layer 101, and a separation portion disposed in the semiconductor layer 101. 120 and 130 are provided. The separation units 120 and 130 are disposed in the semiconductor layer 101 so as to separate the plurality of charge storage regions 103 from each other. The separation units 120 and 130 are impurity semiconductor regions formed by ion implantation, and form potential barriers.

  The solid-state imaging device 100 includes a plurality of micro lenses 171. Here, the plurality of microlenses 171 are arranged such that one microlens 171 is assigned to a charge storage region pair consisting of two charge storage regions 103. The solid-state imaging device 100 is configured to be able to individually read out signals corresponding to the charges stored in the two charge storage regions 103 forming the charge storage region pair. Such a configuration can be used for focus detection by phase difference detection. The solid-state imaging device 100 can also be configured to be able to individually read out signals corresponding to the sum of the charges accumulated in each of the two charge accumulation regions 103 constituting the charge accumulation region pair. A signal corresponding to the sum of the charges accumulated in each of the two charge accumulation regions 103 constituting the charge accumulation region pair corresponds to a signal of one pixel.

  The separation unit 120 is an inter-pair separation unit that is disposed between the charge storage region pair and the other charge storage region pair and forms a potential barrier. The separation unit 130 is an inter-pair separation unit that is disposed between two charge storage regions 103 that form a charge storage region pair, and forms a potential barrier. The potential barrier formed by the intra-pair separation portion 130 is smaller than the potential barrier formed by the inter-pair separation portion 120. Such a configuration allows charges overflowed from one of the two charge storage regions 103 constituting one charge storage region pair (pixel) to move to the other, while the other charges from the charge storage region pair It is advantageous to prevent the transfer of charge to the storage region pair. This contributes to reducing color mixing while expanding the dynamic range.

  As a method of making the potential barrier formed by the pair inner separating portion 130 smaller than the potential barrier formed by the pair inner separating portion 120, the following first to third methods can be mentioned, for example. The first to third methods may be used in combination of two or more thereof.

  In the first method, the intra-pair separation unit 130 is formed of the impurity semiconductor region of the first stage number, the inter-pair separation unit 120 is formed of the impurity semiconductor regions of the second stage number, and the first stage number is smaller than the second stage number. Do.

  In the second method, the impurity concentration of the intra-pair separator 130 is set lower than the impurity concentration of the inter-pair separator 120.

  In the third method, the width of the intra-pair separation portion 130 in the direction along the first surface F1 is smaller than the width of the inter-pair separation portion 120 in the direction along the first surface F1.

  The pair pair separation unit 120 may have a first separation region 121 and a second separation region 122. The first separation region 121 can be formed by implanting ions into the semiconductor layer 101 through the first surface F1. The second separation region 122 can be formed by implanting ions into the semiconductor layer 101 through the second surface F2.

  The in-pair separation unit 130 may have a first separation region 131 and a second separation region 132. The first separation region 131 can be formed by implanting ions into the semiconductor layer 101 through the first surface F1. The second separation region 132 can be formed by implanting ions into the semiconductor layer 101 through the second surface F2. For example, the first separation region 131 and the second separation region 132 are not in contact with each other. The first separation region 131 and the second separation region 132 may not be in contact with each other by forming the pair separation portion 130 with the first number of impurity semiconductor regions smaller than the second number.

  The solid-state imaging device 100 can include a surface pinning layer 105 disposed between the first surface F <b> 1 and the charge storage region 103. The solid-state imaging device 100 can also include a back surface pinning layer 107 disposed to be adjacent to the second surface F2. Here, the separation units 120 and 130, the front surface pinning layer 105, and the back surface pinning layer 107 are formed of a first conductivity type impurity semiconductor region. The semiconductor layer 101 and the charge storage region 103 can be formed of an impurity semiconductor region of a second conductivity type different from the first conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and if the first conductivity type is n-type, the second conductivity type is p-type.

  The solid-state imaging device 100 can include the floating diffusion 106 in the semiconductor layer 101. The floating diffusion 106 can be formed of an impurity semiconductor region of the second conductivity type. The charge stored in the charge storage region 103 can be transferred to the floating diffusion 106 through the channel formed in the semiconductor layer 101 by the transfer gate 141. The solid-state imaging device 100 can further include a reset transistor that resets the potential of the floating diffusion 106, and an amplification transistor that outputs a signal corresponding to the charge transferred to the floating diffusion 106 to the vertical signal line.

  The solid-state imaging device 100 can include the multilayer wiring structure 140 on the side of the first surface F1. The multilayer interconnection structure 140 may include a gate electrode such as the transfer gate 141, an interconnection pattern 143, an insulating film 145, a contact plug (not shown), a via plug (not shown), and the like. The solid-state imaging device 100 can also include, for example, an antireflective film 161, a light shielding film 163, an insulating film 165, and a color filter layer 167 on the side of the second surface F2. The solid-state imaging device in which the multilayer wiring structure 140 is disposed on one side (the first surface side) of the semiconductor layer 101 and the microlens 171 is disposed on the other side (the second surface side) of the semiconductor layer 101 is It can be called back side illumination type. However, the present invention is not limited to the backside illumination type.

  The solid-state imaging device 100 can include the support substrate 151 on the side of the multilayer wiring structure 140. The support substrate 151 supports the multilayer wiring structure 140, the semiconductor layer 101, and the like.

  Hereinafter, a method of manufacturing the solid-state imaging device 100 according to the first embodiment will be described with reference to FIGS. First, in the process shown in FIG. 3A, a semiconductor substrate 101 'such as a silicon substrate is prepared, and wells and element isolation such as STI (Shallow Trench Isolation) are formed in the semiconductor substrate 101'. The separation regions 121 and 131 are formed. Here, the semiconductor substrate 101 ′ later becomes the semiconductor layer 101. The first isolation regions 121 and 131 may be formed by performing at least one (typically, a plurality of) ion implantation steps on the semiconductor substrate 101 'through the first surface F1 of the semiconductor substrate 101'. The first isolation regions 121 and 131 may be formed of the first conductivity type impurity region as described above. When the first conductivity type is p-type, the first isolation regions 121 and 131 are formed by implanting boron into the semiconductor substrate 101 'at 1.5 MeV, 1 MeV, 600 keV, 300 keV, 100 keV, 50 keV, for example. can do. In some embodiments, ions may be implanted only in the inter-pair separator 120 among the inter-pair separator 120 and the in-pair separator 130 in part of ion implantation among the plurality of ion implantation steps.

  In the step shown in FIG. 3B, charge storage regions 103, surface pinning layers 105, floating diffusions 106, gate electrodes such as transfer gates 141, and diffusion regions of transistors are formed in a semiconductor substrate 101 '. The gate electrode such as the transfer gate 141 is formed on the first surface F1 via the gate insulating film. As described above, the charge storage region 103 and the floating diffusion 106 are impurity regions of the second conductivity type, and the surface pinning layer 105 is an impurity region of the first conductivity type. When the first conductivity type is p-type, the surface pinning layer 105 can be formed, for example, by implanting boron into the semiconductor substrate 101 'at 10 keV.

  After the ion implantation process for forming impurity semiconductor regions such as the first isolation regions 121 and 131, a first annealing process for repairing a crystal defect generated by the ion implantation may be performed. The first annealing process may be performed by, for example, FA method (Furnace Annealing) using an electric furnace or RTP method (Rapid Thermal Annealing).

  In the process shown in FIG. 4A, the multilayer wiring structure 140 is formed on the first surface F1 of the semiconductor substrate 101.

  The step shown in FIG. 4B is an optional step, in which the support substrate 151 is coupled to the multilayer wiring structure 140. The surface of the multilayer wiring structure 140 typically has a planarized insulating film exposed. The support substrate 151 is made of a substrate such as a silicon substrate or a glass substrate, for example, and typically has a planarized surface. Bonding of the support substrate 151 to the multilayer wiring structure 140 can be performed, for example, in a vacuum or in an inert gas atmosphere. Before this bonding step, the bonding strength can be enhanced by performing plasma irradiation on the surface of the multilayer wiring structure 140 and the surface of the support substrate 151. Alternatively, the surface of the multilayer wiring structure 140 and the surface of the support substrate 151 may be activated by treatment with a chemical solution before the bonding step.

  Although the above bonding process directly bonds the surface of the multilayer wiring structure 140 to the surface of the support substrate 151, this bonding may be performed using an adhesive. Examples of the adhesive include benzocyclobutene, and when benzocyclobutene is used, bonding can be performed at about 250 ° C.

  In the step shown in FIG. 5A, the semiconductor substrate 101 'is thinned by processing the second surface F2' of the semiconductor substrate 101 'to form the semiconductor layer 101 having the processed second surface F2. . The thinning can be performed by, for example, grinding, polishing, CMP (Chemical Mechanical Polishing) or etching. When the semiconductor layer 101 is a silicon layer, the thickness of the semiconductor layer 101 is preferably in the range of 2 to 10 μm, for example. In this case, the semiconductor layer 101 absorbs 80% or more of light in a wavelength band of 400 to 700 nm which is a wavelength band including visible light and the vicinity thereof.

  In the process illustrated in FIG. 5B, the second separation regions 122 and 132 are formed. The second isolation regions 122 and 132 can be formed by performing at least one (typically, multiple) ion implantation steps on the semiconductor layer 101 through the second surface F2 of the semiconductor substrate 101. The second isolation regions 122 and 132 may be formed of the first conductivity type impurity region, as described above. When the first conductivity type is p-type, the second isolation regions 122 and 132 can be formed by implanting boron into the semiconductor layer 101 at 600 keV, 300 keV, 100 keV, and 50 keV, for example. As a result, the inter-pair separation portion 120 including the first separation region 121 and the second separation region 122 and the in-pair separation portion 130 including the first separation region 131 and the second separation region 132 can be formed. In some embodiments, ions may be implanted only in the inter-pair separator 120 among the inter-pair separator 120 and the in-pair separator 130 in part of ion implantation among the plurality of ion implantation steps.

  Here, the number of ion implantations for forming the second separation region 122 is preferably smaller than the number of ion implantations for forming the first separation region 121. Alternatively, the dimension in the depth direction of the second separation region 122 is preferably smaller than the dimension in the depth direction of the first separation region 121. Further, the number of ion implantations for forming the second separation region 132 is preferably smaller than the number of ion implantations for forming the first separation region 131. Alternatively, the dimension in the depth direction of the second separation region 132 is preferably smaller than the dimension in the depth direction of the first separation region 131. This is because heating in the second annealing step for recovering crystal defects formed by ion implantation for forming the second isolation regions 122 and 132 and the back surface pinning layer 107 described below is performed in the vicinity of the second surface F2. This is because selective implementation is preferred.

  In the step shown in FIG. 6A, the back surface pinning layer 107 is formed by implanting ions in the vicinity of the second surface F2. When the first conductivity type is p-type, the back surface pinning layer 107 can be formed by implanting boron into the semiconductor layer 101 through the second surface F2 at 10 keV, for example. Thereafter, a second annealing step is performed to recover the crystal defects formed by ion implantation for forming the second isolation regions 122 and 132 and the back surface pinning layer 107. For the second annealing step, a method different from the first annealing step may be used. Here, since the multilayer wiring structure 140 is already formed on the first surface F1 side, heating in the second annealing step is performed with respect to the vicinity of the second surface F2 so that the wiring pattern 143 does not reach the melting point. Selectively.

  The second annealing step may be performed, for example, by a method of irradiating the second surface F2 with light. More specifically, the second annealing step can be performed by, for example, a laser annealing method or a flash lamp annealing method. In one example to which the laser annealing method is applied, laser light is irradiated to the second surface F2 for about 100 nsec using a 308 nm (XeCl) excimer laser.

  The second annealing step may be performed after the formation of the antireflective film 161 described later and before the formation of the light shielding film 163. In this case, ion implantation for forming the back surface pinning layer 107 may also be performed after the formation of the anti-reflection film 161 (and before the second annealing step). When ion implantation for forming the back surface pinning layer 107 is performed after the formation of the antireflective film 161, the antireflective film 161 can function as a buffer layer that prevents channeling at the time of ion implantation.

  In the step shown in FIG. 6B, the anti-reflection film 161 is formed on the second surface F2 of the semiconductor layer 101. The antireflective film 161 can be made of, for example, a silicon oxide film and a silicon nitride film. For example, the antireflective film 161 is a lamination of a 5 nm thick silicon oxide film and a 50 nm thick silicon nitride film, or a 5 nm thick silicon oxide film, a 50 nm thick silicon nitride film, and a 50 nm thick silicon oxide film Can be composed of a stack of The antireflection film 161 is not limited to these examples, and any structure having an antireflection function may be adopted.

  In the step shown in FIG. 6B, the light shielding film 163 is formed on the antireflective film 161 again. The light shielding film 163 may be formed of, for example, aluminum or tungsten. The light shielding film 163 is an optional component.

  Then, it demonstrates, referring FIG. In the process shown in FIG. 1, the insulating film (planarizing film) 165 is formed on the light shielding film 163 and the antireflective film 161, the color filter layer 167 is formed on the insulating film 165, and the color filter layer 167 is formed. The micro lens 171 is formed.

  Hereinafter, the manufacturing method of the second embodiment of the present invention will be described with reference to FIGS. 7-9. The second embodiment is different from the first embodiment in the method of obtaining the thinned semiconductor layer 101. Matters not mentioned in the second embodiment can follow the first embodiment as long as no contradiction arises.

  First, in a step shown in FIG. 7A, an SOI (Silicon On Insulator) substrate is prepared. The SOI substrate has the buried insulating layer 201 on the handle substrate 203 and the semiconductor layer 101 on the buried insulating layer 201. Further, in the step shown in FIG. 7A, the back surface pinning layer 107 is formed in the semiconductor layer 101 by implanting ions into the semiconductor layer 101 through the first surface F1 of the semiconductor layer 101. The back surface pinning layer 107 can be formed to be in contact with the buried insulating layer 201, for example. Note that the back surface pinning layer 107 may be formed in the semiconductor layer 101 when the SOI substrate is manufactured. In the step shown in FIG. 7A, a well and an element isolation such as STI (Shallow Trench Isolation) are formed in the semiconductor layer 101, and further, first isolation regions 121 and 131 are formed.

  In the process shown in FIG. 7B, the charge storage region 103, the surface pinning layer 105, the floating diffusion 106, the gate electrode such as the transfer gate 141, the diffusion region of the transistor, and the like are formed in the semiconductor layer 101.

  In the process shown in FIG. 8A, the multilayer wiring structure 140 is formed on the first surface F1 of the semiconductor substrate 101. The step shown in FIG. 8B is an optional step, and in this step, the support substrate 151 is bonded to the multilayer wiring structure 140.

  In the process shown in FIG. 9, the handle substrate 203 and the buried insulating layer 201 are removed (that is, the SOI substrate is thinned so that the semiconductor layer 101 remains). This process corresponds to the thinning process shown in FIG. 5A in the first embodiment. The removal of the handle substrate 203 and the buried insulating layer 201 can be performed, for example, by etching the handle substrate 203 using the buried insulating layer 201 as an etching stop layer and then etching the buried insulating layer 201. Here, if the embedded insulating layer 201 has a structure that can be used as the antireflective film 161, the process of removing the embedded insulating layer 201 and the process of forming the antireflective film 161 can be omitted.

  The subsequent steps are the same as the steps shown in FIGS. 5 (b), 6 (a), 6 (b) and 1 in the first embodiment.

  Hereinafter, a third embodiment of the present invention will be described with reference to FIG. Matters not mentioned in the third embodiment can follow the first or second embodiment as long as no contradiction arises. In the first and second embodiments, one microlens 171 is assigned to a charge storage region pair consisting of two charge storage regions 103. In the third embodiment, one microlens 171 is assigned to one charge storage region 103. A separation unit 120 is disposed between the charge storage region 103 and the charge storage region 103 to form a potential barrier. The separation unit 120 may have a first separation region 121 and a second separation region 122. The first separation region 121 can be formed by implanting ions into the semiconductor layer 101 through the first surface F1. The second separation region 122 can be formed by implanting ions into the semiconductor layer 101 through the second surface F2.

  The number of ion implantations for forming the second separation region 122 is preferably smaller than the number of ion implantations for forming the first separation region 121. Alternatively, the dimension in the depth direction of the second separation region 122 is preferably smaller than the dimension in the depth direction of the first separation region 121.

  In the solid-state imaging device and the method of manufacturing the same according to the third embodiment, the separation unit 120 is disposed instead of the separation unit 130 in the first embodiment, and one microlens 171 is allocated to one charge storage region 103. Except in the first embodiment.

  Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. Matters not mentioned in the fourth embodiment can follow the first or second embodiment as long as no contradiction arises.

  In the fourth embodiment, the plurality of microlenses 171 are arranged such that one microlens 171 is assigned to the charge storage region pair consisting of two charge storage regions 103. In the fourth embodiment, the first separation unit 120 includes a first separation region 121 and a second separation region 122 mutually connected by the connection plane IF. The first separation area 121 is disposed between the first surface F1 and the connection surface IF so as to be in contact with the connection surface IF. The second separation region 122 is disposed between the second surface F2 and the connection surface IF so as to be in contact with the connection surface IF. Here, the width on the connection surface IF side of the first separation region 121 is larger than the width of the portion on the first surface F1 side of the first separation region 121 and / or the connection surface of the second separation region 122 The width at the side of IF is larger than the width of the portion at the side of the second surface F 2 of the second separation region 122. As a result, the possibility of the first separation region 121 and the second separation region 122 being separated due to an alignment error in the lithography process can be reduced.

  The structure of the first isolation region 121 as described above can be realized by performing ion implantation multiple times into the semiconductor layer 101 through the first surface F1. That is, when ions are implanted at a position (deep position) far from the first surface F1, high ion implantation energy is required, whereby the region into which the ions are implanted is in the lateral direction (parallel to the first surface F1 Spread in the direction). For example, multiple ion implantations of different energies may be performed using a mask having the same opening. Similarly, the structure of the second isolation region 122 as described above can be realized by performing ion implantation a plurality of times into the semiconductor layer 101 through the second surface F2.

  A fifth embodiment of the present invention is shown in FIG. The fifth embodiment is different from the fourth embodiment in that a separating unit 120 is disposed instead of the separating unit 130 in the fourth embodiment, and one microlens 171 is allocated to one charge storage region 103. It is similar.

  Hereinafter, as an application example of the solid-state imaging device according to each of the above-described embodiments, a camera in which the solid-state imaging device is incorporated will be exemplarily described. The concept of a camera includes not only an apparatus whose main purpose is imaging, but also an apparatus (for example, a personal computer or a portable terminal) additionally equipped with an imaging function. The camera includes the solid-state imaging device according to the present invention exemplified as the above embodiment, and a processing unit that processes a signal output from the solid-state imaging device. The processing unit may include, for example, an A / D converter, and a processor that processes digital data output from the A / D converter.

F1: first surface, F2: second surface, 101: semiconductor layer, 121: first separation region, 122: second separation region, 131: first separation region, 132: second separation region, 103: charge storage region

Claims (17)

A solid-state imaging device comprising a semiconductor layer having a first surface and a second surface, the solid-state imaging device comprising:
A plurality of charge storage region pairs each disposed between the first surface and the second surface and including a plurality of charge storage regions for storing charge;
A transfer gate disposed on the side of the first surface to transfer charges;
A plurality of microlenses arranged on the side of the second surface such that one microlens is assigned to one charge storage region pair of the plurality of charge storage region pairs;
A first separation unit disposed between the plurality of charge storage regions of the one charge storage region pair, and including a separation region extending from the second surface toward the first surface;
And a second separation portion disposed between the plurality of charge storage region pairs and continuously extending from the second surface to the first surface,
The depth of the separation region from the second surface is smaller than the depth of the second separation portion from the second surface,
A solid-state imaging device characterized by A solid-state imaging device comprising a semiconductor layer having a first surface and a second surface, the solid-state imaging device comprising:
A plurality of charge storage region pairs each disposed between the first surface and the second surface and including a plurality of charge storage regions for storing charge;
A transfer gate disposed on the side of the first surface to transfer charges;
A plurality of microlenses arranged on the side of the second surface such that one microlens is assigned to one charge storage region pair of the plurality of charge storage region pairs;
A first separation unit disposed between the plurality of charge storage regions of the one charge storage region pair, and including a separation region extending from the first surface toward the second surface;
And a second separation portion disposed between the plurality of charge storage region pairs and continuously extending from the first surface to the second surface,
The depth of the separation region from the first surface is smaller than the depth of the second separation portion from the first surface,
A solid-state imaging device characterized by The impurity concentration of the first separation unit is smaller than the impurity concentration of the second separation unit,
The solid-state imaging device according to claim 1 or 2, characterized in that The width of the first separation part is smaller than the width of the second separation part,
The solid-state imaging device according to claim 1 or 2, characterized in that The plurality of charge storage regions of the one charge storage region pair include a first charge storage region and a second charge storage region, and the transfer gate transfers the charge of the first charge storage region. A gate, and a second transfer gate transferring the charge of the second charge storage region,
The solid-state imaging device according to any one of claims 1 to 4, characterized in that: Each of the first isolation portion and the second isolation portion includes a semiconductor region of a first conductivity type, and the plurality of charge storage regions of the one charge storage region pair includes a semiconductor region of a second conductivity type. ,
The solid-state imaging device according to any one of claims 1 to 5, characterized in that: The transfer gate transfers charge to the semiconductor region of the second conductivity type.
The solid-state imaging device according to claim 6, The semiconductor device further includes a first semiconductor region of a first conductivity type disposed between the second surface and the plurality of charge storage regions of the one charge storage region pair.
The solid-state imaging device according to claim 6 or 7, characterized in that And a second semiconductor region of a second conductivity type disposed between the first semiconductor region and the plurality of charge storage regions of the one charge storage region pair.
The solid-state imaging device according to claim 8, The semiconductor device further includes a third semiconductor region of the first conductivity type disposed between the first surface and the plurality of charge storage regions of the one charge storage region pair.
The solid-state imaging device according to claim 9, characterized in that: Further comprising a film disposed on the semiconductor layer and in contact with the first semiconductor region;
The solid-state imaging device according to any one of claims 8 to 10, wherein A first film disposed between the plurality of microlenses and the semiconductor layer, a second film disposed between the plurality of microlenses and the first film, the first film, and the first film. And a light shielding film disposed between the two films.
The solid-state imaging device according to any one of claims 1 to 11, characterized in that: The second separation portion may be a first separation region disposed between the first surface and the second surface, and a second separation region disposed between the first separation region and the first surface. And including
The solid-state imaging device according to claim 1, The width of the first separation area is such that the side of the first surface is larger than the side of the second surface, and / or
The width of the second separation area is such that the side of the second surface is larger than the side of the first surface,
The solid-state imaging device according to claim 13, characterized in that: The separation region is disposed between the first surface and the second surface, and the first separation portion includes a third separation region disposed between the separation region and the first surface.
The solid-state imaging device according to claim 13 or 14, characterized in that The depth of the third separation region from the first surface is greater than the depth of the separation region from the second surface,
The solid-state imaging device according to claim 15, characterized in that: A solid-state imaging device according to any one of claims 1 to 16,
A processing unit that processes a signal from the solid-state imaging device;
Focus detection by phase difference detection method using the signal
A camera characterized by