JP2008270298A - Solid-state image sensor and imaging apparatus employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high-quality image by reducing a difference between an imaging signal obtained from an imaging pixel near a focal point detection pixel, and an imaging signal obtained from a region other than the vicinity of a focal point detection pixel. <P>SOLUTION: A P-type well layer 52 is arranged on an N-type silicon substrate 51. An isolation region 76 exists between a focal point detection pixel 20V and an imaging pixel 20R. A crosstalk reduction layer 77 is arranged at a part in the P-type well layer 52 opposing the charge cumulation layers 74 of the embedded photodiodes 42 and 43 of an AF pixel 20V. The crosstalk reduction layer 77 has the same conductivity type as that of the P-type well layer 52 and a higher concentration than that of the P-type well layer 52. The crosstalk reduction layer 77 reduces crosstalk, i.e., the mixing of charges generated from the AF pixel 20V into the imaging pixel 20R. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  In recent years, imaging devices such as video cameras and electronic cameras have been widely spread. These cameras use a solid-state imaging device such as a CCD type or an amplification type. In these solid-state imaging devices, a plurality of pixels having a photoelectric conversion unit that generates a signal charge according to the amount of incident light are arranged in a matrix.

  In the amplification type solid-state imaging device, signal charges generated and stored in the photoelectric conversion unit of the pixel are guided to an amplification unit provided in the pixel, and a signal amplified by the amplification unit is output from the pixel. As the amplification type solid-state imaging device, for example, a solid-state imaging device using a junction field effect transistor in the amplification unit (Patent Documents 1 and 2), or a CMOS type solid-state imaging device using a MOS transistor in the amplification unit (Patent Document 3) has been proposed.

  By the way, in order to realize automatic focus adjustment in an electronic camera, it is necessary to detect the focus adjustment state of the imaging lens. Conventionally, a focus detection element is provided separately from a solid-state image sensor used for imaging. However, in that case, the cost increases by the focus detection element and the focus detection optical system that guides light to the focus detection element, and the size of the device increases accordingly.

  Therefore, in recent years, a solid-state imaging device has been proposed which is configured to adopt a so-called pupil division phase difference method as a focus detection method and also to be used as a focus detection device (for example, Patent Document 4).

  In the solid-state imaging device disclosed in Patent Document 4, a focus detection signal (“AF signal”) indicating a focus adjustment state is provided separately from the imaging pixels that output an imaging signal for forming an image signal indicating a subject image. A plurality of focus detection pixels (also referred to as “AF pixels”) are generated. In this solid-state imaging device, the AF pixel has a photoelectric conversion unit divided into two. On such a photoelectric conversion unit, microlenses are provided on a one-to-one basis with respect to pixels. The two-divided photoelectric conversion unit is arranged at a position where the microlens is in a substantially imaging relationship (that is, substantially conjugate) with the exit pupil of the imaging lens. Therefore, since the distance between the exit pupil of the imaging lens and the microlens is sufficiently long with respect to the size of the microlens, the two-divided photoelectric conversion unit is disposed at a substantially focal position of the microlens. It will be. From the relationship described above, in each pixel, one part of the photoelectric conversion unit divided into two parts is a part of the exit pupil of the imaging lens and emits a light beam from an area decentered in a predetermined direction from the center of the exit pupil. The light is selectively received and photoelectrically converted. In each AF pixel, the other part of the photoelectric conversion unit divided into two parts selectively receives a light beam from a region that is part of the exit pupil of the imaging lens and decentered in the opposite direction from the center of the exit pupil. And photoelectric conversion.

  In general, such AF pixels are not arranged uniformly in the effective pixel region of the solid-state imaging device, but are partially arranged vertically, horizontally, or partially in the center. The reason for this arrangement is to generate AF signals efficiently and increase the number of imaging pixels as much as possible.

In the solid-state imaging device disclosed in Patent Document 4, a color filter is provided in the imaging pixel, but no color filter is provided in the AF pixel (paragraphs [0063] and [0064 of Patent Document 4]. ]).
JP-A-11-177076 JP 2004-335882 A JP 2004-111590 A JP 2000-292686 A

  However, when an image is actually picked up using a solid-state imaging device as disclosed in Patent Document 4, a region where the luminance increases compared to the other is generated even though a subject having a uniform luminance is picked up. It was. Further analysis shows that the region is a region near the region where the AF pixels are arranged.

  That is, even if the same light is incident on the imaging pixels near the AF pixels and the imaging pixels in the region other than the AF pixels, there is a difference in the magnitude of the imaging signal obtained between them. It was. As a result, a high-brightness region is clearly formed in a line along the AF pixel array, resulting in poor quality images.

  The present invention has been made in view of such problems, and an imaging signal obtained from an imaging pixel near the focus detection pixel and an imaging obtained from an imaging pixel in a region other than the vicinity of the focus detection pixel. It is an object of the present invention to provide a solid-state imaging device capable of reducing a difference between the signal and a signal for use, and thus obtaining a high-quality image, and an imaging apparatus using the same.

  As a result of intensive studies, the present inventors have found the cause of the above problems. In the conventional solid-state imaging device described above, as described above, the color filter is removed from the AF pixel. As a result, in the AF pixel, light from a short wavelength, which is a blue component, to a long wavelength light, which is a red component, is incident, so that the amount of light incident on the AF pixel is increased, and thus the accuracy of focus detection is improved. There is an excellent effect.

  However, in the AF pixel, a light component having a wavelength longer than red is incident. Such light enters the semiconductor deeper than the incident surface and is photoelectrically converted. The electric charges generated in the deep position of the semiconductor substrate move in all directions due to drift. If the drifted charge is trapped in the charge storage layer disposed in the AF pixel, no particular problem occurs. However, as the position where charge is generated is deeper, the component that is not captured by the AF pixel and is captured by the charge storage layer of the adjacent imaging pixel increases. The above problem was caused by this phenomenon.

  Although it is so-called crosstalk, it is different from generally called crosstalk. That is, this phenomenon is caused by charges mixed from the AF pixel to the imaging pixel in the vicinity thereof. The AF pixel is arranged in a specific area of the effective pixel area. Therefore, a clear and high-bright area is observed along the area where the AF pixels are arranged in the effective pixel area.

  The present invention has been made as a result of investigating the cause of such problems. That is, in order to solve the above-described problem, the solid-state imaging device according to the first aspect of the present invention is a solid-state imaging device that photoelectrically converts a subject image formed by an optical system, and is arranged in a two-dimensional manner. A plurality of pixels each having a photoelectric conversion unit that generates and accumulates charges according to incident light; and a separation region between the plurality of pixels, the plurality of pixels forming an image signal indicating the subject image A plurality of image pickup pixels for outputting an image pickup signal for output, and a plurality of focus detection pixels for outputting a focus detection signal for detecting a focus adjustment state of the optical system. And / or in the separation region between the focus detection pixel and the imaging pixel adjacent thereto in the separation region, the charge generated in the focus detection pixel is adjacent to the focus detection pixel. Mixed in the matching imaging pixels That in which crosstalk reduction unit for reducing crosstalk is provided.

  A solid-state imaging device according to a second aspect of the present invention, in the first aspect, includes a first conductive type first semiconductor layer and a second conductive type second provided on the first semiconductor layer. The photoelectric conversion unit of the plurality of pixels includes the first conductivity type charge storage layer provided in the second semiconductor layer, and the crosstalk reduction unit includes the first A third semiconductor layer disposed in the two semiconductor layers so as to face the charge storage layer of the focus detection pixel, wherein the second conductivity type is higher in concentration than the second semiconductor layer. A third semiconductor layer is included.

  A solid-state imaging device according to a third aspect of the present invention is the first aspect, wherein the first conductivity type or the second conductivity type first semiconductor layer and the first semiconductor layer provided on the first semiconductor layer are provided. And the photoelectric conversion unit of the plurality of pixels includes the first conductivity type charge storage layer provided in the second semiconductor layer, and the crosstalk. The reduction unit is the second conductivity type separation diffusion layer disposed in a separation region between the focus detection pixel and the imaging pixel adjacent to the focus detection pixel in the separation region. Of these, an isolation diffusion layer having a portion deeper than the isolation diffusion layer of the second conductivity type disposed in an isolation region between the imaging pixels is included.

  According to a fourth aspect of the present invention, there is provided a solid-state imaging device according to the first aspect, wherein the first conductivity type or second conductivity type first semiconductor layer and the first semiconductor layer provided on the first semiconductor layer are provided. And the photoelectric conversion unit of the plurality of pixels includes the first conductivity type charge storage layer provided in the second semiconductor layer, and the crosstalk. The reduction unit is a fourth semiconductor layer disposed in the second semiconductor layer so as to extend over the focus detection pixel and the imaging pixel adjacent thereto, and is more than the second semiconductor layer. A portion including a high-concentration fourth semiconductor layer of the second conductivity type and disposed in a separation region between the focus detection pixel and the imaging pixel adjacent thereto in the fourth semiconductor layer; Is a portion disposed in the focus detection pixel in the fourth semiconductor layer. In which is arranged at a position shallower than.

  The solid-state imaging device according to a fifth aspect of the present invention is the solid-state imaging device according to the fourth aspect, wherein the portion of the fourth semiconductor layer arranged in the focus detection pixel is the imaging pixel in the fourth semiconductor layer. It is arrange | positioned in the position shallower than the part arrange | positioned.

  A solid-state imaging device according to a sixth aspect of the present invention is the first aspect, wherein the first conductive type first semiconductor layer and the second conductive type second semiconductor layer provided on the first semiconductor layer are provided. The photoelectric conversion unit of the plurality of pixels includes the first conductivity type charge storage layer provided in the second semiconductor layer, and the first semiconductor layer includes the first semiconductor layer, The focus detection pixel has a protrusion protruding to the charge storage layer side of the photoelectric conversion unit of the focus detection pixel, and the crosstalk reduction unit includes the protrusion.

  In the solid-state imaging device according to the seventh aspect of the present invention, in any one of the first to sixth aspects, the imaging pixel is provided with a color filter, and the focus detection pixel is provided with a color filter. It is not.

  According to an eighth aspect of the present invention, there is provided an imaging apparatus that uses the solid-state imaging device according to any one of the first to seventh aspects and the focus detection signal from at least some of the plurality of focus detection pixels. A detection processing unit that outputs a detection signal indicating a focus adjustment state of the optical system, and an adjustment unit that performs focus adjustment of the optical system based on the detection signal from the detection processing unit. It is.

  Needless to say, the above-described features of the first to eighth aspects may be arbitrarily combined as long as they do not contradict their purpose.

  According to the present invention, it is possible to reduce a difference between an imaging signal obtained from an imaging pixel near the focus detection pixel and an imaging signal obtained from an imaging pixel in a region other than the vicinity of the focus detection pixel. Therefore, it is possible to provide a solid-state imaging device capable of obtaining a high-quality image and an imaging apparatus using the solid-state imaging device.

  Hereinafter, a solid-state imaging device and an imaging device using the same according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic block diagram showing an electronic camera 1 as an imaging apparatus according to the first embodiment of the present invention. A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 2a for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 3 is arranged.

  The solid-state imaging device 3 is driven by a command from the imaging control unit 4 and outputs a signal. The signal output from the solid-state imaging device 3 is either an image signal or a focus detection signal. In any case, the signal is processed through the signal processing unit 5 and the A / D conversion unit 6 and then temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 2a, an imaging control unit 4, a microprocessor 9, a focus calculation unit (detection processing unit) 10, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. The microprocessor 9 is connected to an operation unit 9a such as a release button. A recording medium 11a is detachably attached to the recording unit 11 described above. The operation of the electronic camera 1 will be described later with reference to FIG.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 3 in FIG. The solid-state imaging device 3 includes a plurality of pixels 20 arranged in a matrix and a peripheral circuit for outputting a signal from the pixels 20. In the figure, the number of pixels indicates 16 pixels of 4 rows horizontally and 4 rows vertically. However, it is not limited to this. In this embodiment, there are five types of pixels 20R, 20G, 20B, 20V, and 20H, which will be described later, as pixels, but in FIG. Yes. These pixels 20 output either an imaging signal or a focus detection signal in accordance with a peripheral circuit drive signal. Further, the exposure time and timing of all the pixels 20 can be made the same by simultaneously resetting the photoelectric conversion unit.

  The peripheral circuit includes a vertical scanning circuit 21, a horizontal scanning circuit 22, driving signal lines 23 and 24 connected thereto, a vertical signal line 25 for receiving a signal from a pixel, and a constant current source 26 connected to the vertical signal line 25. And a correlated double sampling circuit (CDS) 27, a horizontal signal line 28 for receiving a signal output from the correlated double sampling circuit 27, an output amplifier 29, and the like.

  The vertical scanning circuit 21 and the horizontal scanning circuit 22 output drive signals based on a command from the imaging control unit 4 of the electronic camera 1. Each pixel 20 is driven by receiving a drive signal output from the vertical scanning circuit 21 from a predetermined drive signal line 23, and outputs an imaging signal or a focus detection signal to the vertical signal line 25. There are a plurality of drive signals output from the vertical scanning circuit 21, and accordingly, a plurality of drive wirings 23. These will be described later.

  The signal output from the pixel 20 is subjected to predetermined noise removal by the correlated double sampling circuit 27. Then, a signal is output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22.

  FIG. 3 is a schematic plan view schematically showing the solid-state imaging device 3 (particularly, its imaging region 31) in FIG. In the present embodiment, as shown in FIG. 3, the imaging region 31 of the solid-state imaging device 3 includes two focus detection regions 32 and 33 having a cross shape disposed in the center and two disposed on both sides. Focus detection areas 34 and 35 and two focus detection areas 36 and 37 arranged above and below are provided. As shown in FIG. 3, an X axis, a Y axis, and a Z axis that are orthogonal to each other are defined. The direction of the arrow in the X-axis direction is called the + X direction or + X side, and the opposite direction is called the -X direction or -X side, and the same applies to the Y-axis direction. A plane parallel to the XY plane coincides with the imaging surface (light receiving surface) of the solid-state imaging device 3. The arrangement in the X-axis direction is a row, and the arrangement in the Y-axis direction is a column. Incident light is incident from the front side of the drawing in FIG. These points are the same for the drawings described later. In the present specification, the X-axis direction may be referred to as the left-right direction, the + X side as the right side, the -X side as the left side, the Y-axis direction as the up-down direction, the + Y side as the upper side, and the -Y side as the lower side.

  FIG. 4 is a schematic enlarged view in which the vicinity of the focus detection region 35 in FIG. 3 is enlarged, and schematically shows the pixel arrangement. FIG. 5 is a schematic enlarged view in which the vicinity of the focus detection area 36 in FIG. 3 is enlarged, and schematically shows the pixel arrangement. As described above, the solid-state imaging device 3 has the five types of pixels 20R, 20G, 20B, 20V, and 20H as the pixels 20. 4 and 5, the pixels 20R, 20G, 20B, 20V, and 20H are denoted by reference signs “R”, “G”, “B”, “V”, and “H”, respectively.

  The pixels 20 </ b> R, 20 </ b> G, and 20 </ b> B are imaging pixels that output imaging signals for forming an image signal indicating a subject image formed by the photographing lens 2. In the present embodiment, each of the pixels 20R, 20G, and 20B is provided with a corresponding color filter (not shown), so that the pixel 20R has a red imaging signal, the pixel 20G has a green imaging signal, The pixels 20B are configured to output blue imaging signals. On the other hand, the pixels 20V and 20H are focus detection pixels (hereinafter referred to as “AF pixels”) that output a focus detection signal for detecting the focus adjustment state of the photographic lens 2, and are connected to the pixels 20V and 20H. Is not provided with a color filter. In order to increase the incident light quantity with respect to the AF pixels 20V and 20H and increase the focus detection accuracy, it is preferable that the pixels 20V and 20H are not provided with a color filter, but the present invention is not necessarily limited thereto.

  In the present embodiment, as shown in FIGS. 4 and 5, the imaging pixels 20R, 20G, and 20B are basically arranged according to the Bayer array, and every other pixel in the focus detection area 35 extending in the Y-axis direction. AF pixels 20V are arranged, and AF pixels 20H are arranged every other pixel in the focus detection region 36 extending in the X-axis direction. The focus detection areas 33 and 34 are the same as the focus detection area 35, and the focus detection areas 32 and 37 are the same as the focus detection area 36. However, the arrangement is not limited to such an arrangement. For example, all the pixels in the focus detection areas 33 to 35 are AF pixels 20V, and all the pixels in the focus detection areas 32, 36, and 37 are AF pixels 20H. Also good. Further, in the present invention, it may be configured for black and white, and in that case, it is not necessary to provide a color filter for the imaging pixels. Further, even when configured for color, it is not limited to the Bayer arrangement as described above.

  FIG. 6 is a circuit diagram showing the imaging pixels 20R, 20G, and 20B of the solid-state imaging device 3 in FIG. These pixels have the same circuit configuration. Each of the imaging pixels 20R, 20G, and 20B includes an embedded photodiode 41 as a photoelectric conversion unit that generates and accumulates charges according to incident light, a floating diffusion unit 44 as a predetermined portion, and floating diffusion from the embedded photodiode 41. A transfer transistor 45 for transferring charge to the unit 44, a pixel amplifier 48 as an amplifying unit for outputting a signal corresponding to the amount of charge in the floating diffusion unit 44, and a reset transistor as a reset unit for discharging the charge in the floating diffusion unit 44 49 and a selection transistor 50 as a selection switch for outputting a signal from the pixel amplifier 48 from the pixel. In FIG. 6, VDD is a power supply, and 235 is a power supply wiring for connecting to the power supply VDD.

  FIG. 7 is a circuit diagram showing the AF pixels 20V and 20H of the solid-state imaging device 3 in FIG. These pixels have the same circuit configuration. 7, elements that are the same as or correspond to the elements in FIG. 6 are given the same reference numerals, and redundant descriptions thereof are omitted. The AF pixels 20V and 20H are different from the imaging pixels 20R, 20G, and 20B in terms of circuit configuration in that the two pixels are divided into two instead of one embedded photodiode 41 as one photoelectric conversion unit. Only in that it has two embedded photodiodes 42 and 43 as one photoelectric conversion section, and accordingly, in place of one transfer transistor 45, it has two transfer transistors 46 and 47 that can operate independently of each other. It is. The transfer transistor 46 transfers charge from the embedded photodiode 42 to the floating diffusion 44, and the transfer transistor 47 transfers charge from the embedded photodiode 43 to the floating diffusion 44.

  In this embodiment, the transfer transistors 45 to 47, the pixel amplifier 48, the reset transistor 49, and the selection transistor 50 are all configured by NMOS transistors.

  The gate electrodes of the transfer transistors 45 of the imaging pixels 20R, 20G, and 20B and one of the transfer transistors 46 of the AF pixels 20V and 20H are connected in common to each pixel row, and are connected to the drive wiring 23 from the vertical scanning circuit 21. The drive signal φTGA is supplied through the wiring 231. The gate electrodes of the other transfer transistors 47 of the AF pixels 20V and 20H are connected in common to each pixel row, and the drive signal φTGB is supplied from the vertical scanning circuit 21 via the wiring 232 of the drive wiring 23. .

  The gate electrodes of the selection transistors 50 of the pixels 20R, 20G, 20B, 20V, and 20H are connected in common to each pixel row, and the drive signal φS is supplied from the vertical scanning circuit 21 via the wiring 233 of the drive wiring 23. Is done. The gate electrodes of the reset transistors 49 of the pixels 20R, 20G, 20B, 20V, and 20H are commonly connected to each pixel row, and the drive signal φR is supplied from the vertical scanning circuit 21 via the wiring 234 of the drive wiring 23. Is done.

  6 and 7, one terminal of the embedded photodiodes 41, 42, and 43 and one terminal of the floating diffusion portion 44 are described as ground for convenience. However, in the present embodiment, the potential of the P-type well layer 52 is actually as understood from FIG. 9 described later.

  FIG. 8 is a schematic plan view schematically showing 2 × 2 pixels 20R, 20G, 20B, and 20V in the vicinity of the focus detection region 35 of the solid-state imaging device 3 according to the present embodiment. In FIG. 8, each wiring is shown in a simplified manner. Although the AF pixel 20H does not appear in FIG. 8, the structure thereof is basically the same as that of the AF pixel 20V, so the AF pixel 20H will also be described.

  Reference numerals 44a, 44b, 68, 69 and 70 are N-type impurity diffusion regions which are part of each transistor, and reference numerals 64, 65 and 66 are gates (electrodes) of the respective transistors made of polysilicon. Reference numeral 68 denotes a power supply diffusion unit to which the power supply voltage VDD is applied. These points are the same for the imaging pixels 20R, 20G, and 20B and the AF pixels 20V and 20H.

  Reference numeral 61 denotes a gate (electrode) of the transfer transistor 45 made of polysilicon with respect to the imaging pixels 20R, 20G, and 20B. On the other hand, reference numerals 62 and 63 denote gates (electrodes) of transfer transistors 46 and 47 made of polysilicon for the AF pixels 20V and 20H.

  The transfer transistors 45 of the imaging pixels 20R, 20G, and 20B are MOS transistors that have the charge storage layer 74 (see FIG. 9) of the embedded photodiode 41 as a drain and the N-type diffusion region 44a of the floating diffusion portion 44 as a source. The transfer transistor 45 is driven by a drive signal φTGA applied to its gate 61.

  The transfer transistors 46 of the imaging pixels 20V and 20H are MOS transistors using the charge storage layer 74 (see FIG. 9) of the embedded photodiode 42 as a drain and the N-type diffusion region 44a of the floating diffusion portion 44 as a source. The transfer transistor 46 is driven by a drive signal φTGA applied to its gate 62. The transfer transistor 47 of the imaging pixel 20V is a MOS transistor having the charge storage layer 74 (see FIG. 9) of the embedded photodiode 43 as a drain and the N-type diffusion region 44a of the floating diffusion portion 44 as a source. The transfer transistor 47 is driven by a drive signal φTGB applied to its gate 63.

  As shown in FIG. 8, in the floating diffusion portion 44, two N-type diffusion regions 44a and 44b formed in the P-type well layer 52 (see FIG. 9) separately from each other are electrically connected by a wiring 67. Thus, it is substantially configured as one floating diffusion portion. The floating diffusion portion 44 is electrically connected to the gate 65 of the pixel amplifier 48 by a wiring 67. These points are the same for the imaging pixels 20R, 20G, and 20B and the AF pixels 20V and 20H.

  The pixel amplifier 48 is a MOS transistor having a power source diffusion portion 68 as a drain, a diffusion region 69 as a source, and a gate electrode 65 as a gate. The selection transistor 50 is a MOS transistor having the diffusion region 69 as a drain, the diffusion region 70 as a source, and the gate electrode 66 as a gate. The diffusion region 70 is connected to the vertical signal line 25 in common for each column. The reset transistor 49 is a MOS transistor having the power source diffusion portion 38 as a drain, the diffusion region 44b of the floating diffusion portion 44 as a source, and the gate electrode 64 as a gate. These points are the same for the imaging pixels 20R, 20G, and 20B and the AF pixels 20V and 20H.

  FIG. 9 is a schematic cross-sectional view along the line A-A ′ in FIG. 8. In FIG. 9, the configuration above the silicon oxide film is omitted. Actually, a wiring electrode, a protective film, a color filter, a microlens, and the like are disposed above the silicon oxide film. However, although color filters of corresponding colors are arranged for the imaging pixels 20R, 20G, and 20B, no color filters are arranged for the AF pixels 20V and 20H. Although not shown in the drawings, in the present embodiment, the microlenses are arranged one-to-one with respect to the imaging pixels 20R, 20G, and 20B and the AF pixels 20V and 20H.

In the present embodiment, a P-type well layer 52 as a second semiconductor layer is disposed on an N-type silicon substrate 51 as a first semiconductor layer. The impurity concentration of the N-type silicon substrate 51 is 1E15 / cm ³ (where 1E15 is a notation indicating 1 × 10 ¹⁵ , and the same applies hereinafter), and the impurity concentration of the P-type well layer 52 (hereinafter referred to as Simply described as concentration) is 1E16 / cm ³ . However, the concentration is not limited to these, and for example, the concentration of the P-type well layer 52 may be in the range of 5E15 / cm ³ to 5E16 / cm ³ .

  The embedded photodiode 41 that is the photoelectric conversion unit of the imaging pixels 20R, 20G, and 20B and the two embedded photodiodes 42 and 43 that are the two photoelectric conversion units of the AF pixels 20V and 20H are respectively P-type well layers. N-type charge storage layer 74 provided on 52 and a P-type depletion prevention layer 73 provided on the upper surface thereof. These photoelectric conversion portions do not necessarily have to be configured as buried photodiodes, and it is not always necessary to provide the depletion prevention layer 73.

  As understood from FIGS. 8 and 9, the embedded photodiodes 42 and 43 are configured by dividing the embedded photodiode corresponding to the embedded photodiode 41 into two parts. In the AF pixel 20V, the embedded photodiodes 42 and 43 are configured by being divided into a + Y side and a −Y side. Therefore, in the AF pixel 20V, as in the case of FIG. 6 of Patent Document 4 described above, incident light guided from the microlens of the pixel is divided into pupils and incident on the embedded photodiodes 41 and 42. Although not shown in the drawing, the AF pixel 20H differs from the AF pixel 20V only in the division direction of the photoelectric conversion unit and the arrangement of the transfer transistors 46, 47, and the like. The AF pixel 20H is configured by dividing an embedded photodiode corresponding to the embedded photodiode 41 into two on the + X side and the −X side.

For example, the thickness of the charge storage layer 74 is 0.3 micrometers, and its concentration ranges from 5E16 / cm ³ to 5E17 / cm ³ . For example, the thickness of the depletion preventing layer 73 is 0.2 micrometers, and the concentration thereof is in the range of 1E18 / cm ³ to 1E19 / cm ³ .

  A thin silicon oxide film 75 is disposed on the upper surface of the depletion prevention layer 73. Here, the film thickness is, for example, 0.05 micrometers. The pixels 20R, 20G, 20B, 20V, and 20H are electrically separated by the separation region 76. In the isolation region 76, a thick LOCOS silicon oxide film (hereinafter referred to as a LOCOS oxide film) 78 is disposed, and a P-type isolation diffusion layer 79 is further disposed therebelow. The thickness of the LOCOS oxide film 78 is, for example, 0.8 micrometers. However, it is not limited to this.

In the present embodiment, a crosstalk reducing layer 77 is disposed inside the P-type well layer 52 at a portion facing the charge storage layer 74 of the embedded photodiodes 42 and 43 of the AF pixels 20V and 20H. . The crosstalk reduction layer 77 constitutes a crosstalk reduction unit that reduces crosstalk in which charges generated in the AF pixels 20V and 20H are mixed into the imaging pixels 20R, 20G, and 20B adjacent to the AF pixels. . The crosstalk reducing layer 77 is P-type having the same conductivity type as the P-type well layer 52 and has a higher concentration than the P-type well layer 52. The concentration of the crosstalk reducing layer 77 is preferably 10 times or more the concentration of the P-type well layer 52. Here, the peak concentration of the crosstalk reducing layer 77 is, for example, 3E17 / cm ³ .

  In the present embodiment, since the crosstalk reducing layer 77 is disposed, as shown in FIG. 9, in the AF pixels 20V and 20H, light 81 incident to a position deeper than this (on the N-type silicon substrate 51 side) is used. The generated charges (electrons) 82 are drifted toward the higher potential (that is, toward the N-type silicon substrate 51), and are absorbed by the N-type silicon substrate 51. Therefore, the charges generated in the AF pixels 20H and 20V by the incident light having a long wavelength are not drifted toward the adjacent imaging pixels 20R, 20G, and 20B. Therefore, this charge is not captured by the charge storage layer 74 of the adjacent imaging pixels 20R, 20G, and 20B, and the imaging signal does not increase. Therefore, it is obtained from the imaging signals obtained from the imaging pixels 20R, 20G, and 20B in regions other than the AF pixels 20V and 20H, and the imaging pixels 20R, 20G, and 20B in the regions near the AF pixels 20V and 20H. There is no difference in signal magnitude between the imaging signal and a high-quality image can be obtained.

  The depth of the crosstalk reducing layer 77 may be equal to or less than the depth at which red wavelength light enters. Therefore, the depth d1 of the peak concentration point of the crosstalk reducing layer 77 from the silicon surface may be about 3.5 microns or less. However, in order to further improve the above-described effect, it is preferable that the depth d1 is shallower. Here, the depth d1 is set to 2.5 microns, for example.

  In the present embodiment, the crosstalk reducing layer 77 has a rising portion 77a rising from the depth d1 to the depth d2 on the separation region 76 side. As shown in FIG. 9, due to the rising portion 77a, the electric charge 84 generated by the light 83 incident on the separation region 76 side at a position shallower than the crosstalk reducing layer 77 is also applied to the adjacent imaging pixels 20R, 20G, and 20B. It becomes difficult to drift. Therefore, the effect mentioned above increases more. However, in the present invention, the rising portion 77 a is not necessarily provided in the crosstalk reducing layer 77.

  Next, an example of a method for manufacturing the solid-state imaging device 3 used in the present embodiment will be described with reference to FIG. FIG. 10 is a schematic sectional view showing each manufacturing process and corresponds to FIG.

  First, a step of forming a P-type well layer 52 in a predetermined region of the N-type silicon substrate 51 is performed. That is, a silicon thermal oxide film is provided on the surface of the N-type silicon substrate 51, and the silicon thermal oxide film in the portion that becomes the P-type well layer 52 is removed by photolithography, and ion implantation and a predetermined heat treatment are performed using this portion as an opening. .

Ion implantation and heat treatment are performed so that the concentration of the P-type well layer 52 is 5E15 / cm ³ to 5E16 / cm ³ . In order to align the concentration of the P-type well layer 52 in the depth direction, it is preferable to perform ion implantation in a plurality of times by changing the acceleration voltage.

Next, a step of forming an isolation region by the LOCOS oxide film 78 is performed. That is, first, a silicon nitride film is formed by a CVD method and patterned so as to leave a portion that becomes an active region. A thick LOCOS oxide film is later formed in the opening, but as is well known, an isolation diffusion layer 79 is provided in advance in the opening. The separation diffusion layer 79 finally has a depth of 0.8 micrometers and a concentration of 1E17 / cm ³ to 1E18 / cm ³ . Next, a LOCOS oxide film 78 having a thickness of 0.8 μm is formed in this opening by a thermal oxidation method. After removing the silicon nitride film, a thin silicon oxide film 75 is formed in the active region by a thermal oxidation method for the purpose of a protection film for ion implantation. FIG. 10A shows this state.

Next, a step of forming the crosstalk reducing layer 77 is performed. That is, a predetermined heat treatment is performed by ion implantation to form a crosstalk reducing layer 77 having a peak concentration of 3E17 / cm ^{3 at} a depth of 2.5 micrometers. The heat treatment here is performed at a lower temperature than the heat treatment for forming the P-type well layer 52. By performing at a low temperature, the peak concentration of the crosstalk reducing layer 77 is increased. At this time, ions are implanted deeply in the thin silicon oxide film 75 and shallow in the thick LOCOS oxide film 78, whereby a crosstalk reducing layer 77 having a rising portion 77a is easily formed to a predetermined depth. The FIG. 10B shows this state. Needless to say, a resist mask is formed in a region where the crosstalk reducing layer 77 is not formed (region where ions are not implanted). The thickness of the resist varies depending on the acceleration voltage, but is about 3 to 5 micrometers.

  In order to simplify the description, it is assumed that the thin silicon oxide film 75 is held until the solid-state imaging device 3 is completed. However, the thin silicon oxide film 75 used here is removed after the completion of this process, and the oxide film in each part may be formed again by changing the film thickness depending on the purpose, such as a protective film on the depletion prevention layer 73 or a gate oxide film. Good.

  Next, a step of providing a predetermined diffusion portion is performed. That is, the known photolithographic etching method and impurity diffusion method are repeated to form active elements in the respective pixels 20R, 20G, 20B, 20V, and 20H and active elements of peripheral circuits. The diffusion part of the MOS transistor is formed by self-alignment using a LOCOS oxide film and polysilicon. The diffusion portion (charge accumulation layer 74, depletion prevention layer 73) disposed in the photoelectric conversion portion is preferably formed after each gate electrode made of polysilicon is provided in order to suppress variation in charge transfer. FIG. 10C shows this state. Then, the solid-state imaging device 3 is completed by forming wirings, color filters, microlenses, protective films, and the like.

  Next, each example of the driving procedure of the solid-state imaging device 3 will be described with reference to FIGS. 11 and 12. FIG. 11 is a timing chart showing a driving procedure of the solid-state image sensor 3 in the focus detection mode (operation mode for reading a focus detection signal from the solid-state image sensor 3). FIG. 12 is a timing chart showing a driving procedure of the solid-state image sensor 3 in the image-capturing mode (an operation mode for reading an imaging signal from the solid-state image sensor 3). Note that a transistor included in each pixel is an NMOS transistor, and is turned on in response to a high level (high) driving signal.

  First, a driving procedure in the focus detection mode will be described with reference to FIG. First, in the period T1, φTGA and φTGB of all rows are set to high, and the transfer transistors 45 to 47 of all the pixels 20R, 20G, 20B, 20V, and 20H are turned on. At this time, φR of all rows is set high and the reset transistors 49 of all the pixels 20R, 20G, 20B, 20V, and 20H are turned on. Therefore, in the period T1, all the pixels 20R, 20G, 20B, 20V, and 20H are turned on. The embedded photodiodes 41 to 43 and the floating diffusion portion 44 are reset. ΦTGA and φTGB of all the rows are set to low after the period T1, and the transfer transistors 45 to 47 of all the pixels 20R, 20G, 20B, 20V, and 20H are turned off.

  In a period T2 after the period T1, a mechanical shutter (not shown) is opened. This period T2 is an exposure period.

  Next, in a period T3, φS in the first row is set high. As a result, the selection transistor 50 in the first row is turned on, row selection in the first row is started, and source follower readout by the pixel amplifier 48 in the first row is started.

  The period T11 is started after a predetermined period has elapsed since the start of the period T3. In the period T11, φR in the first row is set low, the reset transistor 49 in the first row is turned off, and the reset of the floating diffusion portion 44 in the first row is completed. Between the start time of the period T11 and the start time of the period T14, the dark level of the first row (the signal output from the pixel amplifier 48 of the first row corresponding to the reset state of the floating diffusion portion 44) is a pixel. Clamped (stored) in the CDS circuit 27 from the amplifier 48 via the vertical signal line 25. This dark level is due to the signal charge transferred from the embedded photodiodes 41 and 42 (denoted as PDA in FIG. 11) in response to the φTGA in the first row because the next read signal is embedded. Used as a dark level for the photodiodes 41 and 42 (PDA).

  In period T14, φTGA in the first row is set high, and the transfer transistors 45 and 46 in the first row are turned on. As a result, the signal charge accumulated in the embedded photodiode 41 of the imaging pixels 20R, 20G, and 20B in the first row and the embedded photodiode 42 in one of the AF pixels 20V and 20H in the first row were accumulated. The signal charge is transferred to the floating diffusion portion 44 of the pixel. Then, at the end of the period T14, φTGA in the first row is set low, and the transfer transistors 45 and 46 in the first row are turned off. Between the end time of the period T14 and the end time of the period T11 (start time of the period T12), the potential fluctuation due to the charge transferred to the floating diffusion portion 44 in the first row is transmitted from the pixel amplifier 48 via the vertical signal line 25. And is clamped to the CDS circuit 27. That is, signal reading of the embedded photodiodes 41 and 42 (PDA) is performed. Then, the CDS circuit 27 acquires a difference signal between this signal related to the embedded photodiodes 41 and 42 (PDA) and the previous dark level related to the embedded photodiodes 41 and 42 (PDA). Of these differential signals, only the one relating to one of the embedded photodiodes 42 of the AF pixels 20V and 20H is used as a focus detection signal.

  In period T12, φR in the first row is set high, the reset transistor 49 in the first row is turned on, and the floating diffusion portion 44 in the first row is reset.

  Period T13 starts from the end of period T12. In period T13, φR in the first row is set low, the reset transistor 49 in the first row is turned off, and the reset of the floating diffusion portion 44 is completed. Between the start time of the period T13 (end time of the period T12) and the start time of the period T15, the dark level of the first row (output from the pixel amplifier 48 of the first row corresponding to the reset state of the floating diffusion portion 44) Signal) is clamped (stored) from the pixel amplifier 48 to the CDS circuit 27 via the vertical signal line 25. This dark level is due to the signal charge transferred from the embedded photodiode 43 (indicated as PDB in FIG. 11) in response to the φTGB in the first row for the next read signal. Used as the dark level for 43 (PDB).

  In period T15, φTGB in the first row is set high, and the transfer transistor 47 in the first row is turned on. As a result, the signal charge accumulated in the other embedded photodiode 43 of the AF pixels 20V and 20H in the first row is transferred to the floating diffusion portion 44 of the pixel. Then, at the end of the period T15, φTGB in the first row is set low and the transfer transistor 47 in the first row is turned off. Between the end point of the period T15 and the end point of the period T13 (end point of the period T3), the potential fluctuation due to the charge transferred to the floating diffusion portion 44 in the first row is transmitted from the pixel amplifier 48 via the vertical signal line 25. And is clamped to the CDS circuit 27. That is, signal reading of the embedded photodiode 43 (PDB) is performed. Then, the CDS circuit 27 acquires a difference signal between this signal related to the embedded photodiode 43 (PDB) and the previous dark level related to the embedded photodiode 43 (PDB). This difference signal is used as a focus detection signal.

  Thereafter, at the end of the period T3 (end of the period T13), φR in the first row is set high, the reset transistor 49 in the first row is turned on, and resetting of the floating diffusion portion 44 in the first row is started. At the same time, φS in the first row is set low, the selection transistor 50 in the first row is turned off, and the row selection in the first row is completed.

  Next, the process proceeds to the selection operation period T4 of the next second row through the horizontal blanking period. Since the same operation as the first line is repeated in the second and subsequent lines, the description thereof is omitted here. In this way, when signals are read from all rows, the focus detection mode is terminated.

  Next, a driving procedure in the imaging mode will be described with reference to FIG. In the imaging mode, the signal from the embedded photodiode 43 of the AF pixels 20V and 20H is not used and has no meaning, so φTGB may be arbitrary. Accordingly, FIG. 12 does not describe φTGB.

  In the imaging mode, first, in a period T21, φTGA of all the rows is set high, and the transfer transistors 45 and 46 of all the pixels 20R, 20G, 20B, 20V, and 20H are turned on. At this time, φR of all rows is set high, and the reset transistors 49 of all the pixels 20R, 20G, 20B, 20V, and 20H are turned on, so that at least the embedded photodiodes of the pixels 20R, 20G, and 20B are turned on in the period T21. 41 and the floating diffusion 44 are reset. ΦTGA of all rows is set to low after period T21, and the transfer transistors 45 and 46 of the pixels 20R, 20G, 20B, 20V, and 20H are turned off.

  In a period T22 after the period T21, a mechanical shutter (not shown) is opened. This period T22 is an exposure period.

  Next, in a period T23, φS in the first row is set high. As a result, the selection transistor 50 in the first row is turned on, row selection in the first row is started, and source follower readout by the pixel amplifier 48 in the first row is started.

  The period T31 is started after a predetermined period has elapsed since the start of the period T23. In period T31, φR in the first row is set low, the reset transistor 49 in the first row is turned off, and resetting of the floating diffusion portion 44 in the first row is completed. Between the start time of the period T31 and the start time of the period T32, the dark level of the first row (the signal output from the pixel amplifier 48 of the first row corresponding to the reset state of the floating diffusion portion 44) is the pixel. Clamped (stored) in the CDS circuit 27 from the amplifier 48 via the vertical signal line 25. This dark level is due to the signal charge transferred from the embedded photodiodes 41 and 42 (denoted as PDA in FIG. 11) in response to the φTGA in the first row because the next read signal is embedded. Used as a dark level for the photodiodes 41 and 42 (PDA).

  In the period T32, φTGA in the first row is set high, and the transfer transistors 45 and 46 in the first row are turned on. As a result, the signal charge accumulated in the embedded photodiode 41 of the imaging pixels 20R, 20G, and 20B in the first row and the embedded photodiode 42 in one of the AF pixels 20V and 20H in the first row were accumulated. The signal charge is transferred to the floating diffusion portion 44 of the pixel. Then, at the end of the period T32, φTGA in the first row is set to low, and the transfer transistors 45 and 46 in the first row are turned off. Between the end point of the period T32 and the end point of the period T31 (end point of the period T23), potential fluctuation due to the charge transferred to the floating diffusion portion 44 in the first row is transmitted from the pixel amplifier 48 via the vertical signal line 25. And is clamped to the CDS circuit 27. That is, signal reading of the embedded photodiodes 41 and 42 (PDA) is performed. Then, the CDS circuit 27 acquires a difference signal between this signal related to the embedded photodiodes 41 and 42 (PDA) and the previous dark level related to the embedded photodiodes 41 and 42 (PDA). Of these difference signals, only those relating to the embedded photodiode 41 of the imaging pixels 20R, 20G, and 20B are used as imaging signals.

  Thereafter, at the end of the period T23 (end of the period T31), φR in the first row is set high, the reset transistor 49 in the first row is turned on, and resetting of the floating diffusion portion 44 in the first row is started. At the same time, φS in the first row is set low, the selection transistor 50 in the first row is turned off, and the row selection in the first row is completed.

  Next, the process proceeds to the selection operation period T24 of the second row through the horizontal blanking period. Since the same operation as the first line is repeated in the second and subsequent lines, the description thereof is omitted here. In this way, when signals are read from all rows, the imaging mode is terminated.

  Here, an example of the operation of the electronic camera 1 according to the present embodiment will be described with reference to FIGS. FIG. 13 is a schematic flowchart showing the operation of the electronic camera 1 according to the present embodiment.

  When the half-press operation of the release button of the operation unit 9a is performed (step S1), the microprocessor 9 in the electronic camera 1 drives the imaging control unit 4 in synchronization with the half-press operation. The imaging control unit 4 reads out an imaging signal for subject confirmation from all the pixels of the imaging pixels 20R, 20G, and 20B or a predetermined pixel by a known method that is predetermined for confirming the subject, and stores it in the memory 7. accumulate. At this time, when all the pixels are read out, for example, the same operation as that shown in FIG. 12 is performed. Then, the image processing unit 13 recognizes the subject from the signal using an image recognition technique (step S2). For example, in the face recognition mode, a face is recognized as a subject. At this time, the image processing unit 13 obtains the position and shape of the subject.

  Thereafter, the microprocessor 9 should be used for focus detection, which is optimal for accurately detecting the focus adjustment state for the subject from the focus detection regions 32 to 37 according to the position and shape of the subject obtained in step 2. A focus detection area corresponding to the autofocus line sensor is set (step S3). Further, the microprocessor 9 sets shooting conditions (aperture, focus adjustment state, shutter time, etc.) for focus detection based on the recognition result in step S2 (step S4).

  Subsequently, the microprocessor 9 operates the lens control unit 2a so as to satisfy the conditions such as the diaphragm set in step S4, and the focus detection region set in step S3 under the conditions such as the shutter time set in step S4. By driving the imaging control unit 4 according to the coordinates of the pixel row of the AF pixel 20V or 20H, the focus detection signal is read out and stored in the memory 7 (step S5). At this time, the focus detection signal is read out by the same operation as that shown in FIG.

  Next, the microprocessor 9 picks up a focus detection signal from the AF pixel 20V or 20H in the focus detection area set in step S3 from all the pixel signals acquired in step S5 and stored in the memory 7. Then, the focus detection calculation unit 10 is made to calculate the defocus amount by causing the focus detection calculation unit 10 to perform calculation (focus adjustment state detection processing) according to the pupil division phase difference method based on these signals ( Step S6).

  Next, the microprocessor 9 causes the lens control unit 2a to adjust the photographing lens 2 so as to be in focus according to the defocus amount calculated in step S6. Subsequently, the microprocessor 9 sets shooting conditions (aperture, shutter time, etc.) for the main shooting (step S8).

  Next, the microprocessor 9 operates the lens control unit 2a so as to satisfy the conditions such as the aperture set in step S8, and the shutter set in step S9 in synchronization with the full pressing operation of the release button of the operation unit 9a. By driving the imaging control unit 4 under conditions such as time, an image signal is read out and actual imaging is performed (step S9). At this time, the imaging signal is read out by the same operation as that shown in FIG. The imaging control unit 4 accumulates the imaging signal in the memory 7.

  Thereafter, the microprocessor 9 performs a desired process in the image processing unit 13 or the image compression unit 12 as necessary based on a command from the operation unit 9a, and outputs a processed signal to the recording unit to the recording medium 11a. Record.

  According to the present embodiment, as described with reference to FIG. 9, since the crosstalk reducing layer 77 is disposed in the P-type well layer 52 in the solid-state imaging device 3, the AF pixels 20V and 20H Crosstalk in which charges are mixed into the neighboring imaging pixels 20R, 20G, and 20B is reduced, and thereby a high-quality image can be obtained.

  [Second Embodiment]

  FIG. 14 is a schematic cross-sectional view schematically showing a solid-state imaging device 90 used in an electronic camera according to the second embodiment of the present invention, and corresponds to FIG. 14, elements that are the same as or correspond to those in FIG. 9 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment is different from the first embodiment only in that a solid-state image sensor 90 is used instead of the solid-state image sensor 3. Where the solid-state image sensor 90 is different from the solid-state image sensor 3, the P-type well layer 52 is not provided with the crosstalk reducing layer 77, and the P-type (P-type) corresponding to the separation diffusion layer 79 of the solid-state image sensor 3. Of the separation diffusion layers 79a and 79b of the same conductivity type as the well layer 52), the separation diffusion disposed in the separation region 76 between the AF pixels 20V and 20H and the imaging pixels 20R, 20G and 20B adjacent thereto. Most of the depth d3 of the layer 79a is only deeper than the depth d4 of the P-type separation diffusion layer 79b disposed in the separation region 76 between the imaging pixels 20R, 20G, and 20B. is there. The concentration of the separation diffusion layers 79 a and 79 b is higher than the concentration of the P-type well layer 52, for example, the same concentration as that of the separation diffusion layer 79 of the solid-state imaging device 3. In the present embodiment, the depth d4 of the separation diffusion layer 79b is the same as the depth of the separation diffusion layer 79 of the solid-state imaging device 3.

  The isolation diffusion layer 79b simply isolates electrical connections between pixels or between elements in the pixel, whereas the isolation diffusion layer 79a having a portion of depth d3 has such an isolation function. It also functions as a crosstalk reducing unit that reduces crosstalk in which the charges generated in the AF pixels 20V and 20H are mixed into the imaging pixels 20R, 20G, and 20B adjacent to the AF pixels. In order to reduce such crosstalk, the depth d3 of the isolation diffusion layer 79a is preferably as deep as possible. However, here, the depth d3 is, for example, 2.5 microns.

  In the case of manufacturing the solid-state imaging device 90 used in the present embodiment, for example, the same steps as the manufacturing method of the solid-state imaging device 3 described with reference to FIG. I do. However, at this time, in addition to ion implantation at the same time as the separation diffusion layer 79b, further ion implantation is performed at a position corresponding to the separation diffusion layer 79a under appropriate conditions so as to form a deep portion of the separation diffusion layer 79a. . Thereafter, the solid-state imaging device 90 is completed by performing the steps after FIG. 10B described as the manufacturing method of the solid-state imaging device 3.

  In this embodiment, since most of the depth d3 of the separation diffusion layer 79a is deepened, as shown in FIG. 14, the charge generated by the light 101 incident to a relatively deep position on the separation diffusion layer 79a side. The (electron) 102 is less likely to drift toward the adjacent imaging pixels 20R, 20G, and 20B. For this reason, it is reduced that this charge is captured by the charge storage layer 74 of the adjacent imaging pixels 20R, 20G, and 20B and the imaging signal increases. Therefore, it is obtained from the imaging signals obtained from the imaging pixels 20R, 20G, and 20B in regions other than the AF pixels 20V and 20H, and the imaging pixels 20R, 20G, and 20B in the regions near the AF pixels 20V and 20H. There is no difference in signal magnitude between the imaging signal and a high-quality image can be obtained.

  In the present embodiment, the substrate 51 is an N-type silicon substrate here. Thus, if the conductivity type of the substrate 51 is N-type opposite to that of the P-type well layer 52, the charge (not shown) photoelectrically converted at a deep position is absorbed by the substrate 51 and is adjacent to the imaging pixel. This is more preferable because less charge drifts toward 20R, 20G, and 20B. However, in the present invention, the present embodiment may be modified so that a P-type substrate is used as the substrate 51.

  [Third Embodiment]

  FIG. 15 is a schematic sectional view schematically showing a solid-state imaging device 110 used in an electronic camera according to the third embodiment of the present invention, and corresponds to FIG. 15, elements that are the same as or correspond to those in FIG. 9 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment differs from the first embodiment only in that a solid-state image sensor 110 is used instead of the solid-state image sensor 3. The solid-state image sensor 110 is different from the solid-state image sensor 3 only in that a crosstalk reducing layer 111 is disposed in the P-type well layer 52 instead of the crosstalk reducing layer 77.

  The crosstalk reduction layer 111 is formed in the P-type well layer 52 so as to extend to the AF pixels 20V and 20H and the imaging pixels 20R, 20G, and 20B adjacent thereto. The crosstalk reduction layer 111 constitutes a crosstalk reduction unit that reduces crosstalk in which charges generated in the AF pixels 20V and 20H are mixed into the imaging pixels 20R, 20G, and 20B adjacent to the AF pixels. . The crosstalk reducing layer 111 is P-type having the same conductivity type as the P-type well layer 52 and has a higher concentration than the P-type well layer 52. The concentration of the crosstalk reducing layer 111 is preferably 10 times or more the concentration of the P-type well layer 52.

  In the present embodiment, the peak density of the portion 111a disposed in the separation region 76 between the AF pixels 20V and 20H and the imaging pixels 20R, 20G, and 20B adjacent to the AF pixel in the crosstalk reduction layer 111. The depth d5 from the silicon surface of the point is made shallower than the depth d6 from the silicon surface at the point of the peak concentration of the portion 111b arranged in the AF pixels 20V and 20H in the crosstalk reducing layer 111. Yes.

  Further, in the present embodiment, the depth d6 is the peak density point of the portion 111c arranged in the imaging pixels 20R, 20G, 20B adjacent to the AF pixels 20V, 20H in the crosstalk reduction layer 111. It is shallower than the depth d7 from the silicon surface.

  Next, an example of a method for manufacturing the solid-state imaging device 110 used in the present embodiment will be described with reference to FIG. FIG. 16 is a schematic sectional view showing each manufacturing process, and corresponds to FIG.

  First, the same steps as those in the method for manufacturing the solid-state imaging device 3 described with reference to FIG. 10A are performed until the state shown in FIG. Next, since a step is provided in the crosstalk reduction layer 111 between the lower part of the focus detection pixels 20V and 20H and the lower part of the imaging pixels 20R, 20G, and 20B adjacent to the AF pixel, as an additional mask material The resist 120 is patterned in portions corresponding to the AF pixels 20V and 20H and the separation region 76 around them. The thicker the silicon oxide film is, the shorter the distance from which ions are implanted from the silicon surface. The resist has a similar effect on ion implantation. In the AF pixels 20V and 20H where the resist 120 thinner than the ion implantation range is disposed, ions are implanted shallower than the imaging pixels 20R, 20G and 20B where the resist 120 is not disposed. FIG. 16A shows a state in which the resist 120 is arranged.

  In the present embodiment, the crosstalk reduction layer 111 is not formed in a region other than the region extending over the AF pixels 20V and 20H and the imaging pixels 20R, 20G, and 20B adjacent thereto. For this reason, although not shown in the drawing, a resist (ion implantation prevention resist) having a sufficient thickness to prevent ion implantation is formed in a region where the crosstalk reducing layer 111 is not formed. However, the crosstalk reduction layer 111 may be formed in a region other than the region extending over the AF pixels 20V and 20H and the imaging pixels 20R, 20G, and 20B adjacent to the AF pixels 20V and 20H as appropriate. Ion implantation may be performed.

  Next, a step of forming the crosstalk reducing layer 111 is performed. That is, ions are implanted and the resist 120 and the ion implantation blocking resist are removed, and then a predetermined heat treatment is performed. Thereby, the crosstalk reducing layer 111 having a step is easily formed to a predetermined depth. FIG. 16B shows this state.

  Next, a step of providing a predetermined diffusion portion is performed. That is, the known photolithographic etching method and impurity diffusion method are repeated to form active elements in the respective pixels 20R, 20G, 20B, 20V, and 20H and active elements of peripheral circuits. FIG. 16C shows this state. Then, the solid-state imaging device 110 is completed by forming wirings, color filters, microlenses, protective films, and the like.

  According to the present embodiment, as described above, the crosstalk reduction layer 111 is formed so as to extend over the AF pixels 20V and 20H and the imaging pixels 20R, 20G, and 20B adjacent thereto. Therefore, as shown in FIG. 15, the charges 133 and 134 generated by the light 131 and 132 incident to the deeper position (on the substrate 51 side) than the crosstalk reducing layer 111 in the AF pixels 20V and 20H are the AF pixels 20V and 20H. The charge accumulation layer 74 of the imaging pixels 20R, 20G, and 20B adjacent to 20H is not supplemented. For this reason, the crosstalk in which the charges generated by the incident light entering the substrate 51 side from the crosstalk reducing layer 111 in the AF pixels 20V and 20H are mixed into the adjacent imaging pixels 20R, 20G, and 20B is surely prevented. Is done. Accordingly, it is obtained from the imaging signals obtained from the imaging pixels 20R, 20G, and 20B in regions other than the AF pixels 20V and 20H, and the imaging pixels 20R, 20G, and 20B in the regions near the AF pixels 20V and 20H. There is no difference in signal magnitude between the imaging signal and a high-quality image can be obtained.

  Further, in the present embodiment, as described above, the depth d5 of the portion 111a disposed in the isolation region 76 in the crosstalk reducing layer 111 is disposed in the AF pixels 20V and 20H in the crosstalk reducing layer 111. It is made shallower than the depth d6 of the portion 111b. Therefore, the charges generated on the surface side of the crosstalk reducing layer 111 in the AF pixels 20V and 20H have a high probability of being captured by the charge accumulation layer 74 of the AF pixel, and the adjacent imaging pixels 20R, 20G, The probability of being supplemented by the 20B charge storage layer 74 is reduced. Therefore, also from this point, crosstalk from the AF pixels 20V and 20H to the imaging pixels 20R, 20G, and 20B is reduced. Therefore, also from this point, the imaging signals obtained from the imaging pixels 20R, 20G, and 20B in areas other than the AF pixels 20V and 20H, and the imaging pixels 20R and 20G in the areas near the AF pixels 20V and 20H. , 20B, no difference occurs in the magnitude of the signal from the imaging signal obtained from 20B, and a high-quality image can be obtained.

  Furthermore, in the present embodiment, as described above, the depth d6 of the portion 111b arranged in the AF pixels 20V and 20H in the crosstalk reduction layer 111 is equal to the adjacent imaging pixels 20R and 20B in the crosstalk reduction layer 111. It is made shallower than the depth d7 of the part 111c arrange | positioned at 20G, 20B. Therefore, the charges generated on the surface side of the crosstalk reducing layer 111 in the AF pixels 20V and 20H have a high probability of being captured by the charge accumulation layer 74 of the AF pixel, and the adjacent imaging pixels 20R, 20G, The probability of being supplemented by the 20B charge storage layer 74 is reduced. Therefore, also from this point, crosstalk from the AF pixels 20V and 20H to the imaging pixels 20R, 20G, and 20B is reduced. Therefore, also from this point, the imaging signals obtained from the imaging pixels 20R, 20G, and 20B in areas other than the AF pixels 20V and 20H, and the imaging pixels 20R and 20G in the areas near the AF pixels 20V and 20H. , 20B, no difference occurs in the magnitude of the signal from the imaging signal obtained from 20B, and a high-quality image can be obtained. However, in the present invention, it is not always necessary to make the depth d6 shallower than the depth d7. For example, the depth d6 and the depth d7 may be the same.

  Furthermore, in the present embodiment, the depth d7 of the portion 111c arranged in the imaging pixels 20R, 20G, and 20B in the crosstalk reducing layer 111 is deep. Therefore, the effect that the sensitivity of the imaging pixels 20R, 20G, and 20B is improved is also obtained.

  In the present invention, this embodiment may be modified to use a P-type substrate as the substrate 51.

  [Fourth Embodiment]

  FIG. 17 is a schematic cross-sectional view schematically showing a solid-state imaging device 140 used in an electronic camera according to the fourth embodiment of the present invention, and corresponds to FIG. 17, elements that are the same as or correspond to those in FIG. 9 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment differs from the first embodiment only in that a solid-state image sensor 140 is used instead of the solid-state image sensor 3. The solid-state imaging device 140 is different from the solid-state imaging device 3 in that the crosstalk reduction layer 77 is removed and the P-type well layer 52 is provided on the N-type silicon substrate 51 forming the first semiconductor layer. The P-type epitaxial layer 152 is formed as the second semiconductor layer, and the N-type silicon substrate 51 includes the charge storage layers 74 of the embedded photodiodes 42 and 43 of the AF pixels in the AF pixels 20V and 20H. It is only the point which has the convex part 51a which protruded in the side. In the present embodiment, the convex portion 51a includes a crosstalk reducing unit that reduces crosstalk in which charges generated in the AF pixels 20V and 20H are mixed into the imaging pixels 20R, 20G, and 20B adjacent to the AF pixels. It is composed.

  Next, an example of a method for manufacturing the solid-state imaging device 140 used in the present embodiment will be described with reference to FIGS. 18 and 19 are schematic sectional views showing the respective manufacturing steps, and correspond to FIG.

  First, an N-type silicon substrate 51 is prepared, and a mask material is patterned on the N-type silicon substrate 51 so as to cover only the region corresponding to the convex portion 51a, and regions other than the region corresponding to the convex portion 51a are formed. The mask material is removed by dry etching. FIG. 18A shows this state. The mask material may be anything that is durable to silicon etching. For example, a resist is used. Further, wet etching may be performed instead of dry etching.

  Next, a P-type epitaxial layer 152 is formed on the N-type silicon substrate 51 in the state shown in FIG. 18A using a known epitaxial technique. FIG. 18B shows this state. On the surface of the P-type epitaxial layer 152, there is a step corresponding to the shape of the convex portion 51a.

  Subsequently, the surface of the P-type epitaxial layer 152 having a step is polished and planarized according to a well-known CMP technique. FIG. 18C shows this state.

  Next, a step of forming an isolation region by the LOCOS oxide film 78 is performed. That is, first, a silicon nitride film is formed by a CVD method and patterned so as to leave a portion that becomes an active region. A thick LOCOS oxide film is later formed in the opening, but as is well known, an isolation diffusion layer 79 is provided in advance in the opening. Next, a LOCOS oxide film 78 is formed in the opening by a thermal oxidation method. After removing the silicon nitride film, a thin silicon oxide film 75 is formed in the active region by a thermal oxidation method for the purpose of a protection film for ion implantation. FIG. 19A shows this state.

  Next, a step of providing a predetermined diffusion portion is performed. That is, the known photolithographic etching method and impurity diffusion method are repeated to form active elements in the respective pixels 20R, 20G, 20B, 20V, and 20H and active elements of peripheral circuits. FIG. 19B shows this state. Then, the solid-state imaging device 140 is completed by forming wirings, color filters, microlenses, protective films, and the like.

  In the present embodiment, as described above, the N-type silicon substrate 51 has the protrusions 51a protruding toward the charge storage layer 74 of the embedded photodiodes 42 and 43 of the AF pixels in the AF pixels 20V and 20H. is doing. Thereby, the charge storage layers 74 of the AF pixels 20V and 20H are closer to the N-type silicon substrate 51 than the charge storage layers 74 of the imaging pixels 20R, 20G, and 20B. Therefore, as shown in FIG. 17, the electric charge 162 generated by the light 161 incident to a deep position in the AF pixels 20V and 20H is absorbed by the convex portion 51a of the substrate 51 and is adjacent to the imaging pixels 20R, 20G, and 20B. It is not drifted towards. Therefore, this charge is not captured by the charge storage layer 74 of the adjacent imaging pixels 20R, 20G, and 20B, and the imaging signal does not increase. Therefore, it is obtained from the imaging signals obtained from the imaging pixels 20R, 20G, and 20B in regions other than the AF pixels 20V and 20H, and the imaging pixels 20R, 20G, and 20B in the regions near the AF pixels 20V and 20H. There is no difference in signal magnitude between the imaging signal and a high-quality image can be obtained.

  [Fifth Embodiment]

  FIG. 20 is a schematic cross-sectional view schematically showing a solid-state imaging device 170 used in an electronic camera according to the fifth embodiment of the present invention, and corresponds to FIG. 20, elements that are the same as or correspond to those in FIG. 17 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment is different from the fourth embodiment only in that a solid-state image sensor 170 is used instead of the solid-state image sensor 140. The solid-state imaging device 170 is different from the solid-state imaging device 3 in place of the second semiconductor layer made of the P-type epitaxial layer 152 on the N-type silicon substrate 51 (first semiconductor layer) having the convex portions 51a. Only the second semiconductor formed by the P-type well layer 152a and the P-type buried layer as a whole is provided, and both are substantially equivalent. Therefore, the present embodiment can provide the same advantages as those of the fourth embodiment.

  Unlike the solid-state imaging device 140, the solid-state imaging device 170 can be manufactured more easily because the CMP technique is not required for forming the convex portions 51a. An example of a method for manufacturing the solid-state imaging element 170 will be described with reference to FIGS. 21 and 22 are schematic sectional views showing the respective manufacturing steps, and correspond to FIG.

  First, the same steps as the method for manufacturing the solid-state imaging device 3 described with reference to FIG. 10A are performed up to the state shown in FIG. 21A, which is the same as the state shown in FIG. However, in FIG. 10A, the reference numeral 52 is attached to the P-type well layer, whereas in FIG. 21, the reference numeral 152a is attached in accordance with FIG. Further, the thickness of the P-type well layer 152a is made thinner than the thickness of the P-type well layer 52.

  Next, a resist 181 as a mask material for preventing ion implantation is formed in a region corresponding to the convex portion 51a. FIG. 21B shows this state.

  Subsequently, after p-type ions are implanted and the resist 181 is removed, a predetermined heat treatment is performed. As a result, the P-type buried layer 152b is formed on a part of the N-type silicon substrate 51, and the convex portion 51a is formed. FIG. 22A shows this state.

  Next, a step of providing a predetermined diffusion portion is performed. That is, the known photolithographic etching method and impurity diffusion method are repeated to form active elements in the respective pixels 20R, 20G, 20B, 20V, and 20H and active elements of peripheral circuits. FIG. 22B shows this state. Then, wiring, a color filter, a microlens, a protective film, and the like are formed to complete the solid-state image sensor 170.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, in the above-described embodiment, the AF pixels 20V and 20H are pixels having a so-called two-divided photoelectric conversion unit. However, a pixel having only one photoelectric conversion unit may be used as the AF pixel. Is possible. For example, in the above-described AF pixel 20V, the embedded photodiode 42 is removed and only the embedded photodiode 43 is provided, and in the AF pixel 20V, the embedded photodiode 43 is removed and only the embedded photodiode 42 is provided. The pixel having the pixel can be used instead of the AF pixel 20V.

  Further, it goes without saying that each feature of each of the above-described embodiments may be arbitrarily combined as long as it does not contradict the gist thereof. For example, in the solid-state imaging device 90 shown in FIG. 14, the substrate 51 may be provided with a convex portion similar to the convex portion 51a of the solid-state imaging device 140 shown in FIG.

It is a schematic block diagram which shows the electronic camera as an imaging device which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. It is a schematic plan view which shows typically the solid-state image sensor in FIG. FIG. 4 is a schematic enlarged view in which the vicinity of a predetermined focus detection region in FIG. 3 is enlarged. FIG. 4 is a schematic enlarged view in which the vicinity of another focus detection region in FIG. 3 is enlarged. It is a circuit diagram which shows the pixel for an imaging of the solid-state image sensor in FIG. It is a circuit diagram which shows the focus detection pixel (AF pixel) of the solid-state image sensor in FIG. FIG. 2 is a schematic plan view schematically showing 2 × 2 pixels of the solid-state imaging device in FIG. 1. It is a schematic sectional drawing in alignment with the A-A 'line in FIG. It is a schematic sectional drawing which shows each manufacturing process of the solid-state image sensor in FIG. It is a timing chart which shows the drive procedure of the solid-state image sensor in FIG. 1 at the time of focus detection mode. It is a timing chart which shows the drive procedure of the solid-state image sensor in FIG. 1 at the time of imaging mode. It is a schematic flowchart which shows operation | movement of the electronic camera by 1st Embodiment. It is a schematic sectional drawing which shows typically the solid-state image sensor used by 2nd Embodiment. It is a schematic sectional drawing which shows typically the solid-state image sensor used in 3rd Embodiment. It is a schematic sectional drawing which shows each manufacturing process of the solid-state image sensor shown in FIG. It is a schematic sectional drawing which shows typically the solid-state image sensor used in 4th Embodiment. It is a schematic sectional drawing which shows each manufacturing process of the solid-state image sensor shown in FIG. It is a schematic sectional drawing which shows each manufacturing process following FIG. It is a schematic sectional drawing which shows typically the solid-state image sensor used in 5th Embodiment. It is a schematic sectional drawing which shows each manufacturing process of the solid-state image sensor shown in FIG. It is a schematic sectional drawing which shows each manufacturing process following FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic camera 3,90,110,140,170 Solid-state image sensor 20 pixels 20V, 20H Focus detection pixel (AF pixel)
20R, 20G, 20B Imaging pixels 51a Convex part 51 Substrate (first semiconductor layer)
52 well layer (second semiconductor layer)
74 charge storage layer 76 isolation region 77, 111 crosstalk reduction layer 79, 79a, 79b isolation diffusion layer

Claims (8)

A solid-state imaging device that photoelectrically converts a subject image formed by an optical system,
A plurality of pixels having a photoelectric conversion unit that is two-dimensionally arranged and each generates and accumulates charges according to incident light,
A separation region between the plurality of pixels;
The plurality of pixels output a plurality of imaging pixels that output an imaging signal for forming an image signal indicating the subject image, and a focus detection signal for detecting a focus adjustment state of the optical system. A plurality of focus detection pixels,
Charge generated in the focus detection pixel is applied to the focus detection pixel and / or to a separation region between the focus detection pixel and the imaging pixel adjacent to the focus detection pixel in the separation region. A solid-state imaging device, comprising: a crosstalk reducing unit that reduces crosstalk mixed in the imaging pixels adjacent to the detection pixels. A first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer provided on the first semiconductor layer,
The photoelectric conversion units of the plurality of pixels include the first conductivity type charge storage layer provided in the second semiconductor layer,
The crosstalk reducing unit is a third semiconductor layer disposed in the second semiconductor layer so as to face the charge storage layer of the focus detection pixel, and is more than the second semiconductor layer. The solid-state imaging device according to claim 1, further comprising a third semiconductor layer of the second conductivity type having a high concentration. A first conductivity type or second conductivity type first semiconductor layer, and the second conductivity type second semiconductor layer provided on the first semiconductor layer;
The photoelectric conversion units of the plurality of pixels include the first conductivity type charge storage layer provided in the second semiconductor layer,
The crosstalk reducing unit is the second conductive type separation diffusion layer disposed in a separation region between the focus detection pixel and the imaging pixel adjacent thereto in the separation region, 2. The solid state according to claim 1, further comprising: a separation diffusion layer having a portion deeper than the separation diffusion layer of the second conductivity type disposed in a separation region between the imaging pixels among the separation regions. Image sensor. A first conductivity type or second conductivity type first semiconductor layer, and the second conductivity type second semiconductor layer provided on the first semiconductor layer;
The photoelectric conversion units of the plurality of pixels include the first conductivity type charge storage layer provided in the second semiconductor layer,
The crosstalk reducing unit is a fourth semiconductor layer arranged in the second semiconductor layer so as to extend over the focus detection pixel and the imaging pixel adjacent to the focus detection pixel. A fourth semiconductor layer of the second conductivity type having a higher concentration than the layer,
A portion disposed in a separation region between the focus detection pixel in the fourth semiconductor layer and the imaging pixel adjacent thereto is disposed in the focus detection pixel in the fourth semiconductor layer. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is disposed at a position shallower than the portion.   The portion of the fourth semiconductor layer disposed in the focus detection pixel is disposed at a position shallower than the portion of the fourth semiconductor layer disposed in the imaging pixel. 4. The solid-state imaging device according to 4. A first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer provided on the first semiconductor layer,
The photoelectric conversion units of the plurality of pixels include the first conductivity type charge storage layer provided in the second semiconductor layer,
The first semiconductor layer has a convex portion protruding toward the charge storage layer of the photoelectric conversion unit of the focus detection pixel in the focus detection pixel,
The solid-state imaging device according to claim 1, wherein the crosstalk reducing unit includes the convex portion.   The solid-state imaging device according to claim 1, wherein a color filter is provided in the imaging pixel, and a color filter is not provided in the focus detection pixel. A solid-state imaging device according to any one of claims 1 to 7,
A detection processing unit that outputs a detection signal indicating a focus adjustment state of the optical system based on the focus detection signal from at least some of the plurality of focus detection pixels;
An adjusting unit that adjusts the focus of the optical system based on the detection signal from the detection processing unit;
An imaging apparatus comprising:

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