JP6505803B2 - Storage system control system - Google Patents

Description

The present invention relates to a product (a product (machine), a product (manufacturer), a composition (composition of matter)), and a method (process (including a simple method and a production method)). . In particular, the present invention relates to a power storage device, a control system for a power storage device, a power storage system,
The present invention relates to an electronic circuit, a semiconductor device, a display device, a light emitting device, or another electric device, a driving method thereof, or a manufacturing method thereof. In particular, the present invention relates to a power storage device having an oxide semiconductor,
Control system of power storage device, power storage system, electronic circuit, semiconductor device, display device, light emitting device,
Or other electric devices, a method of driving them, or a method of manufacturing them.

In recent years, secondary batteries such as lithium ion secondary batteries, lithium ion capacitors, air batteries, etc.
Various power storage devices have been actively developed (for example, Patent Document 1). In particular, lithium ion secondary batteries having high output and high energy density can be used in portable information terminals such as mobile phones and smartphones, notebook personal computers, electric devices such as portable music players and digital cameras, or medical devices, hybrid vehicles (HEVs Demand is rapidly expanding with the development of the semiconductor industry, such as next-generation clean energy vehicles such as electric vehicles (EVs) or plug-in hybrid vehicles (PHEVs), and modern information as a source of rechargeable energy Has become an integral part of the

Another example of the conventional power storage device is, for example, a power storage system in which a plurality of battery cells are connected in series (for example, Patent Document 2).

WO 10/113268 JP 2012-135154 A

The conventional power storage device is gradually deteriorated when charge and discharge are repeated, and there is a problem that a decrease in capacity, a rise in resistance, and the like occur.

For example, in the case of a lithium ion secondary battery, the resistance of the negative electrode may increase during the charging period. One of the reasons is that, for example, carrier ions move from the positive electrode to the negative electrode, and when the value of the potential of the negative electrode is less than the allowable value, the carrier ions are precipitated on the negative electrode.

Alternatively, in a conventional power storage device in which a plurality of battery cells are connected in series, if the resistance value of each battery cell is different when charging, each battery cell is based on the voltage of the battery cell having the highest resistance value. Because it is charged, it may not be possible to fully charge all of the plurality of battery cells.

In one embodiment of the present invention, it is an object to suppress deterioration of a power storage device or the like.

Alternatively, in one embodiment of the present invention, it is an object to suppress reduction in capacity of a power storage device or the like due to charge or discharge.

Alternatively, in one embodiment of the present invention, one of the problems is to improve charge efficiency in a plurality of battery cells.

Alternatively, in one embodiment of the present invention, one of the problems is to perform control of a power storage device or the like with low power consumption.

Alternatively, in one embodiment of the present invention, one problem is to improve the reliability of a power storage device or the like.

Alternatively, in one embodiment of the present invention, one problem is to improve the safety of a power storage device or the like.

Alternatively, in one embodiment of the present invention, it is an object to provide a novel storage device control system or storage device or the like. Alternatively, in one embodiment of the present invention, it is an object to provide an efficient storage device control system or storage device or the like.

Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device or the like.

In particular, one aspect of the present invention may be able to solve at least one of the above-mentioned problems. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. Even if the problem is not included in the problems listed above, it will be obvious naturally from the description of the specification, drawings, claims, etc., and the specification, drawings, claims, etc. From the description, it can be extracted as a task.

The inventor of the present application has found that switching of charging and discharging of each power storage device, or switching of series connection and parallel connection of a plurality of power storage devices is performed by providing a switch individually controlling connection of a plurality of power storage devices. .

Furthermore, the inventor of the present application has found that a control circuit is mounted on the power storage device to configure a control system or a power storage system of the power storage device.

One embodiment of the present invention is a control system of a power storage device which controls charging and discharging of at least a first power storage element to a fourth power storage element, which includes a pair of first switches and a pair of second switches A pair of third switches, a pair of fourth switches, a fifth switch, an encoder, a semiconductor circuit, a pair of first connection terminals that can be electrically connected to a power supply, and a load And a pair of second connection terminals that can be electrically connected to each other, and the pair of first switches is configured to transmit the first storage element according to the first control signal and the pair of first connection terminals. And a pair of second switches that are electrically connected to one another or electrically connected to one of the pair of second connection terminals, and the pair of second switches are connected to the second storage element in accordance with the second control signal. Are electrically connected to the pair of first connection terminals, or A one and a function of selecting whether to electrically connect the second connection terminals, a pair of the third switch, the third power storage device according to the third control signal, the pair of first
And a pair of second connection terminals are electrically connected or selected, and the fourth switch pair is configured to select a fourth storage capacitor according to a fourth control signal. The fifth switch has a function of selecting whether the element is electrically connected to the pair of first connection terminals or electrically connected to the pair of second connection terminals, and the fifth switch controls the first control signal. Electrically connecting at least one of the first storage element and the second storage element and at least one of the third storage element and the fourth storage element in series according to one of the fourth control signal The encoder has a function of generating and outputting at least a first control signal to a fourth control signal by encoding a plurality of input data signals. And the semiconductor circuit is one of the first to fourth storage elements. A control system for a power storage device and having a function of outputting a command instructing the respective charging or discharging a plurality of data signals.

In the control system of the power storage device, the semiconductor circuit includes a processor, a memory electrically connected to the processor, and a controller electrically connected to the processor and the memory.
The processor includes a register, and the register includes a first memory circuit having a function of holding data while power is supplied to the processor, and data is supplied while power supply to the processor is stopped. A second memory circuit having a holding function, and the second memory circuit includes a transistor having a function of controlling writing and holding of data, and the transistor has an off current per μm of a channel width It may be 100 zA or less.

One embodiment of the present invention is a power storage system including the control system and the first to fourth power storage elements.

One embodiment of the present invention is an electric device including the above power storage system.

It is possible to suppress the reduction of the capacity of the power storage device due to charging. Alternatively, control of the power storage device can be performed with low power consumption. Alternatively, the reliability of the power storage device can be improved. Or
The safety of the power storage device can be improved. Alternatively, a novel power storage device can be provided. Alternatively, a good power storage device can be provided. Alternatively, charging efficiency for a plurality of power storage devices can be increased.

Alternatively, a highly reliable semiconductor device can be provided.

The figure for demonstrating an electrical storage system. The figure for demonstrating an electrical storage system. The figure for demonstrating an electrical storage system. The figure for demonstrating an electrical storage system. The figure for demonstrating an electrical storage system. The figure for demonstrating an electrical storage system. The figure for demonstrating a control system. The figure for demonstrating a switch. FIG. 6 illustrates a semiconductor circuit. The figure for demonstrating a register | resistor. The figure for demonstrating memory. The figure for demonstrating memory. The figure for demonstrating memory. The figure for demonstrating memory. FIG. 6 illustrates an example of a structure of a transistor. FIG. 6 illustrates an example of a structure of a transistor. The figure for demonstrating a positive electrode. The figure for demonstrating a negative electrode. FIG. 6 illustrates a power storage device. FIG. 6 illustrates a power storage device. The figure for demonstrating an electrical storage system. The figure for demonstrating an electrical storage system. The figure for demonstrating an electric equipment. The figure for demonstrating an electric equipment. The figure for demonstrating an electric equipment.

Embodiments of the present invention will be described in detail below with reference to the drawings.

However, it is easily understood by those skilled in the art that the present invention is not limited to these descriptions, and various changes in its form and aspect may be made. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

In the drawings described in this specification, the size of each component such as the thickness of a film, a layer, or a substrate, the size of a region, or the like may be exaggerated for clarity of the description. is there. Therefore,
Each component is not necessarily limited to the size, and is not limited to the relative size between each component.

Further, in the present specification and the like, the ordinal numbers given as the first, second, and the like are used for the sake of convenience, and do not indicate the order of steps, the order of layers, or the like. In addition, in the present specification and the like, a unique name is not shown as a matter for specifying the invention.

In the structures of the present invention described in this specification and the like, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated. Moreover, when referring to a portion having the same function, the hatch pattern may be the same and may not be particularly designated.

In the actual manufacturing process, although a resist mask or the like may be unintentionally reduced by a process such as etching, it may be omitted in the drawings for easy understanding.

Further, in the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between components is “directly above” or “directly below”. For example, the expression "a gate electrode on a gate insulating layer" does not exclude those including other components between the gate insulating layer and the gate electrode.

In addition, the voltage often indicates the potential difference between a certain potential and a reference potential (for example, the ground potential GND or a source potential). Therefore, the voltage can be reworded as a potential.

Further, in the present specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, "electrodes" may be used as part of "wirings" and vice versa. Furthermore, the terms "electrode" and "wiring" refer to multiple "electrodes"
Also includes the case where the “wiring” is integrally formed.

In addition, the functions of “source” and “drain” may be interchanged when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification and the like, the terms "source" and "drain" can be used interchangeably.

Further, in the present specification and the like, the connection includes the case of being electrically connected, the case of being functionally connected, and the case of being directly connected. Furthermore, the connection relationship of each component shown in the embodiment is
It is not limited only to the connection shown in the figure or the sentence.

In the present specification, etc., active elements (transistors, diodes, etc.), passive elements (
Those skilled in the art may be able to configure one embodiment of the present invention without specifying the connection destinations of all the terminals including a capacitor, a resistor, and the like. That is, even when the connection destination is not specified, it may be possible to determine that one aspect of the invention is clear and described in the present specification and the like. In particular, when a plurality of connection destinations of terminals can be considered, it is not necessary to limit the connection destinations of the terminals to a specific location. Therefore, only some of the terminals of active elements (transistors, diodes, etc.), passive elements (capacitive elements, resistance elements, etc.), etc.
By specifying the connection destination, it may be possible to configure one aspect of the invention.

In the specification and the like, if at least a connection destination is specified for a certain circuit, the person skilled in the art may be able to specify the invention. Alternatively, one skilled in the art may be able to specify the invention by specifying at least the function of a circuit. That is, when the function is specified, it may be possible to determine that one aspect of the invention is clear and described in the present specification and the like. Therefore, if a connection destination is specified for a circuit without specifying a function, the circuit is disclosed as an aspect of the invention, and one aspect of the invention can be configured. Alternatively, if a function is specified for a circuit without specifying a connection destination, the circuit is disclosed as one aspect of the invention, and one aspect of the invention can be configured.

In the present specification and the like, both of the positive electrode and the negative electrode for a secondary battery may be collectively referred to as an electrode. In this case, the electrode indicates at least one of the positive electrode and the negative electrode.

Further, in the present specification and the like, the charge rate C indicates the speed at which the secondary battery is charged. For example, the charge rate in the case of charging a battery having a capacity of 1 Ah at 1 A is 1C. Further, the discharge rate C represents the speed at which the secondary battery is discharged. For example, the discharge rate in the case of discharging a battery with a capacity of 1 Ah at 1 A is 1C.

In addition, the contents described in the modes for carrying out the present invention can be used in appropriate combination.

First Embodiment Storage system]
An example of a power storage device and a power storage system will be described.

[1.1. Constitution]
An example of the circuit configuration of the storage system will be described with reference to FIG.

The storage system illustrated in FIG. 1 includes a storage element 10_1, a storage element 10_2, and a storage element 20_.
, A storage element 20_2, and a pair of switches 11 (switches 11a and 11b)
, A pair of switches 12 (switches 12a and 12b), and a pair of switches 21
(A switch 21a and a switch 21b), a pair of switches 22 (a switch 22a and a switch 22b), a switch 51, and a switch 61.

The switch 11a and the switch 11b are, for example, the storage element 10_1 and a pair of connection terminals 71.
It has a function capable of selecting whether it is connected to (the connection terminal 71a and the connection terminal 71b) or to the connection terminal 72a. Alternatively, the switch 11a has a function of selecting, for example, whether or not the storage element 10_1 is connected to the pair of connection terminals 71 (connection terminals 71a). Alternatively, the switch 11a has a function of, for example, selecting whether or not the storage element 10_1 is connected to the connection terminal 72a. Similarly, the switch 11 b has a function of selecting, for example, whether or not the storage element 10 _ 1 is connected to the pair of connection terminals 71 (connection terminals 71 b). Alternatively, the switch 11 b has a function of, for example, selecting whether to connect or not connect the storage element 10 _ 1 to the connection terminal 72 a. Or switch 11a
Has a function of preventing the storage element 10_1 from being connected to any terminal, for example. Similarly, the switch 11 b has a function of preventing, for example, the storage element 10 _ 1 from being connected to any terminal.

The connection terminal 71a and the connection terminal 71b are, for example, terminals that can be connected to a power supply.

The connection terminal 72a and the connection terminal 72b are, for example, terminals that can be connected to a load.

The switches 12a and 12b have a function of, for example, selecting whether to connect the storage element 10_2 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a.

For example, the switch 21a and the switch 21b have a function of selecting whether to connect the storage element 20_1 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a and the connection terminal 72b. Alternatively, the switch 21a has a function of selecting, for example, whether or not the storage element 20_1 is connected to the connection terminal 71a. Or switch 2
For example, 1a has a function of selecting whether or not the storage element 20_1 is connected to the connection terminal 72a. Similarly, the switch 21 b may, for example, connect the storage element 20 _ 1 to a connection terminal 7.
It has a function to select whether to connect or not to 1b. Or, the switch 21b is
For example, the storage element 20_1 has a function of selecting whether to connect or not to the connection terminal 72b. Alternatively, the switch 21a has a function of, for example, not connecting the storage element 20_1 to any terminal. Similarly, the switch 21b is, for example, a storage element 20_1.
It has a function to prevent connection to any terminal.

The switches 22a and 22b have, for example, a function of selecting whether to connect the storage element 20_2 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a and the connection terminal 72b. Alternatively, the switch 22a has a function of, for example, selecting whether the storage element 20_2 is connected to the connection terminal 71a or not. Or switch 2
For example, 2a has a function of selecting whether or not the storage element 20_2 is connected to the connection terminal 72a. Similarly, the switch 22 b may, for example, connect the storage element 20 _ 2 to a connection terminal 7.
It has a function to select whether to connect or not to 1b. Or, the switch 22b is
For example, it has a function of selecting whether or not the storage element 20_2 is connected to the connection terminal 72a. Alternatively, the switch 22a has a function of, for example, not connecting the storage element 20_2 to any terminal. Similarly, the switch 22 b is, for example, a storage element 20_2.
It has a function to prevent connection to any terminal.

It should be noted that when the switch "connects" A and B and "does not connect", the switch
It may be used in the sense of “make conductive” and “make conductive” between A and B. Alternatively, the wording that the switch "connects" A and B and "does not connect" means that the switch is "conductive (on)""nonconductive(off)" It may be used in the sense of.

The switch 51 has a function of selecting whether or not to connect at least one of the storage element 10_1 and the storage element 10_2 and at least one of the storage element 20_1 and the storage element 20_2 in series connection.

The switch 61 has a function of selecting whether or not to connect at least one of the storage element 10_1 and the storage element 10_2 and at least one of the storage element 20_1 and the storage element 20_2 in series connection.

Note that the number of storage elements and switches is not limited to FIG. For example, as shown in FIG. 2, the number of storage elements and switches may be increased, and a plurality of storage elements may be provided and a switch may be provided for each of the storage elements. The configuration of the storage system shown in FIG. 2 will be described below. In the configurations shown in FIG. 1 and FIG. 2, the description of each other may be used as appropriate for each other in common with each other.

The storage system illustrated in FIG. 2 includes storage elements 10_1 to 10_3 and storage elements 20_.
1 to the storage element 20_3, the storage element 30_1 to the storage element 30_3, a pair of switches 11 (switches 11a and 11b), a pair of switches 12 (switches 12a and 12b), and a pair of switches 13 (switches 13a and 13b) Switch 13b),
A pair of switches 21 (switches 21a and 21b), a pair of switches 22 (switches 22a and 22b), a pair of switches 23 (switches 23a and 23b), and a pair of switches 31 (switches 31a and 31b) , A pair of switches 32 (switches 32a and 32b), and a pair of switches 33 (switches 3)
3a and switch 33b), switch 51, switch 52, switch 61, switch 62, pair of connection terminals 71 (connection terminal 71a and connection terminal 71b), and pair of connection terminals 72 (connection terminal 72a and connection terminals And 72b).

The storage elements 10_1 to 10_3 are provided in the cell 100_1. Storage element 20
The _1 to the storage element 20_3 are provided in the cell 100_2. The storage elements 30_1 to 30_3 are provided in the cell 100_3. A storage element is an element having at least a pair of electrodes and an electrolyte and having a function capable of storing electricity. Note that the storage element may be a storage device. Alternatively, one cell may be one power storage device or battery cell. Alternatively, one cell may be one assembled battery.

The storage elements 10_1 to 10_3, the storage elements 20_1 to 20_3, and the storage elements 30_1 to 30_3 include, for example, lithium ion secondary batteries, lead storage batteries, lithium ion polymer secondary batteries, nickel hydrogen storage batteries, nickel cadmium Storage batteries, nickel-iron storage batteries, nickel-zinc storage batteries, secondary batteries such as silver oxide-zinc storage batteries, redox flow batteries, zinc-chlorine batteries, liquid circulation type secondary batteries such as zinc-bromine batteries, aluminum-air batteries, A mechanically charged secondary battery such as an air zinc battery, an air / iron battery, a high temperature operation secondary battery such as a sodium / sulfur battery, or a lithium / iron sulfide battery can be used. Note that without limitation thereto, the power storage elements 10_1 to 10_3, the power storage elements 20_1 to 20_3, and the power storage elements 30_1 to 30_3 may be formed using, for example, lithium ion capacitors.

The switch 11a, the switch 11b, the switch 12a, the switch 12b, the switch 13a,
Switch 13b, switch 21a, switch 21b, switch 22a, switch 22b,
The switch 23a, the switch 23b, the switch 31a, the switch 31b, the switch 32a,
Each of the switch 32b, the switch 33a, and the switch 33b has at least three types of terminals (referred to as a first terminal, a second terminal, and a third terminal). For example, a plurality of transistors may be used to form a switch having three types of terminals. In addition, a switch having three types of terminals may be configured using a micro-electro-mechanical system (also referred to as MEMS) or the like. Alternatively, other electrical switches or mechanical switches may be used.

The first terminal of the switch 11a is connected to the positive electrode of the storage element 10_1, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 12a, the third terminal of the switch 13a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 11b is connected to the negative electrode of the storage element 10_1, the second terminal is connected to the connection terminal 71b, and the third terminal is the third terminal of the switch 12b and the third terminal of the switch 13b.
Connected to terminal.

For example, the switch 11a and the switch 11b have a function of selecting whether to connect the storage element 10_1 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a.

The first terminal of the switch 12a is connected to the positive electrode of the storage element 10_2, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 11a, the third terminal of the switch 13a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 12b is connected to the negative electrode of the storage element 10_2, the second terminal is connected to the connection terminal 71b, and the third terminal is a third terminal of the switch 11b and the third terminal of the switch 13b.
Connected to terminal.

The switches 12a and 12b have a function of, for example, selecting whether to connect the storage element 10_2 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a.

The first terminal of the switch 13a is connected to the positive electrode of the storage element 10_3, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 11a, the third terminal of the switch 12a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 13b is connected to the negative electrode of the storage element 10_3, the second terminal is connected to the connection terminal 71b, and the third terminal is a third terminal of the switch 11b and the third terminal of the switch 12b.
Connected to terminal.

The switches 13a and 13b have a function of selecting, for example, whether the storage element 10_3 is connected to the connection terminal 71a and the connection terminal 71b or connected to the connection terminal 72a.

The first terminal of the switch 21a is connected to the positive electrode of the storage element 20_1, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 22a, the third terminal of the switch 23a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 21b is connected to the negative electrode of the storage element 20_1, the second terminal is connected to the connection terminal 71b, and the third terminal is a third terminal of the switch 22b and the third terminal of the switch 23b.
Connected to terminal.

The switches 21a and 21b have a function of selecting, for example, whether the storage element 20_1 is connected to the connection terminal 71a and the connection terminal 71b or to the connection terminal 72a.

The first terminal of the switch 22a is connected to the positive electrode of the storage element 20_2, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 21a, the third terminal of the switch 23a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 22b is connected to the negative electrode of the storage element 20_2, the second terminal is connected to the connection terminal 71b, and the third terminal is a third terminal of the switch 21b and the third terminal of the switch 23b.
Connected to terminal.

For example, the switch 22a and the switch 22b have a function of selecting whether to connect the storage element 20_2 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a.

The first terminal of the switch 23a is connected to the positive electrode of the storage element 20_3, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 21a, the third terminal of the switch 22a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 23b is connected to the negative electrode of the storage element 20_3, the second terminal is connected to the connection terminal 71b, and the third terminal is a third terminal of the switch 21b and the third terminal of the switch 22b.
Connected to terminal.

The switch 23a and the switch 23b have a function of selecting, for example, whether the storage element 20_3 is connected to the connection terminal 71a and the connection terminal 71b or connected to the connection terminal 72a.

The first terminal of the switch 31a is connected to the positive electrode of the storage element 30_1, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 32a, the third terminal of the switch 33a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 31b is connected to the negative electrode of the storage element 30_1, the second terminal is connected to the connection terminal 71b, and the third terminal is the third terminal of the switch 32b, the third terminal of the switch 33b, and the connection It is connected to the terminal 72b.

For example, the switch 31a and the switch 31b have a function of selecting whether to connect the storage element 30_1 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a and the connection terminal 72b.

The first terminal of the switch 32a is connected to the positive electrode of the storage element 30_2, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 31a, the third terminal of the switch 33a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 32b is connected to the negative electrode of the storage element 30_2, the second terminal is connected to the connection terminal 71b, and the third terminal is the third terminal of the switch 31b, the third terminal of the switch 33b, and the connection It is connected to the terminal 72b.

For example, the switch 32a and the switch 32b have a function of selecting whether to connect the storage element 30_2 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a and the connection terminal 72b.

The first terminal of the switch 33a is connected to the positive electrode of the storage element 30_3, the second terminal is connected to the connection terminal 71a, and the third terminal is the third terminal of the switch 31a, the third terminal of the switch 32a, and the connection It is connected to the terminal 72a.

The first terminal of the switch 33b is connected to the negative electrode of the storage element 30_3, the second terminal is connected to the connection terminal 71b, and the third terminal is the third terminal of the switch 31b, the third terminal of the switch 32b, and the connection It is connected to the terminal 72b.

For example, the switch 33a and the switch 33b have a function of selecting whether to connect the storage element 30_3 to the connection terminal 71a and the connection terminal 71b or to connect the connection terminal 72a and the connection terminal 72b.

Each of the switches 51 and 52 has at least two types of terminals (referred to as a first terminal and a second terminal). For example, a transistor may be used to form a switch having two types of terminals. In addition, a micro-electro-mechanical system or the like may be used to configure a switch having two types of terminals.

The first terminal of the switch 51 is connected to the third terminals of the switches 11 b to 13 b,
The second terminal is connected to the third terminals of the switches 21a to 23a.

The switch 51 has a function of selecting whether or not to connect at least one of the storage elements 10_1 to 10_3 and at least one of the storage elements 20_1 to 30_3 in series connection.

The first terminal of the switch 52 is connected to the third terminals of the switches 21b to 23b,
The second terminal is connected to the third terminals of the switches 31a to 33a.

The switch 52 has a function of selecting whether or not to connect at least one of the storage elements 20_1 to 20_3 and at least one of the storage elements 30_1 to 30_3 in series connection.

Each of the switch 61 and the switch 62 has at least two types of terminals (referred to as a first terminal and a second terminal). For example, a transistor may be used to form a switch having two types of terminals. In addition, a switch having two types of terminals may be configured using a micro-electro-mechanical system or the like.

The first terminal of the switch 61 is connected to the connection terminal 72a, and the second terminal is connected to the third terminals of the switches 21a to 23a.

The switch 61 has a function of selecting whether to connect the connection terminal 72a and at least one of the power storage elements 20_1 to 20_3.

The first terminal of the switch 62 is connected to the connection terminal 72a, and the second terminal is connected to the third terminals of the switches 31a to 33a.

The switch 62 has a function of selecting whether to connect the connection terminal 72a and at least one of the power storage elements 30_1 to 30_3.

Note that although an example in which a plurality of power storage elements are provided is shown as an example, one aspect of the embodiment of the present invention is not limited to this. Depending on the situation, or in some cases, the storage element may not necessarily be provided.

[1.2. Driving method]
Next, an example of a method of driving the storage system shown in FIG. 2 will be described as an example of a method of driving the storage system with reference to FIGS. 3 to 6. In addition, in FIG. 3 thru | or FIG. 6 for convenience, the connection terminal 71a
The connection terminal 71 b is connected to the power supply 91, and the connection terminal 72 a and the connection terminal 72 b are connected to the load 92.
The case of connecting to will be described.

[1.2.1. Driving method 1]
An example of a driving method in the case of performing charging or discharging will be described with reference to FIGS. 3 and 4.

When the storage elements 10_1 to 10_3, the storage elements 20_1 to 20_3, and the storage elements 30_1 to 30_3 are charged, as shown in FIG.
1a to switch 13a, switch 11b to switch 13b, switch 21a to switch 23a, switch 21b to switch 23b, switch 31a to switch 33a,
A storage element 10_1 to a storage element 10_3, a storage element 20_1 to a storage element 20_3, and a storage element 30_1 to a storage element 30_3 are provided by the switches 31b to 33b,
The power supply 91 is connected in parallel connection. Further, the switch 51 and the switch 52 are turned off. The switch 61 and the switch 62 may be on or off.

At this time, power storage elements 10_1 to 10_3 and power storage elements 20_1 to 20
_3, and each of the storage elements 30_1 to 30_3 are charged. Storage element 1
0_1 to storage element 10_3, storage element 20_1 to storage element 20_3, and storage element 3
Since each of 0_1 to the storage element 30_3 is connected in parallel connection, each storage element can be charged. When charging a power storage device in which a plurality of power storage elements are connected in series,
If the resistance value of each storage element is different, each storage element is charged based on the voltage of the storage element having the highest resistance value, and the problem arises that all of the plurality of storage elements can not be sufficiently charged. Such a problem does not occur in the driving method of the present embodiment. Thus, for example, the safety of the storage element can be enhanced.

When discharging the storage elements 10_1 to 10_3, the storage elements 20_1 to 20_3, and the storage elements 30_1 to 30_3, as shown in FIG.
The switch 51 and the switch 52 are turned on, and the switch 61 and the switch 62 are turned off. Furthermore, the switches 11 a to 13 a and the switches 11 b to 1
3b, switches 21a to 23a, switches 21b to 23b, switches 31a to 33a, and switches 31b to 33b, respectively.
_1 to storage element 10_3, storage element 20_1 to storage element 20_3, and storage element 30
, And the load 92 are connected in series.

At this time, power storage elements 10_1 to 10_3 and power storage elements 20_1 to 20
Each of the storage element 30_1 to the storage element 30_3 is discharged, and a current flows in the load 92. A storage element 10_1 to a storage element 10_3, a storage element 20_1 to a storage element 2
Since 0_3 and the storage elements 30_1 to 30_3 are connected in series, the amount of current supplied to the load 92 can be increased.

[1.2.2. Driving method 2]
In the driving method for discharging described with reference to FIG. 4, the case of discharging all the storage elements has been described. However, the present invention is not limited to this. Only some of the storage elements may be discharged.

For example, as shown in FIG. 5, the switch 51 is turned off, the switch 52 is turned on, the switch 61 is turned on, and the switch 62 is turned off. Furthermore, the switch 11
The switches 31a to 33a and the switches 31b to 33b do not discharge the power storage elements 10_1 to 10_3 by the switches a to 13a, the switches 11b to 13b, the switches 21a to 23a, and the switches 21b to 23b. The storage elements 20_1 to 20_3 and the storage elements 30_1 to 30_3 may be electrically connected in series and discharged. As a result, the current flowing to the load 92 can be appropriately changed without providing a voltage conversion circuit such as a converter.

[1.2.3. Driving method 3]
Although the driving method described with reference to FIGS. 3 and 4 has described the case of charging or discharging all the storage elements, the present invention is not limited thereto, and some of the storage elements are charged and the remaining storage elements are You may discharge it.

For example, as shown in FIG. 6, the switch 12a and the switch 12b store the storage element 10_2.
And the power supply 91 are connected in parallel, and the storage element 20_2 and the power supply 91 are connected in parallel connection by the switch 22a and the switch 22b, and the storage element 30_2 and the power supply 91 by the switch 32a and the switch 32b. Storage element 10 by connecting in parallel connection.
_2, the storage element 20_2, and the storage element 30_2 are charged. On the other hand, the switch 51 and the switch 52 are turned on, and the switch 61 and the switch 62 are turned off. further,
The switch 11a, the switch 11b, the switch 13a, the switch 13b, the switch 21a,
The switch 21b, the switch 23a, the switch 23b, the switch 31a, the switch 31b,
The storage element 10_1, the storage element 10_3, the storage element 20_1, the storage element 20_3, the storage element 30_1, and the storage element 30_3 and the load 92 are connected in series connection by the switch 33a and the switch 33b. Element 10_3, Storage Element 20_
1. The storage element 20_3, the storage element 30_1, and the storage element 30_3 may be discharged.
Note that storage elements to be charged include the storage element 10_2, the storage element 20_2, and the storage element 30_
For example, the storage element to be charged by the switches 11a to 13a, the switches 11b to 13b, the switches 21a to 23a, the switches 21b to 23b, the switches 31a to 33a, and the switches 31b to 33b can be used. You may switch in order.

As described with reference to FIG. 6, since it is possible to charge other storage elements while discharging some storage elements, it is not necessary to provide an operation stop period of the storage system for charging. Therefore, the operation can be made faster.

Second Embodiment Control system of power storage device]
An example of a control system of a power storage device which can be used for a power storage system which is one embodiment of the present invention is described. Note that, for the same portions as the descriptions of the power storage system described with reference to FIGS. 1 to 6, the description can be appropriately employed.

[2.1. Constitution]
An example of a control system of the power storage device will be described with reference to FIG.

The circuit 200 shown in FIG. 7 includes a pair of switches 11 (switches 11 a and 11 b), a pair of switches 12 (switches 12 a and 12 b), and a pair of switches 21 (
The switch 21a and the switch 21b), the pair of switches 22 (the switch 22a and the switch 22b), the switch 51, the switch 61, the encoder 240, the current detection circuit 245, the semiconductor circuit 246, and the pair of connection terminals 201 ( Connection terminal 201a and connection terminal 201b), pair of connection terminals 202 (connection terminal 202a and connection terminal 202b) pair of connection terminals 203 (connection terminal 203a and connection terminal 203b) pair of connection terminals 204 (connection terminal 204a and connection terminal 204b) A pair of connection terminals 71 (connection terminals 71a and connection terminals 7)
1b) A pair of connection terminals 72 (connection terminals 72a and connection terminals 72b) are provided. Note that the circuit 200 may be a control system, a controller, or a circuit board. The circuit 200 and the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_2 are combined to form a storage system. In addition, the circuit 20 is connected through the connection terminal 71a and the connection terminal 71b.
0 may be connected to the power supply. Alternatively, the circuit 2 can be connected via the connection terminal 72a and the connection terminal 72b.
00 may be connected to the load. Note that the voltage output to the load is used to
VSS) may be generated and input to the circuit 200. Although an example of controlling four power storage elements is described in the circuit 200, the present invention is not limited to this. For example, as shown in FIG. 2, the number of power storage elements may be more than four.

The switch 11a, the switch 11b, the switch 12a, the switch 12b, the switch 21a,
Specific examples of the switch 21b, the switch 22a, and the switch 22b are shown in FIG.

The switch illustrated in FIG. 8 includes three input / output terminals (also referred to as input / output terminals IOa to IOc) and two control terminals (also referred to as control terminals CTL_1 and control terminal CTL_2).
Have.

Further, the switch illustrated in FIG. 8 includes a transistor 251 and a transistor 252.

One of the source and the drain of the transistor 251 is connected to the input / output terminal IOa, and the other is connected to the input / output terminal IOb. The gate of transistor 251 has a control terminal CTL_.
It is electrically connected to 1.

One of the source and the drain of the transistor 252 is connected to the input / output terminal IOa, and the other is connected to the input / output terminal IOc. The gate of transistor 252 has a control terminal CTL_
It is electrically connected to 2.

The switch illustrated in FIG. 8 controls the conduction state of the source and the drain of the transistor 251 and the conduction state of the source and the drain of the transistor 252 according to the control signal.
The connection between the input / output terminal IOa and the input / output terminal IOb and the connection between the input / output terminal IOa and the input / output terminal IOc can be selected.

Note that by controlling the potentials of the control terminal CTL_1 and the control terminal CTL_2, both of the transistor 251 and the transistor 252 can be turned off.

Note that by providing transistors of different polarities in parallel with the transistor 251,
It is also possible to use a CMOS configuration. Similarly, a CMOS configuration is also possible by providing transistors of different polarities in parallel with the transistor 252.

The above is the specific example of the switch.

The control signal CTL1 from the encoder 240 is input to the control terminal CTL_1 of the switch 11a and the control terminal CTL_1 of the switch 11b, and the inverted signal of the control signal CTL1 from the inverter 241_1 is input to the control terminal CTL_2.

The input / output terminal IOa of the switch 11a is connected to the connection terminal 201a. Thus, the input / output terminal IOa of the switch 11a can be connected to the positive electrode of the storage element 10_1 through the connection terminal 201a. The input / output terminal IOb of the switch 11a is connected to the connection terminal 71a, and the input / output terminal IOc is connected to the connection terminal 72a via the resistance element 244.

The input / output terminal IOa of the switch 11b is connected to the connection terminal 201b. Accordingly, the input / output terminal IOa of the switch 11b can be connected to the negative electrode of the storage element 10_1 through the connection terminal 201b. The input / output terminal IOb of the switch 11b is connected to the connection terminal 71b, and the input / output terminal IOc is connected to one of the source and the drain of the transistor included in the switch 51.

The control signal CTL2 from the encoder 240 is input to the control terminal CTL_1 of the switch 12a and the control terminal CTL_1 of the switch 12b, and the inverted signal of the control signal CTL2 from the inverter 241_2 is input to the control terminal CTL_2.

The input / output terminal IOa of the switch 12a is connected to the connection terminal 202a. Thus, the input / output terminal IOa of the switch 12a can be connected to the positive electrode of the storage element 10_2 through the connection terminal 202a. The input / output terminal IOb of the switch 12a is connected to the connection terminal 71a, and the input / output terminal IOc is connected to the connection terminal 72a via the resistance element 244.

The input / output terminal IOa of the switch 12b is connected to the connection terminal 202b. Thus, the input / output terminal IOa of the switch 12b can be connected to the negative electrode of the storage element 10_2 through the connection terminal 202b. The input / output terminal IOb of the switch 12b is connected to the connection terminal 71b, and the input / output terminal IOc is connected to one of the source and the drain of the transistor included in the switch 51.

The control signal CTL3 from the encoder 240 is input to the control terminal CTL_1 of the switch 21a and the control terminal CTL_1 of the switch 21b, and the inverted signal of the control signal CTL3 from the inverter 241_3 is input to the control terminal CTL_2.

The input / output terminal IOa of the switch 21a is connected to the connection terminal 203a. Thus, the input / output terminal IOa of the switch 21a can be connected to the positive electrode of the storage element 20_1 through the connection terminal 203a. The input / output terminal IOb of the switch 21a is connected to the connection terminal 71a, the input / output terminal IOc is connected to the connection terminal 72a via the resistance element 244, and is connected to the other of the source and drain of the transistor of the switch 51. .

The input / output terminal IOa of the switch 21b is connected to the connection terminal 203b. Thus, the input / output terminal IOa of the switch 21b can be connected to the negative electrode of the storage element 20_1 through the connection terminal 203b. The input / output terminal IOb of the switch 21b is connected to the connection terminal 71b, and the input / output terminal IOc is connected to the connection terminal 72b.

The control signal CTL4 from the encoder 240 is input to the control terminal CTL_1 of the switch 22a and the control terminal CTL_1 of the switch 22b, and an inverted signal of the control signal CTL4 from the inverter 241_4 is input to the control terminal CTL_2.

The input / output terminal IOa of the switch 22a is connected to the connection terminal 204a. Thus, the input / output terminal IOa of the switch 22a can be connected to the positive electrode of the storage element 20_2 via the connection terminal 204a. The input / output terminal IOb of the switch 22a is connected to the connection terminal 71a, and the input / output terminal IOc is connected to the connection terminal 72a via the resistance element 244.

The input / output terminal IOa of the switch 22b is connected to the connection terminal 204b. Accordingly, the input / output terminal IOa of the switch 22b can be connected to the negative electrode of the storage element 20_2 through the connection terminal 204b. The input / output terminal IOb of the switch 22b is connected to the connection terminal 71b, and the input / output terminal IOc is connected to the connection terminal 72b.

One of the source and drain of the transistor of the switch 51 is connected to the input / output terminal IOc of the switch 11b and the input / output terminal IOc of the switch 12b, and the other is the input / output terminal IOc of the switch 21a and the input / output of the switch 22a Connected to terminal IOc. The potential of the gate of the transistor included in the switch 51 is controlled by the logic circuit 243. The output of the logic circuit 243 corresponds to the logical sum of the potential of the control signal CTL1 and the potential of the control signal CTL2. Therefore, in accordance with the potential of control signal CTL1 and the potential of control signal CTL2, switch 5
The conduction state of 1 is controlled. The logic circuit 243 is configured using, for example, an OR circuit.

One of the source and drain of the transistor of the switch 61 is connected to the input / output terminal IOc of the switch 11a and the input / output terminal IOc of the switch 12a, and the other is the input / output terminal IOc of the switch 21a and the input / output of the switch 22a Connected to terminal IOc. The potential of the gate of the transistor included in the switch 61 is controlled by the logic circuit 247. The output of the logic circuit 247 corresponds to the logical sum of the potential of the inverted signal of the control signal CTL1 and the potential of the inverted signal of the control signal CTL2. Therefore, the potential of the inverted signal of control signal CTL1 and control signal C
The conduction state of the switch 61 is controlled in accordance with the potential of the inverted signal of TL2. Logic circuit 247
Are configured using, for example, an OR circuit.

The encoder 240 has a function of generating and outputting the control signals CTL1 to CTL4 by encoding a plurality of data signals input from the semiconductor circuit 246.

The current detection circuit 245 detects the potentials at both ends of the resistance element 244, and inputs each potential as a detection signal to the comparison circuit to determine whether the current flowing in the resistance element 244 is larger than the reference value. Have the ability to

The semiconductor circuit 246 has a function of generating and outputting a plurality of data signals including an instruction instructing charging or discharging of a storage element. The semiconductor circuit 246 may exchange signals with an external circuit such as a load, for example. The semiconductor circuit 246 may be, for example, a microcomputer, a microprocessor (also referred to as MPU), a micro control unit (MC).
U), field programmable gate array (also called FPGA), central processing unit (also called CPU), or battery management unit (also called BMU)
It may be

The switches of the circuit 200 (for example, the switch 11a, the switch 11b, and the switch 12a)
, Switch 12b, switch 21a, switch 21b, switch 22a, switch 22b
As a transistor that can be used for the switch 51, the switch 61, and the like, a transistor with low off current may be applied. For example, a transistor having a channel formation region including an oxide semiconductor having a wider band gap than silicon and having a substantially i-type channel formation region can be used as the transistor having low off-state current. In addition, it is not limited to the circuit 200, For example, switch 31a shown in FIG. 2, switch 31b, switch 3
2a, switch 32b, switch 33a, switch 33b, switch 52, switch 62
Alternatively, the above transistor with low off current may be used. The present invention is not limited to this, and for example, the switch may be configured using a semiconductor having silicon.

For example, a transistor including the above oxide semiconductor can be manufactured by removing impurities such as hydrogen or water as much as possible and supplying oxygen to reduce oxygen vacancies as much as possible.
At this time, secondary ion mass spectrometry (SIMS (Second
It is preferable to reduce the amount of hydrogen referred to as donor impurity in the measured value of ary Ion Mass Spectrometry) to 1 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁸ / cm ³ or less. The off-state current of the transistor is 1 per μm of channel width at 25 ° C.
X ^10-19 A (100 zA) or less. More preferably, 1 × 10 ^-22 A (100 y
A) It is below. The lower the off-state current of the transistor, the better, but the lower limit of the off-state current of the transistor is estimated to be about 1 × 10 ^-30 A / μm.

As the oxide semiconductor, an In-based metal oxide, a Zn-based metal oxide, an In-Zn-based metal oxide, an In-Ga-Zn-based metal oxide, or the like can be used, for example.

Here, an example of the semiconductor circuit 246 will be described with reference to FIG.

The semiconductor circuit 246 illustrated in FIG. 9 includes a processor 710, a bus bridge 711, and a memory 712.
, Memory interface 713, controller 720, interrupt controller 721,
It has an I / O interface (input / output interface) 722 and a power gate unit 730.

Further, the semiconductor circuit 246 includes a crystal oscillation circuit 741, a timer circuit 745, an I / O interface 746, an I / O port 750, a comparator 751, an I / O interface 752, a bus line 761, a bus line 762, a bus line 763, and A data bus line 764 is provided. Further, the semiconductor circuit 246 includes at least connection terminals 770 to 776 as connection portions with external devices. Note that each connection terminal 770 to connection terminal 77
6 represents a terminal group consisting of one terminal or a plurality of terminals. In addition, an oscillator 742 having a crystal oscillator 743 is connected to the semiconductor circuit 246 through the connection terminal 772 and the connection terminal 773.

The processor 710 has a register 785, and the bus line 76 via the bus bridge 711.
1 to the bus line 763 and the data bus line 764.

The memory 712 is a storage device that can function as a main memory of the processor 710, and for example, a random access memory is used. Memory 712 is a processor 71
0 is a device for storing an instruction to be executed, data necessary for the execution of the instruction, and data by the processing of the processor 710. Data is written to and read from the memory 712 according to an instruction processed by the processor 710. For example, the semiconductor circuit 246 may generate a data signal in accordance with an instruction instructing connection of each storage element and output the data signal through the I / O port 750.

In the semiconductor circuit 246, the power supply to the memory 712 is cut off in the low power consumption mode. Therefore, it is preferable that the memory 712 be configured as a memory that can hold data even when power is not supplied.

The memory interface 713 is an input / output interface with an external storage device. Data is written to and read from an external storage device connected to the connection terminal 776 through the memory interface 713 in accordance with an instruction processed by the processor 710.

The clock generation circuit 715 is a circuit that generates a clock signal MCLK (hereinafter, also simply referred to as “MCLK”) used in the processor 710, and includes an RC oscillator and the like. MC
LK is also output to the controller 720 and the interrupt controller 721.

The controller 720 is a circuit that controls the semiconductor circuit 246, and, for example, the semiconductor circuit 2
The power supply control of 46, the control of the clock generation circuit 715, the crystal oscillation circuit 741, and the like can be performed.

The connection terminal 770 is a terminal for external interrupt signal input, and the non-maskable interrupt signal NMI is input to the controller 720 through the connection terminal 770. Controller 72
When the non-maskable interrupt signal NMI is input to 0, the controller 720 immediately outputs the non-maskable interrupt signal NMI 2 to the processor 710 to cause the processor 710 to execute interrupt processing.

In addition, the interrupt signal INT is input to the interrupt controller 721 through the connection terminal 770. The interrupt controller 721 receives an interrupt signal (T0IRQ) from a peripheral circuit.
, P0IRQ and C0IRQ) are also input without passing through the buses (761 to 764).

The interrupt controller 721 has a function of assigning priorities of interrupt requests. When the interrupt controller 721 detects an interrupt signal, the interrupt controller 721 determines whether the interrupt request is valid. If it is a valid interrupt request, interrupt signal IR to controller 720
Output Q

Also, the interrupt controller 721 is connected to the bus line 761 and the data bus line 764 via the I / O interface 722.

When the controller 720 receives the interrupt signal INT, the controller 720 outputs an interrupt signal INT2 to the processor 710 to cause the processor 710 to execute interrupt processing.

In addition, the interrupt signal T0IRQ may be directly input to the controller 720 without passing through the interrupt controller 721. When the interrupt signal T0IRQ is input, the controller 720 outputs an unmaskable interrupt signal NMI2 to the processor 710 to cause the processor 710 to execute interrupt processing.

The register 780 of the controller 720 is provided in the controller 720, and the register 786 of the interrupt controller 721 is provided in the I / O interface 722.

Subsequently, peripheral circuits included in the semiconductor circuit 246 will be described. The semiconductor circuit 246 includes a timer circuit 745, an I / O port 750, and a comparator 751 as peripheral circuits. These peripheral circuits are one example, and necessary circuits can be provided depending on an electric device in which the semiconductor circuit 246 is used.

Timer circuit 745 outputs clock signal TCLK (outputted from clock generation circuit 740).
Hereinafter, it is also simply referred to as "TCLK". ) Has a function of measuring time. The timer circuit 745 may be provided with a plurality of timer circuits. Also, the timer circuit 745 can output the interrupt signal T0IRQ to the controller 720 and the interrupt controller 721 at a determined time interval. The timer circuit 745 is connected to the bus line 761 and the data bus line 764 via the I / O interface 746. For example, the timer circuit 745 has a function of being able to control the charge time or discharge time of the storage element.

TCLK is a clock signal of lower frequency than MCLK. For example, the frequency of MCLK is set to several MHz (for example, 8 MHz), and TCLK is set to several tens kHz (for example, 32).
kHz). The clock generation circuit 740 includes a crystal oscillation circuit 741 incorporated in the semiconductor circuit 246, and an oscillator 742 connected to the connection terminal 772 and the connection terminal 773. A quartz oscillator 743 is used as an oscillator of the oscillator 742. Note that by configuring the clock generation circuit 740 with a CR oscillator or the like, all the modules of the clock generation circuit 740 can be incorporated in the semiconductor circuit 246.

The I / O port 750 is an interface for inputting and outputting information with an external device connected via the connection terminal 774, and is an input / output interface for digital signals. For example, the I / O port 750 receives the interrupt signal P0IRQ in response to the input digital signal.
Are output to the interrupt controller 721. The I / O port 750 is connected to the encoder 240 and the current detection circuit 245 shown in FIG. Thereby, a data signal can be output to the encoder 240. Further, a detection signal is input from the current detection circuit 245. Note that a plurality of connection terminals 774 may be provided.

The comparator 751 can compare, for example, the magnitude of the potential (or current) of an analog signal input from the connection terminal 775 with the potential (or current) of a reference signal, and can generate a digital signal having a value of 0 or 1 . Furthermore, the comparator 751 responds to the digital signal by
An interrupt signal C0IRQ can be generated. The interrupt signal C0IRQ is output to the interrupt controller 721.

The I / O port 750 and the comparator 751 are connected to the bus line 761 and the data bus line 764 via a common I / O interface 752. Here, I / O
Although there is a circuit that can be shared by the I / O interface of each of the port 750 and the comparator 751, the I / O interface 750 of the I / O port 750 and the comparator 751 It can also be provided separately.

In addition, the registers of the peripheral circuits are provided in the corresponding input / output interface. The register 787 of the timer circuit 745 is provided in the I / O interface 746, and the register 783 of the I / O port 750 and the register 784 of the comparator 751 are I, respectively.
/ O interface 752 is provided.

The semiconductor circuit 246 is a power gate unit 730 for interrupting power supply to internal circuits.
Have. By supplying power only to circuits necessary for operation by the power gate unit 730, power consumption of the semiconductor circuit 246 can be reduced.

As shown in FIG. 9, a unit 701 enclosed by a two-dot chain line in the semiconductor circuit 246, a unit 7
The circuits of the unit 02 and the unit 703 and the unit 704 are connected to the connection terminal 771 via the power gate unit 730.

In the present embodiment, unit 701 includes timer circuit 745 and I / O interface 746, and unit 702 includes I / O port 750, comparator 751, and I.
Unit 703 includes an interrupt controller 721, and an I / O interface 752.
And I / O interface 722, unit 704 includes processor 710, memory 712, bus bridge 711, and memory interface 713.

The power gate unit 730 is controlled by the controller 720. The power gate unit 730 has a switch 731 and a switch 732 for interrupting the supply of the power supply voltage to the units 701 to 704. As the power supply voltage at this time, for example, the power supply voltage of the control system can be used.

The on / off of the switch 731 and the switch 732 is controlled by the controller 720.
Specifically, the controller 720 outputs a signal to turn off part or all of the switches included in the power gate unit 730 according to the request of the processor 710 (power supply stop). In addition, the controller 720 is triggered by the non-maskable interrupt signal NMI or the interrupt signal T0IRQ from the timer circuit 745 to generate the power gate unit 7.
Output a signal to turn on the switch of 30 (start of power supply).

Although FIG. 9 shows a configuration in which two switches (a switch 731 and a switch 732) are provided in the power gate unit 730, the present invention is not limited to this. .

Further, in this embodiment, switch 731 is provided to control power supply to unit 701 independently, and switch 732 is provided to control power supply to unit 702 to unit 704 independently. However, the present invention is not limited to such a power supply path. For example, a switch different from the switch 732 may be provided so that the power supply of the memory 712 can be controlled independently. Also, 1
A plurality of switches may be provided for one circuit.

Further, the power supply voltage is always supplied to the controller 720 from the connection terminal 771 without passing through the power gate unit 730. Further, in order to reduce the influence of noise, power supply potentials are supplied to the oscillation circuit of the clock generation circuit 715 and the crystal oscillation circuit 741 from an external power supply circuit different from the power supply circuit of the power supply voltage.

By including the controller 720 and the power gate unit 730, the semiconductor circuit 246 can be operated in three operation modes. The first operation mode is a normal operation mode, in which all the circuits of the semiconductor circuit 246 are in an active state. Here, the first operation mode is referred to as “active mode”.

The second and third operation modes are low power consumption modes and modes in which some circuits are activated. In the second mode of operation, the controller 720 as well as the timer circuit 745
And their associated circuits (crystal oscillator circuit 741, I / O interface 746) are active. In the third mode of operation, only controller 720 is active. here,
The second operation mode is called “Noff1 mode”, and the third operation mode is called “Noff2 mode”. In Noff1 mode, controller 720 and part of peripheral circuits (
Circuits necessary for timer operation are operating, and in the Noff2 mode, only the controller 720 is operating.

Note that power is always supplied to the oscillator of the clock generation circuit 715 and the crystal oscillation circuit 741 regardless of the operation mode. To deactivate the clock generation circuit 715 and the crystal oscillation circuit 741, input an enable signal from the controller 720 or externally.
This is performed by stopping the oscillation of the clock generation circuit 715 and the crystal oscillation circuit 741.

Also, in the Noff1 and Noff2 modes, since the power supply is cut off by the power gate unit 730, the I / O port 750 and the I / O interface 752 become inactive but external devices connected to the connection terminal 774 I to work properly
Power is supplied to part of the / O port 750 and the I / O interface 752. Specifically, the output buffer of the I / O port 750 and the register 783 for the I / O port 750 are used.

In this specification, in the inactive state of a circuit, in addition to the state in which the supply of power is cut off and the circuit is stopped, the state in which the main functions in the Active mode (normal operation mode) are stopped. And, including the state of operating with less power than Active mode.

With the above configuration, for example, when the user forcibly terminates the charging operation of the power storage device, a signal is output to turn off part or all of the switches of the power gate unit 730 at the request of the processor 710. It is also possible to switch to the Noff1 and Noff2 modes and stop the supply of power to unnecessary circuit blocks.

[2.2. Driving method]
Furthermore, an operation example of the control system will be described with reference to an example of the method of driving the storage system.

When charging one or more storage elements, the potential of the control signals CTL1 to CTL4 is set by the encoder 240 to connect the positive electrode and the negative electrode of the storage elements to be charged.
Connect to a and the connection terminal 71b.

For example, the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_
In the case of charging 2, the transistors 251 included in the switches 11a, 11b, 12a, 12b, 21a, 21b, 22a, and 22b are turned on by the control signals CTL1 to CTL4. The transistor 252 is turned off. Further, the transistor included in the switch 51 is turned off.

At this time, storage element 10_1, storage element 10_2, storage element 20_1, and storage element 20
Since _2, the connection terminal 71a, and the connection terminal 71b are in a conductive state, the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_2 are charged through the connection terminal 71a and the connection terminal 71b.

When discharging one or more storage elements, the potentials of the control signals CTL1 to CTL4 are set by the encoder 240 to connect the positive and negative electrodes of the storage elements to be discharged to the connection terminal 7.
2a and the connection terminal 72b.

For example, the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_
2 to discharge the switch 11, the control signal CTL1 to the control signal CTL4 causes the switch 11a,
Switch 11b, switch 12a, switch 12b, switch 21a, switch 21b,
The transistor 252 included in each of the switch 22a and the switch 22b is turned on, and the transistor 251 is turned off. Furthermore, control signal CTL1 or control signal C
The transistor included in the switch 51 is turned on by TL2 and the transistor included in the switch 61 is turned off.

At this time, storage element 10_1, storage element 10_2, storage element 20_1, and storage element 20
Since the connection terminal 72a and the connection terminal 72b are in a conductive state, the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_2 are discharged through the connection terminal 72a and the connection terminal 72b.

Note that it is also possible to switch whether to charge the storage element according to the detection signal output from the current detection circuit 245.

For example, when the current detection circuit 245 determines that the amount of current flowing through the resistance element 244 is equal to or less than the reference value, it is assumed that the detection signal becomes high level. At this time, the semiconductor circuit 246 determines that the storage element needs to be charged. When the semiconductor circuit 246 is in the low power consumption mode, the interrupt signal P0IRQ is activated to resume the power supply to the processor 710. Furthermore, a data signal is generated according to an instruction instructing charging of the corresponding storage element, and is output via I / O port 750. In the semiconductor circuit 246 shown in FIG.
Although only one connection terminal 774 of 0 is illustrated, the present invention is not limited thereto, and a plurality of connection terminals 774 are provided when generating and outputting a plurality of data signals as in the present driving method example. May be

At this time, the encoder 240 sets the potentials of the control signals CTL1 to CTL4 by encoding the input data signal. Accordingly, among the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_2, the storage element to be charged can be connected to the connection terminal 71a and the connection terminal 71b to charge the storage element.

If it is desired to adjust the amount of current flowing to the load, the number of storage elements connected in series to the load may be changed. At this time, an instruction for setting the connection state of the storage element 10_1, the storage element 10_2, the storage element 20_1, and the storage element 20_2 corresponding to a desired amount of current is written in the memory 712 as data.

For example, when the amount of current flowing to the load may be smaller than the maximum current, a data signal is generated and output through the I / O port 750 according to an instruction to set the desired amount of current.

At this time, the encoder 240 encodes the input data signal to set the potentials of the control signals CTL1 to CTL4. Thereby, the switch 11a, the switch 11b,
The switch 12a, the switch 12b, the switch 21a, the switch 21b, the switch 22a,
The number of storage elements connected in series can be set by controlling the transistor 252 included in each of the switches 22 b, the transistor 251, the transistor included in the switch 51, and the transistor included in the switch 61.

In the case of discharging or charging the power storage device, data for setting a charging time or a discharging time as a reference value is written in the register 787 of the I / O interface 746. Then, the timer circuit 745 measures time. When the measured value of the timer circuit 745 reaches the value of time data previously written in the register 787, the semiconductor circuit 246 activates T0IRQ and outputs an interrupt signal, and the processor via the interrupt controller 721 The interrupt signal INT2 is sent to 710. The processor 710 may then execute an instruction to switch to charge or discharge, generate a data signal, and output it via the I / O port 750.

For example, in the case of discharging or charging the power storage device including the power storage element 10_1, the semiconductor circuit 24 can be used.
6 generates a data signal according to an instruction for discharging the storage element 10_1 using the processor 710 when the measured value in the timer circuit 745 exceeds the value of the time data written in the register 787. Output to the encoder 240 via the / O port 750. The encoder 240 encodes the input signal and controls the control signal CTL1 to the control signal CT.
The potential of L4 is set to electrically connect the storage element 10_1 to the connection terminal 72a and the connection terminal 72b. Thus, the storage element 10_1 is discharged.

In this manner, by setting the charge time and the discharge time in the register 787 of the I / O interface 746, the timer circuit 745 can control the length of the charge period and the discharge period to perform discharge or charge.

As described above, by controlling the switch using the semiconductor circuit 246 and the encoder 240, charging or discharging of the storage element can be controlled.

Third Embodiment register]
A configuration example of a register applicable to each circuit block of the semiconductor circuit 246 will be described with reference to FIG.

[3.1. Constitution]
The register illustrated in FIG. 10A includes a memory circuit 651, a memory circuit 652, and a selector 653.
And.

The memory circuit 651 receives the reset signal RST, the clock signal CLK, and the data signal D. The memory circuit 651 has a function of holding data of the input data signal D in accordance with the clock signal CLK and outputting the data as the data signal Q. Memory circuit 651
For example, it is possible to configure a register such as a buffer register or a general purpose register. Alternatively, as the memory circuit 651, Static Random Access M
A cache memory consisting of emory (also referred to as SRAM) may be provided.
These registers and cache memory can save data in the memory circuit 652.

The write control signal WE, the read control signal RD, and the data signal are input to the memory circuit 652.

The memory circuit 652 has a function of storing data of an input data signal in accordance with the write control signal WE and outputting the stored data as a data signal in accordance with the read control signal RD.

The selector 653 selects the data signal D or the data signal output from the memory circuit 652 in accordance with the read control signal RD, and inputs the selected data signal to the memory circuit 651.

The memory circuit 652 is provided with a transistor 631 and a capacitor 632.

The transistor 631 is an n-channel transistor and has a function as a selection transistor. One of the source and the drain of the transistor 631 is connected to the output terminal of the memory circuit 651. Further, the back gate of the transistor 631 is supplied with a power supply potential. The transistor 631 has a function of controlling retention of a data signal output from the memory circuit 651 in accordance with the write control signal WE.

For example, a transistor with low off current may be used as the transistor 631.

One of the pair of electrodes of the capacitor 632 is connected to the other of the source and the drain of the transistor 631, and the other is supplied with the low power supply potential VSS. The capacitor 632 has a function of holding charge based on data of a stored data signal. Since the off-state current of the transistor 631 is very low, the charge of the capacitor 632 is held and data is held even when the supply of the power supply voltage is stopped. The power supply voltage (VDD-VSS) is generated, for example, using the power supplied from the storage element.

The transistor 633 is a p-channel transistor. The high power supply potential VDD is supplied to one of the source and the drain of the transistor 633, and the read control signal R is supplied to the gate.
D is input.

The transistor 634 is an n-channel transistor. One of the source and the drain of the transistor 634 is connected to the other of the source and the drain of the transistor 633, and the read control signal RD is input to the gate.

The transistor 635 is an n-channel transistor. One of the source and the drain of the transistor 635 is connected to the other of the source and the drain of the transistor 634, and the other of the source and the drain is supplied with the low power supply potential VSS.

The input terminal of the inverter 636 is connected to the other of the source and the drain of the transistor 633. The output terminal of the inverter 636 is connected to the input terminal of the selector 653.

One of the pair of electrodes of the capacitor 637 is connected to the input terminal of the inverter 636, and the other is supplied with the low power supply potential VSS. The capacitor 637 has a function of holding charge based on data of a data signal input to the inverter 636.

In addition, it is not limited above, for example, phase change type memory (PRAM (Phase-change
The memory circuit 652 is formed using a RAM (also referred to as RAM) or a PCM (Phase Change Memory), a resistance change memory (also referred to as ReRAM (Resistance RAM)), a magnetoresistive memory (also referred to as MRAM (Magnetoresistive RAM)), or the like. May be For example, as a MRAM, a magnetic tunnel junction device (MT
MR using J (Magnetic Tunnel Junction)
AM can be applied.

[3.2. Driving method]
Next, an example of a method of driving the register shown in FIG. 10A will be described.

First, in the normal operation period, the power supply voltage serving as power, the reset signal RST, and the clock signal CLK are supplied to the register. At this time, the selector 653 outputs the data of the data signal D to the memory circuit 651. Storage circuit 651 holds the data of input data signal D in accordance with clock signal CLK. At this time, the transistor 633 is turned on by the read control signal RD, and the transistor 634 is turned off.

Next, in the backup period immediately before stopping the power supply voltage, the transistor 631 is turned on according to the write control signal WE, data of the data signal D is stored in the memory circuit 652, and the transistor 631 is turned off. Thereafter, the supply of the clock signal CLK to the register is stopped, and then the supply of the reset signal RST to the register is stopped. Note that when the transistor 631 is in an on state, a positive power supply potential may be supplied to the back gate of the transistor 631. At this time, the transistor 633 is turned on by the read control signal RD, and the transistor 634 is turned off.

Next, the supply of the power supply voltage to the register is stopped in the power supply stop period. At this time, since the off-state current of the transistor 631 in the memory circuit 652 is low, stored data is held. Note that supply of the power supply voltage can be considered to be stopped by supplying the ground potential GND instead of the high power supply potential VDD. Note that when the transistor 631 is off, a negative power supply potential may be supplied to the back gate of the transistor 631 to maintain the transistor 631 in the off state.

Next, in the recovery period immediately before returning to the normal operation period, the supply of the power supply voltage to the register is resumed, and then the supply of the clock signal CLK is resumed, and then the supply of the reset signal RST is resumed. At this time, the wiring to which the clock signal CLK is supplied is set to the high power supply potential VDD, and then the supply of the clock signal CLK is restarted. Further, the transistor 633 is turned off in accordance with the read control signal RD, the transistor 634 is turned on, and a data signal having a value stored in the memory circuit 652 is output to the selector 653. The selector 653 stores the data signal in accordance with the read control signal RD.
Output to Thus, the memory circuit 651 can be restored to the state immediately before the power supply stop period.

After that, the normal operation of the memory circuit 651 is performed again in the normal operation period.

The above is the example of the method for driving the register illustrated in FIG.

The register is not limited to the configuration shown in FIG.

For example, the register illustrated in FIG. 10B does not include the transistor 633, the transistor 634, the inverter 636, and the capacitor 637 as compared to the configuration of the register illustrated in FIG.
The configuration has a selector 654. The description of the register shown in FIG. 10A is incorporated as appropriate for the same portion as the register shown in FIG. 10A.

At this time, one of the source and the drain of the transistor 635 is connected to the input terminal of the selector 653.

Further, selector 654 sets low power supply potential V to be data in accordance with write control signal WE2.
A data signal output from the SS or the storage circuit 651 is selected and input to the storage circuit 652.

Next, an example of a method of driving the register illustrated in FIG. 10B will be described.

First, in the normal operation period, the power supply voltage, the reset signal RST, and the clock signal CLK are
It is in the state of being supplied to the register. At this time, the selector 653 outputs the data of the data signal D to the memory circuit 651. Storage circuit 651 holds the data of input data signal D in accordance with clock signal CLK. Also, the selector 65 follows the write control signal WE2.
4 outputs the low power supply potential VSS to the memory circuit 652. In memory circuit 652, transistor 631 is turned on in accordance with write control signal WE, and memory circuit 652 receives low power supply potential V.
SS is stored as data.

Next, in the backup period immediately before stopping the power supply voltage, the selector 654 according to the write control signal WE2 causes the output terminal of the memory circuit 651 and one of the source and the drain of the transistor 631 to be conductive instead of supplying the low power supply potential VSS. become. Further, the transistor 631 is turned on in accordance with the write control signal WE, data of the data signal D is stored in the memory circuit 652, and the transistor 631 is turned off. At this time, the data in the memory circuit 652 is rewritten only when the potential of the data signal D has the same value as the high power supply potential VDD. Furthermore, the supply of the clock signal CLK to the register is stopped, and the supply of the reset signal RST to the register is stopped. Note that when the transistor 631 is in an on state, a positive power supply potential may be supplied to the back gate of the transistor 631.

Next, the supply of the power supply voltage to the register is stopped in the power supply stop period. At this time, since the off-state current of the transistor 631 is low in the memory circuit 652, the value of data is held. Note that the supply of the power supply voltage can be considered to be stopped by supplying the ground potential GND instead of the high power supply potential VDD. Note that when the transistor 631 is off by the multiplexer, a negative power supply potential may be supplied to the back gate of the transistor 631 to maintain the transistor off.

Next, in the recovery period immediately before returning to the normal operation period, the supply of the power supply voltage to the register is resumed, and then the supply of the clock signal CLK is resumed, and then the supply of the reset signal RST is resumed. At this time, the wiring to which the clock signal CLK is supplied is set to the high power supply potential VDD, and then the supply of the clock signal CLK is restarted. The selector 653 outputs a data signal having a value corresponding to the data stored in the memory circuit 652 to the memory circuit 651 in accordance with the read control signal RD. As a result, the memory circuit 6 is set to the state immediately before the power supply stop period.
51 can be restored.

After that, the normal operation of the memory circuit 651 is performed again in the normal operation period.

The above is the example of the method for driving the register illustrated in FIG.

With the configuration shown in FIG. 10B, the low power supply potential VSS in the backup period is
Since it is possible to eliminate the writing of data, it is possible to speed up the operation.

When the above registers are used as the registers 784 to 787, the active mode to no
When transitioning to the f1 and Noff2 modes, the registers 784 to 78 are selected prior to power-off.
The data of the memory circuit 651 of 7 is written to the memory circuit 652, the data of the memory circuit 651 is reset to the initial value, and the power is shut off.

Also, when returning from Noff1 or Noff2 mode to Active, register 7
When the power supply to 84 to 787 is resumed, the data in the storage circuit 651 is first reset to the initial value. Then, the data of the memory circuit 652 is written to the memory circuit 651.

Therefore, even in the low power consumption mode, the data necessary for the processing of semiconductor circuit 246 can be
4 to 787, the semiconductor circuit 246 can be activated from the low power consumption mode.
It is possible to immediately return to the ve mode. Thus, the power consumption of the semiconductor circuit 246 can be reduced.

Fourth Embodiment memory]
An example of a memory applicable to one embodiment of the present invention is described. The memory can also be applied to, for example, the memory 712 shown in FIG.

[4.1. SRAM]
Here, SR, which is a memory configured by a flip flop to which a circuit of an inverter is applied, is used.
The AM (Static Random Access Memory) will be described.

Since SRAM uses flip-flops to hold data, DRAM (Dynamic
Unlike Random Access Memory, no refresh operation is required. Therefore, power consumption at the time of data retention can be suppressed. In addition, since no capacitive element is used, it is suitable for applications requiring high-speed operation.

FIG. 11 is a circuit diagram corresponding to a memory cell of the SRAM according to one embodiment of the present invention. Note that
Although only one memory cell is shown in FIG. 11, the present invention may be applied to a memory cell array in which a plurality of the memory cells are arranged.

The memory cell illustrated in FIG. 11 includes a transistor Tr1 e, a transistor Tr2 e, a transistor Tr3 e, a transistor Tr4 e, a transistor Tr5 e, and a transistor T.
and r6e. The transistor Tr1e and the transistor Tr2e are p-channel transistors, and the transistor Tr3e and the transistor Tr4e are n-channel transistors. The gate of the transistor Tr1e is the drain of the transistor Tr2e,
It is electrically connected to the gate of the transistor Tr3e, the drain of the transistor Tr4e, and one of the source and the drain of the transistor Tr6e. The high power supply potential VDD is applied to the source of the transistor Tr1e. The drain of the transistor Tr1e is electrically connected to the gate of the transistor Tr2e, the drain of the transistor Tr3e, and one of the source and the drain of the transistor Tr5e. The high power supply potential VDD is applied to the source of the transistor Tr2e. The ground potential GND is applied to the source of the transistor Tr3e. The back gate of the transistor Tr3e is electrically connected to the back gate line BGL. The ground potential GND is applied to the source of the transistor Tr4e. Transistor Tr
The back gate 4e is electrically connected to the back gate line BGL. Transistor Tr5
The gate of e is electrically connected to the word line WL. The other of the source and the drain of the transistor Tr5e is electrically connected to the bit line BLB. The gate of transistor Tr6e is electrically connected to word line WL. The other of the source and the drain of the transistor Tr6e is electrically connected to the bit line BL.

In the present embodiment, an example is shown in which n-channel transistors are applied as the transistor Tr5 e and the transistor Tr6 e. However, the transistors Tr5e and Tr6e are not limited to n-channel transistors, and p-channel transistors can also be applied. In that case, the write, hold, and read methods described later may be changed as appropriate.

Thus, a flip flop is configured by ring-connecting the inverter including the transistor Tr1 e and the transistor Tr3 e and the inverter including the transistor Tr2 e and the transistor Tr4 e.

As the p-channel transistor, for example, a transistor using silicon may be applied. However, the p-channel transistor is not limited to a transistor using silicon. In addition, as the n-channel transistor, the transistor including the oxide semiconductor film described in the above embodiment may be used.

In this embodiment, the transistor including the oxide semiconductor film described in the above embodiment is applied as the transistor Tr3 e and the transistor Tr4 e. Since the transistor has extremely small off-state current, through current also becomes extremely small.

Note that an n-channel transistor can be used as the transistor Tr1 e and the transistor Tr2 e instead of the p-channel transistor. Transistor Tr1e
When an n-channel transistor is used as the transistor Tr2e, a depletion transistor may be applied.

The writing, holding, and reading of the memory cell shown in FIG. 11 will be described below.

At the time of writing, first, a potential corresponding to data 0 or data 1 is applied to the bit line BL and the bit line BLB.

For example, when data 1 is to be written, bit line BL is set to high power supply potential VDD, bit line BL
Let B be the ground potential GND. Next, a potential (VH) equal to or higher than the sum of the high power supply potential VDD and the threshold voltage of the transistors Tr5e and Tr6e is applied to the word line WL.

Next, by setting the potential of the word line WL to less than the threshold voltage of the transistors Tr5e and Tr6e, the data 1 written to the flip-flop is held. In the case of the SRAM, the current flowing in retaining data is only the leak current of the transistor. Where SR
By applying the above-described transistor with low off current to a part of transistors included in AM, standby power for data retention can be reduced.

At the time of reading, the bit line BL and the bit line BLB are previously set to the high power supply potential VDD.
Next, by applying VH to the word line WL, the bit line BL remains unchanged at the high power supply potential VDD, but the bit line BLB is discharged through the transistor Tr5e and the transistor Tr3e to become the ground potential GND. Data 1 held can be read out by amplifying the potential difference between bit line BL and bit line BLB with a sense amplifier (not shown).

When data 0 is to be written, bit line BL is at ground potential GND and bit line BLB.
May be set to the high power supply potential VDD, and then VH may be applied to the word line WL. Next, by setting the potential of the word line WL to less than the threshold voltage of the transistors Tr5e and Tr6e, the data 0 written to the flip-flop is held. At the time of reading, the bit line BLB remains unchanged at the high power supply potential VDD by setting the bit line BL and the bit line BLB to the high power supply potential VDD and applying VH to the word line WL in advance. And discharge through the transistor Tr4e to the ground potential GND.
Data 0 held can be read out by amplifying the potential difference between bit line BL and bit line BLB with a sense amplifier.

According to the above aspect, an SRAM with small standby power can be provided.

[4.2. DOSRAM]
A transistor including an oxide semiconductor film can have extremely low off-state current. That is, the transistor has an electrical characteristic in which charge leakage through the transistor is less likely to occur. In the following, a DOSRAM (Dynamic Oxide Semiconductor) to which a transistor having such electrical characteristics is applied as a memory superior in function to a known memory.
The uctor random access memory will be described. DOSR
AM refers to a memory in which the above-mentioned transistor with low off current is used as a select transistor (transistor as a switching element) of a memory cell.

First, the memory will be described with reference to FIG. Here, FIG. 12A is a circuit diagram showing a memory cell array of a memory. FIG. 12B is a circuit diagram of a memory cell.

The memory cell array shown in FIG. 12A includes a memory cell 1050, a bit line 1051, and the like.
A plurality of word lines 1052, capacitance lines 1053, and sense amplifiers 1054 are provided.

Note that bit lines 1051 and word lines 1052 are provided in a grid shape, and each memory cell 1 is
050 are disposed one by one at the intersections of the bit lines 1051 and the word lines 1052. The bit line 1051 is connected to the sense amplifier 1054, and has a function of reading the potential of the bit line 1051 as data.

As illustrated in FIG. 12B, the memory cell 1050 includes the transistor 1055 and the capacitor 105.
And 6). The gate of the transistor 1055 is electrically connected to the word line 1052. The source of the transistor 1055 is electrically connected to the bit line 1051. The drain of the transistor 1055 is electrically connected to one end of the capacitor 1056. The other end of capacitor 1056 is electrically connected to capacitance line 1053.

FIG. 13 is a perspective view of the memory. The memory shown in FIG. 13 includes a plurality of memory cells as a memory circuit at the top, and a memory cell array (memory cell array 3400 a to memory cell array 3
A plurality of layers 400 n (n is an integer of 2 or more) are provided, and a logic circuit 3004 necessary for operating the memory cell array 3400 a to the memory cell array 3400 n is provided below.

The voltage held in the capacitor 1056 gradually decreases with time due to the leak of the transistor 1055. The voltage charged from V0 to V1 initially decreases to VA, which is the limit point for reading out data 1 as time passes. This period is referred to as a holding period T_1. That is, in the case of a binary memory cell, it is necessary to refresh during the holding period T_1.

For example, when the off-state current of the transistor 1055 is not sufficiently small, the time change of the voltage held in the capacitor 1056 is large, so that the holding period T_1 is shortened. Therefore, it is necessary to refresh frequently. As the frequency of refresh increases, the power consumption of the memory increases.

In this embodiment, the off-state current of the transistor 1055 is extremely small.
Can be quite long. That is, since the frequency of refresh can be reduced, power consumption can be reduced. For example, when a memory cell is formed with the transistor 1055 whose off-state current is 1 × 10 ⁻²¹ A to 1 × 10 ⁻²⁵ A, data can be held for several days to several decades without supplying power. It becomes possible.

As described above, according to one embodiment of the present invention, a memory with high integration and low power consumption can be obtained.

[4.3. NOSRAM]
Next, as a memory different from the memory shown in FIG. 11 and FIG.
volatile Oxide Semiconductor Random Acce
ss Memory) will be described. The NOSRAM indicates a memory in which the transistor with a low off current is used as a select transistor (transistor as a switching element) of a memory cell and a transistor using a silicon material or the like is used as an output transistor of the memory cell.

FIG. 14A is a circuit diagram including a memory cell and a wiring which constitute a memory. Also, FIG.
(B) is a figure which shows the electrical property of the memory cell shown to FIG. 14 (A).

As shown in FIG. 14A, the memory cell includes a transistor 1071 and a transistor 1072.
And a capacitor 1073. Here, the gate of the transistor 1071 is the word line 10
It is electrically connected to 76. The source of the transistor 1071 is electrically connected to the source line 1074. The drain of the transistor 1071 is electrically connected to the gate of the transistor 1072 and one end of the capacitor 1073, and this portion is referred to as a node 1079. The source of the transistor 1072 is electrically connected to the source line 1075. Transistor 107
The drain of 2 is electrically connected to the drain line 1077. The other end of capacitor 1073 is electrically connected to capacitance line 1078.

Note that the memory illustrated in FIG. 14 utilizes variation in the apparent threshold voltage of the transistor 1072 in accordance with the potential of the node 1079. For example, FIG. 14B illustrates the relationship between the voltage V _CL of the capacitor line 1078 and the drain current I _{d —} 2 flowing through the transistor 1072.

Note that the potential of the node 1079 can be adjusted through the transistor 1071. For example, the potential of the source line 1074 is set to the high power supply potential VDD. At this time, the word line 1076
The potential of the node 1079 can be set to HIGH by setting the potential of the potential of the transistor 1071 to the potential obtained by adding the high power supply potential VDD to the threshold voltage Vth of the transistor 1071 or higher. Further, by setting the potential of the word line 1076 to the threshold voltage Vth or lower of the transistor 1071, the potential of the node 1079 can be LOW.

Therefore, the transistor 1072 has a V _CL -I _d _2 curve shown by LOW and an HIG
It becomes one of the electrical characteristics of the V _CL -I _d _2 curve shown by H. That is, at LOW, since I _d _2 is small at V _CL = 0 V, data 0 is obtained. Also, at HIGH, V _C
Since I _d _2 is large at _L = 0 V, data 1 is obtained. In this way, data can be stored.

By using a transistor with low off-state current as the transistor 1071, data retention time can be extended. With the use of the transistor 1072, data can be read repeatedly because data is not lost when data is read.

Fifth Embodiment Structural Example of Semiconductor Device]
A structural example of a semiconductor device used for a control system, a storage system, and the like will be described.

[5.1. Structure of transistor]
First, structural examples of a transistor applicable to a semiconductor device are described.

The structure of the transistor is not particularly limited, and can be any structure. As a structure of the transistor, for example, a stagger type or a planar type of a bottom gate structure described below can be used. The transistor may have a single gate structure in which one channel formation region is formed, a multigate structure such as a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. In addition, a structure having two gate electrodes disposed above and below the channel formation region with a gate insulating film interposed therebetween (herein, this may be referred to as a dual gate structure). Alternatively, a channel etch type or channel protection type transistor may be used.

[5.1.1. Bottom gate structure]
FIG. 15 shows a configuration example of a transistor 421 having a bottom gate top contact structure, which is a type of bottom gate transistor. 15A is a plan view of the transistor 421, FIG. 15B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 15A, and FIG. It is sectional drawing in dashed dotted line B1-B2 in A).

The transistor 421 includes a gate electrode 401 provided over a substrate 400 having an insulating surface, a gate insulating film 402 provided over the gate electrode 401, and an oxide film overlapping with the gate electrode 401 with the gate insulating film 402 interposed therebetween. And a source electrode 405 a and a drain electrode 405 b which are provided in contact with the oxide film 404. In addition, an insulating film 406 is provided to cover the source electrode 405 a and the drain electrode 405 b and to be in contact with the oxide film 404. The substrate 400 may be a device forming substrate on which another device is formed.

Note that in the oxide film 404, an n-type region 403 may be provided in a region in contact with the source electrode 405a and the drain electrode 405b.

[5.1.2. Top gate structure]
The top gate transistor 422 is illustrated in FIG.

The transistor 422 includes an insulating film 408 provided over a substrate 400 having an insulating surface, an oxide film 404 provided over the insulating film 408, and a source electrode 405a and a drain electrode provided in contact with the oxide film 404. And a gate insulating film 409 provided over the oxide film 404, the source electrode 405a, and the drain electrode 405b, and a gate electrode 410 overlapping with the oxide film 404 with the gate insulating film 409 interposed therebetween.

Note that in the oxide film 404, an n-type region 403 may be provided in a region in contact with the source electrode 405a and the drain electrode 405b.

[5.1.3. Dual gate structure]
FIG. 16B illustrates a dual-gate transistor 423 having two gate electrodes disposed above and below the channel formation region with a gate insulating film interposed therebetween.

The transistor 423 includes a gate electrode 401 provided over a substrate 400 having an insulating surface, a gate insulating film 402 provided over the gate electrode 401, and an oxide film overlapping with the gate electrode 401 with the gate insulating film 402 interposed therebetween. 404, a source electrode 405a and a drain electrode 405b provided in contact with the oxide film 404, and a source electrode 405a and a drain electrode 40.
A gate insulating film 409 which covers the transistor 5 b and is in contact with the oxide film 404 and a gate electrode 410 which overlaps with the oxide film 404 with the gate insulating film 409 interposed therebetween.

Note that in the oxide film 404, an n-type region 403 may be provided in a region in contact with the source electrode 405a and the drain electrode 405b.

[5.2. Components of transistor]
Each component of the transistor is described.

[5.2.1. Conductive film]
As the gate electrode 401 and the gate electrode 410, for example, Al, Cr, Cu, Ta, Ti
, Mo, W, etc. can be used.

The source electrode 405a and the drain electrode 405b may be, for example, Al, Cr, Cu, Ta.
, Ti, Mo, W, etc. can be used.

[5.2.2. Insulating film]
As the gate insulating film 402, the insulating film 406, and the gate insulating film 409, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, a gallium oxide film, an aluminum oxide film, an aluminum nitride film, or oxynitride nitride An aluminum film can be used.

In addition, by forming the insulating film under film forming conditions in which a large amount of oxygen is contained, an insulating film containing excess oxygen can be formed. Further, when it is desired to include more excess oxygen in the insulating film, oxygen may be added by ion implantation, ion doping, or plasma treatment. Thus, oxygen can be supplied to the oxide film.

[5.2.3. Oxide film]
Further, materials applicable to the oxide film 404 are described.

As the oxide film 404, a film of, for example, an In-based metal oxide, a Zn-based metal oxide, an In—Zn-based metal oxide, or an In—Ga—Zn-based metal oxide can be used.

In may have a function of enhancing the conductivity of the oxide film 404, for example. For example, In
The carrier mobility of the oxide film 404 can be improved.

Alternatively, a metal oxide containing another metal element instead of part or all of Ga contained in the above In-Ga-Zn-based metal oxide may be used. As the other metal element, for example, a metal element capable of binding to more oxygen atoms than gallium may be used, and for example, any one or more elements of titanium, zirconium, hafnium, germanium, and tin may be used. Just do it. In addition, as the other metal element, any one or more of lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and lutetium can be used. Good. These metal elements may have a function as a stabilizer and may have a function of suppressing the generation of oxygen vacancies in the oxide film. In addition, the addition amount of these metal elements is an amount which a metal oxide can function as a semiconductor. By using a metal element capable of binding to more oxygen atoms than gallium and supplying oxygen into the metal oxide, oxygen defects in the metal oxide can be reduced.

Zn may have a function of facilitating crystallization of an oxide film, for example.

The hydrogen concentration in the oxide film is measured by secondary ion mass spectrometry (SIMS: Secondary Ion).
In mass spectrometry), 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ at.
It can be oms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, the nitrogen concentration in the oxide film is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atm in SIMS.
It can be oms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, the carbon concentration in the oxide film is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atm in SIMS.
It can be oms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, the silicon concentration in the oxide film is 5 × 10 ¹⁹ atoms / cm in SIMS.
Less than ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸
atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, the sodium concentration in the oxide film is 5 × 10 ¹⁶ cm ⁻³ or less in SIMS,
Preferably it can be set to 1 × 10 16 cm ⁻³ or less, more preferably 1 × 10 ¹⁵ cm ⁻³ or less. In addition, the lithium concentration in the oxide film is 5 × 10 ^{15 in} SIMS.
It can be set to cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or less. Further, the potassium concentration in the oxide film can be 5 × 10 ¹⁵ cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or less.

In oxide films, thermal desorption gas spectroscopy (TDS: Thermal Desorpti)
Gas molecules (atoms) whose m / z is 2 (such as hydrogen molecule), gas molecules (atoms) whose m / z is 18 and gas molecules (atoms) whose m / z is 28 by m The amount of released gas molecules (atoms) where / z is 44 is 1 × 10 ¹⁹ / cm, respectively
^It is preferably ³ or less, preferably 1 × 10 ¹⁸ cells / cm ³ or less.

For the oxide film 404, an oxide semiconductor film can be used, for example.

The oxide semiconductor film may have, for example, a non-single crystal. Non-single crystals are, for example, CAAC (C
Axis Aligned Crystal), polycrystalline, microcrystalline, having amorphous parts.
The amorphous part has a higher density of defect states than microcrystalline or CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor containing a CAAC is referred to as a CAAC-OS (C
Axis Aligned Crystalline Oxide Semicond
Call it uctor.

The oxide semiconductor film may have, for example, a CAAC-OS. For example, CAAC-OS
The oxide semiconductor is c-axis oriented and the a-axis and / or b-axis are not aligned macroscopically.

Sixth Embodiment Power storage device]
A non-aqueous secondary battery represented by a lithium ion secondary battery will be described below as an example of a power storage device.

[6.1. Positive electrode]
First, the positive electrode of the power storage device will be described with reference to FIG.

The positive electrode 6000 includes a positive electrode current collector 6001 and a positive electrode active material layer 6002 formed on the positive electrode current collector 6001 by a coating method, a CVD method, a sputtering method, or the like. FIG. 17A shows an example in which the positive electrode active material layer 6002 is provided on both sides of a sheet-like (or strip-like) positive electrode current collector 6001, but the present invention is not limited thereto. It may be provided only on one side of the positive electrode current collector 6001. In FIG. 17A, the positive electrode active material layer 6002 is provided on the entire surface of the positive electrode current collector 6001; however, without limitation thereto, the positive electrode active material layer 6002 may be provided on part of the positive electrode current collector 6001. . For example, the positive electrode active material layer 6002 may not be provided in a portion where the positive electrode current collector 6001 and the positive electrode tab are connected.

For the positive electrode current collector 6001, a material such as stainless, gold, platinum, zinc, iron, metals such as copper, aluminum, titanium, and alloys thereof, which has high conductivity and is not alloyed with carrier ions such as lithium is used. be able to. Also, silicon, titanium, neodymium, scandium,
An aluminum alloy to which an element that improves heat resistance such as molybdenum is added can be used. Alternatively, it may be formed of a metal element which reacts with silicon to form a silicide. Examples of the metal element which reacts with silicon to form silicide include zirconium, titanium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel and the like. The positive electrode current collector 6001 can have a foil shape, a plate shape (sheet shape), a net shape, a punching metal shape, an expanded metal shape, or the like as appropriate. Positive electrode current collector 60
It is preferable that 01 has a thickness of 10 μm to 30 μm.

FIG. 17B is a schematic view showing a vertical cross section of the positive electrode active material layer 6002. Positive electrode active material layer 6
The 002 includes a granular positive electrode active material 6003, graphene 6004 as a conductive additive, and a binder 6005 (binder).

As the conductive additive, other than graphene described later, acetylene black (AB), ketjen black, graphite (graphite) particles, carbon nanotubes, etc. can be used. Here, as one example, positive electrode active using graphene 6004 The material layer 6002 will be described.

A positive electrode active material 6003 is a granular positive electrode composed of secondary particles having an average particle diameter and a particle diameter distribution, which is obtained by pulverizing, granulating and classifying the calcined product obtained by mixing and calcining the raw material compounds in a predetermined ratio by appropriate means. It is an active material. Therefore, although the positive electrode active material 6003 is schematically shown as a sphere in FIG. 17B, the present invention is not limited to this shape.

Any material can be used as the positive electrode active material 6003 as long as carrier ions such as lithium ions can be inserted and released.

For example, a lithium-containing composite phosphate having an olivine structure (general formula LiMPO ₄ (M is Fe
(II), Mn (II), Co (II), one or more of Ni (II))) can be used. Typical examples of the general formula LiMPO ₄ include LiFePO ₄ , LiNiPO ₄ , LiCo
PO ₄ , LiMnPO ₄ , LiFe _a Ni _b PO ₄ , LiFe _a Co _b PO ₄ , LiFe
_a Mn _b PO ₄ , LiNi _a Co _b PO ₄ , LiNi _a Mn _b PO ₄ (a + b is 1 or less,
0 <a <1, 0 <b <1), LiFe _c Ni _d Co _e PO ₄ , LiFe _c Ni _d Mn _e P
_{O 4, LiNi c Co d Mn} e PO 4 (c + d + e ≦ 1, 0 <c <1,0 <d <1,
0 <e <1), LiFe _f Ni _g Co _h Mn _i PO ₄ (f + g + h + i is 1 or less, 0 <f
Lithium compounds such as <1, 0 <g <1, 0 <h <1, 0 <i <1) can be used as the positive electrode active material.

Or the general formula Li _(2-j) MSiO ₄ (M is Fe (II), Mn (II), Co (I
Lithium-containing complex silicates such as I), one or more of Ni (II), 0 ≦ j ≦ 2) can be used. As a representative example of the general formula Li _(2-j) MSiO ₄ , Li _(2-j) FeSi
O ₄ , Li _(2-j) NiSiO ₄ , Li _(2-j) CoSiO ₄ , Li _(2-j) Mn
SiO ₄ , Li _(2-j) Fe _k Ni _l SiO ₄ , Li _(2-j) Fe _k Co ₁ SiO ₄
, Li _(2-j) Fe _k Mn _l SiO ₄ , Li _{(2- j)} Ni _k Co _l SiO ₄ , Li _(
2-j) Ni _k Mn _l SiO ₄ (k + 1 is 1 or less, 0 <k <1, 0 <l <1), Li _(2
−j) Fe _m Ni _n Co _q SiO ₄ , Li _(2-j) Fe _m Ni _n Mn _q SiO ₄ , Li
_{(2-j) Ni m Co} n Mn q SiO 4 (m + n + q is 1 or less, 0 <m <1,0 <n <1
_{, 0 <q <1),} Li (2-j) Fe r Ni s Co t Mn u SiO 4 (r + s + t + u ≦ 1, 0 <r <1,0 <s <1,0 <t <1,0 < Compounds such as u <1) can be used as the positive electrode active material.

In addition, lithium cobaltate (LiCoO ₂ ), LiNi having a layered rock salt type crystal structure
NiCo-based (such as O ₂ , LiMnO ₂ , Li ₂ MnO ₃ , LiNi _0.8 Co _0.2 O _2, etc.
The general formula is LiNi _x Co _1-x O ₂ (0 <x <1), LiNi _0.5 Mn _0.5 O ₂
NiMn system etc. (general _{formula, LiNi x Mn 1-x O} 2 (0 <x <1)), LiNi 1 /
NiMnCo series such as ₃ Mn _1/3 Co _1/3 O ₂ (also referred to as NMC, the general formula is LiNi)
_{x Mn y Co 1-x-} y O 2 (x> 0, y> 0, x + y <1)) can be used lithium-containing material, such as.

Further, other various compounds can be used, such as an active material having a spinel crystal structure such as LiMn ₂ O ₄ , an active material having an inverse spinel crystal structure such as LiMVO _{4, and the} like.

When the carrier ion is an alkali metal ion other than a lithium ion or an alkaline earth metal ion, an alkali metal (eg, sodium, potassium, etc.) is used as the positive electrode active material 6003 in place of lithium in the above compounds and oxides. ), Alkaline earth metals (eg, calcium, strontium, barium, beryllium, magnesium etc.) may be used.

Although not shown, a carbon layer may be provided on the surface of the positive electrode active material 6003. By providing the carbon layer, the conductivity of the electrode can be improved. The coating of the carbon layer on the positive electrode active material 6003 can be formed by mixing a carbohydrate such as glucose at the time of firing of the positive electrode active material.

In addition, the graphene 6004 added to the positive electrode active material layer 6002 as a conductive additive can be formed by performing reduction treatment on graphene oxide.

Here, in the present specification, graphene includes single-layer graphene or multilayer graphene including two or more and 100 or less layers. Single-layer graphene refers to a sheet of one atomic layer of carbon molecules having a π bond. In addition, graphene oxide refers to a compound in which the graphene is oxidized. Note that in the case where graphene oxide is reduced to form graphene, part of oxygen remains in the graphene without desorbing all oxygen contained in the graphene oxide. When oxygen is contained in graphene, the proportion of oxygen is 2 atomic% or more and 20 atomic% or less of the entire graphene, preferably 3 atomic% or more, as measured by XPS.
It is less than atomic%.

Here, in the case where the graphene is a multilayer graphene, an interlayer distance of graphene is 0.34 nm or more and 0.5 nm or less, preferably 0.38 nm or more and 0.42 nm or less, and more preferably, by having graphene obtained by reducing graphene oxide. 0.39 nm or more and 0.41 nm or less. Since the interlayer distance of single-layer graphene is 0.34 nm and graphene used in the power storage device according to one embodiment of the present invention has a longer interlayer distance, transfer of carrier ions between the layers of multilayer graphene is possible. Becomes easy.

Graphene oxide can be manufactured, for example, using an oxidation method called Hummers method.

In the Hummers method, a sulfuric acid solution of potassium permanganate, a hydrogen peroxide solution, and the like are added to graphite powder to cause an oxidation reaction to prepare a dispersion containing graphite oxide. In graphite oxide, functional groups such as an epoxy group, a carbonyl group, a carboxyl group and a hydroxyl group are bonded by the oxidation of carbon of graphite. For this reason, the interlayer distance of the plurality of graphenes is longer than that of the graphite, and exfoliation due to interlayer separation is facilitated. Next, ultrasonic vibration is applied to the mixed solution containing graphite oxide, whereby the graphite oxide having a long interlayer distance is cleaved to separate the graphene oxide, and a dispersion including graphene oxide can be manufactured. Then, powdered graphene oxide can be obtained by removing the solvent from the dispersion containing graphene oxide.

In addition, preparation of graphene oxide is Hummers using sulfuric acid solution of potassium permanganate
Instead of the method, for example, the Hummers method using nitric acid, potassium chlorate, sodium nitrate, potassium permanganate or the like, or a manufacturing method of graphene oxide other than the Hummers method may be used as appropriate.

In addition to the addition of ultrasonic vibration, exfoliation of graphite oxide may be performed by irradiation of microwaves, radio waves, or thermal plasma, or addition of physical stress.

The produced graphene oxide has an epoxy group, a carbonyl group, a carboxyl group, a hydroxyl group, and the like. Graphene oxide is negatively charged with oxygen in a functional group in a polar solvent represented by NMP (also referred to as N-methylpyrrolidone, 1-methyl-2-pyrrolidone, N-methyl-2-pyrrolidone, etc.) Therefore, while interacting with NMP, the different graphene oxides repel each other and hardly aggregate. Therefore, graphene oxide is easily dispersed uniformly in a polar solvent.

In addition, the length of one side (also referred to as flake size) of graphene oxide is 50 n
The thickness is preferably m or more and 100 μm or less, more preferably 800 nm or more and 20 μm or less.

As shown in the cross-sectional view of the positive electrode active material layer 6002 shown in FIG.
003 is covered by a plurality of graphenes 6004. One sheet of graphene 6004 is connected to a plurality of granular positive electrode active materials 6003. In particular, graphene 600
Since 4 is in the form of a sheet, it can be in surface contact so as to wrap a part of the surface of the granular positive electrode active material 6003. Unlike granular conductive aids such as acetylene black and the like, which are in point contact with the positive electrode active material, the graphene 6004 enables surface contact with low contact resistance, and therefore, it is possible to use granular form without increasing the amount of conductive aids. The electron conductivity of the positive electrode active material 6003 and the graphene 6004 can be improved.

In addition, the plurality of graphenes 6004 are also in surface contact with each other. This is because graphene oxide with extremely high dispersibility in a polar solvent is used for forming the graphene 6004. In order to volatilize and remove the solvent from the dispersion medium containing the uniformly dispersed graphene oxide and reduce the graphene oxide to form graphene, the graphene 6004 remaining in the positive electrode active material layer 6002 partially overlaps and is in surface contact with each other It forms an electron conduction path by being dispersed in

In addition, part of the graphene 6004 is provided between the plurality of positive electrode active materials 6003 and is formed to be three-dimensionally arranged. In addition, since the graphene 6004 is an extremely thin film (sheet) configured of a single layer of carbon molecules or a stack of these, the positive electrode active material 6 of individual particles is
Contact a portion of the surface so as to trace the surface of 003;
The portion which is not in contact with the plurality of granular positive electrode active materials 6003 is bent, wrinkled, or stretched to exhibit a stretched state.

Therefore, a plurality of graphenes 6004 form a network of electron conduction in the positive electrode 6000. For this reason, the path of electrical conduction between the positive electrode active materials 6003 is maintained. From the above, in the case of the application method, a positive electrode active having high electron conductivity can be obtained by using, as a conductive agent, graphene obtained by applying and dispersing a dispersion medium containing graphene oxide uniformly dispersed, and drying it. A material layer 6002 can be formed.

In order to increase the contact point between the positive electrode active material 6003 and the graphene 6004, the ratio of the positive electrode active material 6003 in the positive electrode active material layer 6002 can be increased because the amount of addition of the conductive aid does not have to be increased. it can. Thereby, the discharge capacity of the secondary battery can be increased.

The average particle diameter of the primary particles of the granular positive electrode active material 6003 is 500 nm or less, preferably 50 n.
It is preferable to use one having m or more and 500 nm or less. The graphene 6004 preferably has a length of 50 nm to 100 μm, preferably 800 nm to 20 μm, in order to make surface contact with the plurality of granular positive electrode active materials 6003.

Moreover, as a binder (binder) contained in the positive electrode active material layer 6002, in addition to typical polyvinylidene fluoride (PVDF), polyimide, polytetrafluoroethylene, polyvinyl chloride, ethylene propylene diene polymer, styrene-butadiene rubber Acrylonitrile-butadiene rubber, fluororubber, polyvinyl acetate, polymethyl methacrylate, polyethylene, nitrocellulose and the like can be used.

The positive electrode active material layer 6002 described above contains 90 wt% or more and 94 wt% or less of the positive electrode active material with respect to the total amount of the positive electrode active material 6003 and graphene 6004 as a conductive additive and a binder. It is preferable to contain graphene in a ratio of 1 wt% to 5 wt% and a binder in a ratio of 1 wt% to 5 wt%.

[6.2. Negative electrode]
Next, the negative electrode of the power storage device is described with reference to FIG.

The negative electrode 6100 includes a negative electrode current collector 6101 and a negative electrode active material layer 6102 which is formed over the negative electrode current collector 6101 by a coating method, a CVD method, a sputtering method, or the like. FIG. 18A shows an example in which the negative electrode active material layer 6102 is provided on both sides of a sheet-like (or band-like) negative electrode current collector 6101; however, the present invention is not limited thereto. It may be provided only on one side of the negative electrode current collector 6101. In FIG. 18A, the negative electrode active material layer 6102 is provided over the entire surface of the negative electrode current collector 6101; however, without limitation thereto, the negative electrode active material layer 6102 may be provided over part of the negative electrode current collector 6101 . For example, the negative electrode active material layer 6102 is preferably not provided in a portion where the negative electrode current collector 6101 and the negative electrode tab are connected.

For the negative electrode current collector 6101, a material such as stainless, gold, platinum, zinc, metal such as iron, copper, titanium, or an alloy thereof that has high conductivity and is not alloyed with carrier ions such as lithium can be used. it can. Alternatively, it may be formed of a metal element which reacts with silicon to form a silicide. Examples of the metal element which reacts with silicon to form silicide include zirconium, titanium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel and the like. The negative electrode current collector 6101 can have a foil shape, a plate shape (sheet shape), a net shape, a punching metal shape, an expanded metal shape, or the like as appropriate. The negative electrode current collector 6101 preferably has a thickness of 10 μm to 30 μm.

FIG. 18B is a view schematically showing a cross section of a part of the negative electrode active material layer 6102. Here, although an example in which the negative electrode active material 6103 and the binder 6105 (binder) are included in the negative electrode active material layer 6102 is shown, the present invention is not limited thereto, and at least the negative electrode active material 6103 may be included.

The negative electrode active material 6103 is not particularly limited as long as it is a material that can dissolve and deposit a metal or can insert and desorb a metal ion. As a material of the negative electrode active material 6103, in addition to lithium metal, graphite which is a common carbon material in the field of power storage can be used. Graphite includes soft carbon and hard carbon as low crystalline carbon, and natural graphite, quiche graphite, pyrolytic carbon, liquid crystal pitch carbon fiber, meso carbon micro beads (MCMB), liquid crystal pitch as high crystalline carbon , Petroleum or coal-based coke and the like.

Further, as the negative electrode active material 6103, in addition to the above-described materials, an alloy-based material which can perform charge and discharge reaction by alloying with carrier ions and dealloying reaction can be used. When the carrier ion is lithium ion, examples of alloy materials include Mg, Ca, Al, Si
A material containing at least one of Ge, Sn, Pb, As, Sb, Bi, Ag, Au, Zn, Cd, Hg, In, and the like can be used. Such metals have a large capacity relative to graphite, and in particular, silicon has a dramatically high theoretical capacity of 4200 mAh / g. For this reason,
It is preferable to use silicon for the negative electrode active material 6103.

In FIG. 18B, although the negative electrode active material 6103 is expressed as a granular material, the present invention is not limited thereto. The shape of the negative electrode active material 6103 is, for example, a plate, a rod, a column, a powder, or a scale It can be of any shape. Moreover, what has uneven | corrugated shape in plate-shaped surface, what has fine uneven | corrugated shape on the surface, and what has three-dimensional shapes, such as what has a porous shape, may be used.

In the case of forming the negative electrode active material layer 6102 using a coating method, a conductive additive (not shown) and a binder 6105 are added to the negative electrode active material 6103 to prepare a negative electrode paste.
It may be coated on 01 and dried.

Note that lithium may be predoped in the negative electrode active material layer 6102. As a pre-doping method, a lithium layer may be formed on the surface of the negative electrode active material layer 6102 by a sputtering method. Further, by providing a lithium foil on the surface of the negative electrode active material layer 6102, the negative electrode active material layer 610 is obtained.
Lithium can also be pre-doped into 2;

In addition, graphene (not illustrated) is preferably formed on the surface of the negative electrode active material 6103. For example, in the case where silicon is used as the negative electrode active material 6103, the adhesion between the negative electrode current collector 6101 and the negative electrode active material layer 6102 is reduced because a change in volume is large due to insertion and extraction of carrier ions in charge and discharge cycles. Battery characteristics are degraded by charge and discharge. Therefore, when graphene is formed on the surface of the negative electrode active material 6103 containing silicon, the decrease in adhesion between the negative electrode current collector 6101 and the negative electrode active material layer 6102 is suppressed even if the silicon volume changes in the charge and discharge cycle. It is preferable because deterioration of battery characteristics is reduced.

Graphene formed on the surface of the negative electrode active material 6103 can be formed by reducing graphene oxide as in the method for manufacturing the positive electrode. As the graphene oxide, the above-described graphene oxide can be used.

In addition, a film 6104 such as an oxide may be formed on the surface of the negative electrode active material 6103. A film (Solid Electrolyte) formed by decomposition of the electrolyte during charging
Interphase) can not release the amount of charge consumed during its formation and forms an irreversible capacity. On the other hand, the negative electrode active material 61
By providing on the surface of 03, generation | occurrence | production of irreversible capacity | capacitance can be suppressed or prevented.

The film 6104 for covering such a negative electrode active material 6103 may be niobium, titanium, vanadium, tantalum, tungsten, zirconium, molybdenum, hafnium, chromium, an oxide film of any of aluminum, silicon, or any of these elements. An oxide film containing one and lithium can be used. Such a film 6104 is a sufficiently dense film as compared with the film formed on the negative electrode surface by the decomposition product of the conventional electrolytic solution.

For example, niobium oxide (Nb ₂ O ₅ ) has a low electrical conductivity of 10 ⁻⁹ S / cm and exhibits high insulation. Therefore, the niobium oxide film inhibits the electrochemical decomposition reaction between the negative electrode active material and the electrolytic solution. On the other hand, the lithium diffusion coefficient of niobium oxide is 10 ⁻⁹ cm ² / sec and has high lithium ion conductivity. Therefore, it is possible to transmit lithium ions.

For example, a sol-gel method can be used to form the film 6104 covering the negative electrode active material 6103. The sol-gel method is a method in which a solution comprising a metal alkoxide, a metal salt or the like is used as a gel which has lost fluidity by hydrolysis reaction and polycondensation reaction, and this gel is fired to form a thin film. Since the sol-gel method is a method of forming a thin film from a liquid phase, the raw materials can be homogeneously mixed at the molecular level. Therefore, the active material can be easily dispersed in the gel by adding a negative electrode active material such as graphite to the raw material of the metal oxide film at the stage of the solvent. In this manner, the film 6104 can be formed on the surface of the negative electrode active material 6103.

The use of the film 6104 can prevent a decrease in capacity of the power storage device.

6.3. Electrolyte solution]
As a solvent of an electrolytic solution used for a power storage device, an aprotic organic solvent is preferable. For example, ethylene carbonate (EC), propylene carbonate (PC), butylene carbonate, chloroethylene carbonate, vinylene carbonate, γ-butyrolactone, γ-valero Lactone, dimethyl carbonate (DMC), diethyl carbonate (DEC), ethyl methyl carbonate (EMC), methyl formate, methyl acetate, methyl acetate, methyl butyrate, 1,3-dioxane, 1,4-dioxane, dimethoxyethane (DME), dimethyl sulfoxide And diethyl ether, methyl diglyme, acetonitrile, benzonitrile, tetrahydrofuran, sulfolane, sultone and the like, or two or more of them can be used in any combination and ratio. .

Further, by using a polymer material that is gelled as a solvent of the electrolytic solution, the safety against liquid leakage and the like is enhanced. In addition, reduction in thickness and weight of the power storage device is possible. Representative examples of the polymer material to be gelled include silicone gel, acrylic gel, acrylonitrile gel, polyethylene oxide, polypropylene oxide, fluorine-based polymer and the like.

In addition, by using one or more ionic liquid (normal temperature molten salt) that is flame retardant and hardly volatile as a solvent of the electrolytic solution, the internal temperature rises due to internal short circuit of the power storage device, overcharge, etc. Also, the storage battery can be prevented from bursting or firing.

As the electrolytes dissolved in the above solvent, when using a lithium carrier ion, e.g. _{LiPF 6, LiClO 4, LiAsF 6} , LiBF 4, LiAlCl 4, Li
SCN, LiBr, LiI, Li ₂ SO ₄ , Li ₂ B ₁₀ Cl ₁₀ , Li ₂ B ₁₂ Cl _{1
2, LiCF 3 SO 3, LiC} 4 F 9 SO 3, LiC (CF 3 SO 2) 3, LiC (C 2
_{F 5 SO 2) 3, LiN} (CF 3 SO 2) 2, LiN (C 4 F 9 SO 2) (CF 3 SO 2
And lithium salts such as LiN (C ₂ F ₅ SO ₂ ) ₂ , or two or more of them in any combination and ratio.

[6.4. Separator]
As separators for power storage devices, cellulose, polypropylene (PP), polyethylene (P
E) Porous insulators such as polybutene, nylon, polyester, polysulfone, polyacrylonitrile, polyvinylidene fluoride and tetrafluoroethylene can be used.
In addition, non-woven fabric such as glass fiber, or a diaphragm in which glass fiber and polymer fiber are combined may be used.

[6.5. Non-aqueous secondary battery]
Next, the structure of the non-aqueous secondary battery will be described with reference to FIG. 19 and FIG.

[6.5. Coin type rechargeable battery]
FIG. 19A is an external view of a coin-type (single-layer flat-type) lithium ion secondary battery, and is a view partially showing the cross-sectional structure thereof.

In the coin-type secondary battery 950, a positive electrode can 951 also serving as a positive electrode terminal and a negative electrode can 952 serving as a negative electrode terminal are insulated and sealed by a gasket 953 formed of polypropylene or the like.
The positive electrode 954 includes a positive electrode current collector 955 and a positive electrode active material layer 956 provided to be in contact with the positive electrode current collector 955.
It is formed by The negative electrode 957 is formed of a negative electrode current collector 958 and a negative electrode active material layer 959 provided to be in contact with the negative electrode current collector 958. Positive electrode active material layer 956 and negative electrode active material layer 959
And a separator 960 and an electrolyte (not shown).

The negative electrode 957 includes a negative electrode active material layer 959 over a negative electrode current collector 958, and the positive electrode 954 includes a positive electrode active material layer 956 over a positive electrode current collector 955.

The above-described members can be used for the positive electrode 954, the negative electrode 957, the separator 960, and the electrolytic solution.

For the positive electrode can 951 and the negative electrode can 952, metals such as nickel, aluminum and titanium which are resistant to corrosion by the electrolytic solution, or alloys of these metals and alloys of these with other metals (for example, stainless steel etc.) It can be used. In addition, in order to prevent corrosion by the electrolytic solution, it is preferable to coat nickel, aluminum or the like. The positive electrode can 951 and the negative electrode can 952 are electrically connected to the positive electrode 954 and the negative electrode 957, respectively.

The negative electrode 957, the positive electrode 954, and the separator 960 are impregnated with an electrolyte, as shown in FIG.
As shown in the figure, the positive electrode can 951 is down and the positive electrode 954, the separator 960, the negative electrode 957, and the negative electrode can 952 are laminated in this order, and the positive electrode can 951 and the negative electrode can 952 are crimped through the gasket 953 to form a coin shape. The secondary battery 950 is manufactured.

[6.5.2. Thin secondary battery]
Next, an example of a thin secondary battery will be described with reference to FIG. Figure 19 (B)
In the following, for convenience of explanation, the internal structure is partially exposed and described.

A thin secondary battery 970 illustrated in FIG. 19B includes a positive electrode current collector 971 and a positive electrode active material layer 972.
And a negative electrode 976 having a negative electrode current collector 974 and a negative electrode active material layer 975, a separator 977, an electrolytic solution (not shown), and an exterior body 978. Exterior body 97
A separator 977 is provided between the positive electrode 973 and the negative electrode 976 which are provided in the space 8.
In addition, the inside of the exterior body 978 is filled with an electrolytic solution. Note that although one positive electrode 973, one negative electrode 976, and one separator 977 are used in FIG. 19B, a stacked secondary battery in which these are alternately stacked may be used.

The above-described members can be used for the positive electrode, the negative electrode, the separator, and the electrolytic solution (electrolyte and solvent).

In a thin secondary battery 970 shown in FIG. 19B, a positive electrode current collector 971 and a negative electrode current collector 9 are shown.
74 also serves as a terminal (tab) for obtaining an electrical contact with the outside. Therefore, the positive electrode current collector 971 and a part of the negative electrode current collector 974 are disposed so as to be exposed to the outside from the exterior body 978.

In the thin secondary battery 970, the exterior body 978 is a metal thin film excellent in flexibility such as aluminum, stainless steel, copper, nickel or the like on a film made of a material such as polyethylene, polypropylene, polycarbonate, ionomer, or polyamide. And a laminated film having a three-layer structure in which an insulating synthetic resin film such as a polyamide resin or a polyester resin is provided on the metal thin film as the outer surface of the outer package. With such a three-layer structure,
As well as blocking the permeation of the electrolytic solution and the gas, the insulating property is ensured, and at the same time, it has electrolytic solution resistance.

[6.5.3. Cylindrical secondary battery]
Next, an example of a cylindrical secondary battery will be described with reference to FIG. As shown in FIG. 20A, the cylindrical secondary battery 980 has a positive electrode cap (battery lid) 981 on the upper surface, and has a battery can (outer can) 982 on the side and bottom. The positive electrode cap and the battery can (outer can) 982 are insulated by a gasket (insulation packing) 990.

FIG. 20 (B) is a view schematically showing a cross section of a cylindrical secondary battery. Inside the hollow cylindrical battery can 982 is provided a battery element in which a strip-shaped positive electrode 984 and a negative electrode 986 are wound with a separator 985 interposed therebetween. Although not shown, the battery element is wound around the center pin. The battery can 982 is closed at one end and open at the other end.

The members described above can be used for the positive electrode 984, the negative electrode 986, and the separator 985.

For the battery can 982, a metal such as nickel, aluminum, titanium or the like having corrosion resistance to an electrolytic solution, or an alloy of these or an alloy of these with another metal (for example, stainless steel or the like) can be used. . In addition, in order to prevent corrosion by the electrolytic solution, it is preferable to coat nickel, aluminum or the like. Inside the battery can 982, the battery element in which the positive electrode, the negative electrode and the separator are wound is sandwiched by a pair of opposing insulating plates 988 and 989.

In addition, an electrolytic solution (not shown) is injected into the inside of the battery can 982 provided with the battery element. The above-described electrolyte and solvent can be used for the electrolytic solution.

In order to wind the positive electrode 984 and the negative electrode 986 used for the cylindrical secondary battery, active material layers are formed on both sides of the current collector. A positive electrode terminal (positive electrode current collection lead) 983 is connected to the positive electrode 984, and a negative electrode terminal (negative electrode current collection lead) 987 is connected to the negative electrode 986. Both the positive electrode terminal 983 and the negative electrode terminal 987 can be made of a metal material such as aluminum. Positive electrode terminal 983
And the negative electrode terminal 987 are resistance welded to the bottom of the battery can 982, respectively.
The safety valve mechanism 992 is a PTC (Positive Temperature Coeff).
It is electrically connected to the positive electrode cap 981 via the element 991. The safety valve mechanism 992 disconnects the electrical connection between the positive electrode cap 981 and the positive electrode 984 when the increase in internal pressure of the battery exceeds a predetermined threshold. The PTC element 991 is a heat sensitive resistance element whose resistance increases when the temperature rises, and the amount of current is limited by the increase of the resistance to prevent abnormal heat generation. A barium titanate (BaTiO ₃ ) -based semiconductor ceramic or the like can be used for the PTC element.

[6.5.4. Square secondary battery]
Next, an example of a square secondary battery will be described with reference to FIG. Figure 19 (C)
The wound body 993 shown in the drawing includes a negative electrode 994, a positive electrode 995, and a separator 996.
The wound body 993 is formed by winding the laminated sheet by laminating the negative electrode 994 and the positive electrode 995 with the separator 996 interposed therebetween. A rectangular secondary battery is formed by covering the wound body 993 with a rectangular sealing can or the like. Note that the number of stacked layers including the negative electrode 994, the positive electrode 995, and the separator 996 may be appropriately designed according to the necessary capacity and the device volume.

Similar to the cylindrical secondary battery, the negative electrode 994 is connected to the negative electrode tab (not shown) through one of the terminal 997 and the terminal 998, and the positive electrode 995 is connected to the positive electrode tab (the other through the terminal 997 and the terminal 998). Not shown). In addition, the peripheral structure such as the safety valve mechanism conforms to a cylindrical secondary battery.

As described above, coin-type, thin (also referred to as laminate-type), cylindrical and square secondary batteries have been shown as secondary batteries, but various other secondary batteries can be used. In addition, a structure in which a plurality of positive electrodes, a negative electrode, and a separator are stacked, or a structure in which a positive electrode, a negative electrode, and a separator are wound may be used.

[6.6. Lithium ion capacitor]
Next, a lithium ion capacitor which is an example of a power storage device will be described.

Lithium ion capacitor is an electric double layer capacitor (EDLC. Electric D
The hybrid capacitor is a hybrid capacitor in which a positive electrode of an ouble layer capacitor is combined with a negative electrode of a lithium ion secondary battery using a carbon material, and an asymmetric capacitor in which the storage principle of the positive electrode and the negative electrode is different. The positive electrode forms an electrical double layer and performs charge and discharge by physical action, whereas the negative electrode performs charge and discharge by chemical action of lithium. By using a negative electrode in which lithium is occluded in advance in the carbon material as the negative electrode active material, the energy density is dramatically improved as compared with the conventional electric double layer capacitor using activated carbon for the negative electrode.

The lithium ion capacitor may be replaced with a positive electrode active material layer of a lithium ion secondary battery, and a material capable of reversibly supporting at least one of lithium ion and anion may be used. As such a material, for example, activated carbon, conductive polymer, polyacene organic semiconductor (
PAS. PolyAcenic Semiconductor (abbreviated) and the like.

Lithium ion capacitors have high charge and discharge efficiency, can be rapidly charged and discharged, and have a long life after repeated use.

Such a lithium ion capacitor can be used for the power storage device of one embodiment of the present invention. Thereby, generation of irreversible capacity can be suppressed, and a power storage device with improved cycle characteristics can be manufactured.

Seventh Embodiment Storage system]
A structural example of the storage system will be described.

An example of the structure of the storage system is shown in FIG. The power storage system illustrated in FIG. 21A includes a plurality of power storage elements 810 and a circuit substrate 850 in a housing 800.

As the storage element 810, for example, the storage device described with reference to FIGS. 17 to 20 can be applied.

The circuit board 850 includes the control system described with reference to FIG. 7 including, for example, the chip 851. Examples of the chip 851 include the semiconductor circuit 246 shown in FIG.
Further, the circuit board 850 is connected to a connector 852 for connecting to an external device. The circuit board 850 is connected to, for example, a power supply or load by a connector 852.

As the circuit board 850, for example, a printed circuit board (PCB) can be used. When a printed circuit board is used as the circuit board 850, a control system is formed by mounting and connecting electronic components such as a resistive element, a capacitor such as a capacitor, a coil (inductor), and a semiconductor integrated circuit (IC) on the printed board. be able to. In addition to the above, various components such as a temperature detection element such as a thermistor, a fuse, a filter, a crystal oscillator, an EMC countermeasure component, and the like can be mounted as the electronic component.

Here, a circuit including a transistor can be used for the above-described semiconductor integrated circuit (IC). This makes it possible to significantly reduce the power consumption of the control system.

Further, as shown in FIG. 21B, the circuit board 850 includes a plurality of connection terminals 811 a and a plurality of connection terminals 811 b. The connection terminal 811 a and the connection terminal 811 b are provided for each storage element 810. Connection terminal 811 a is a connection terminal 81 of corresponding storage element 810.
Connected to 2a. Connection terminal 811 b is connected to connection terminal 812 b of corresponding storage element 810. At this time, the storage element 810 is connected to the control system provided on the circuit board 850 through the connection terminal 811 a and the connection terminal 811 b.

Note that an antenna 860 may be provided in the housing 800 as shown in FIG.

The antenna 860 can be used to transmit and receive power to and from a plurality of power storage elements 810 from the outside, for example. By electrically connecting the antenna 860 to the circuit substrate 850, exchange of power with the outside or exchange of signals can be controlled by the electric circuit.

Note that a plurality of antennas may be provided, or the antenna may not be provided.

Although FIG. 22 shows the case where the antenna 860 has a coil shape, the present invention is not limited to this. For example, the antenna 860 may have a linear or flat shape. Also, planar antennas, aperture antennas, traveling wave antennas,
An antenna such as an EH antenna, a magnetic field antenna, or a dielectric antenna may be used.

Note that an electromagnetic induction method, a magnetic resonance method, a radio wave method, or the like can be used for wireless transmission and reception of power (also referred to as contactless power transmission, contactless power transmission, or wireless power feeding).

In addition, the housing 800 may have a function of preventing shielding of an electric field or a magnetic field by the storage element 810. In this case, for example, a magnetic body can be used for the housing 800.

As shown in FIG. 21 and FIG. 22, a storage system can be configured. Thereby, for example, deterioration of the power storage device used in the power storage system can be prevented.

Eighth Embodiment Electrical equipment]
The power storage device according to one embodiment of the present invention can be used for various electric devices.

[8.1. Category of Electrical Equipment]
Here, the term "electrical device" refers to an industrial product including a portion that operates by the power of electricity. The electric devices are not limited to household appliances such as household appliances, but various applications such as business, industrial, military, etc. are widely included in this category.

[8.2. Example of electrical equipment]
Examples of the electric device using the power storage device according to one embodiment of the present invention include a display device such as a television or a monitor, a lighting device, a desktop computer or a notebook personal computer, a word processor, a DVD (Digital Versatile Disc) Image playback apparatus for playing back still images or moving images stored in a recording medium, CD (Compact Disc)
Portable or stationary audio reproduction devices such as players and digital audio players, portable or stationary radio receivers, recording and reproduction devices such as tape recorders and IC recorders (voice recorders), headphone stereos, stereos, remote controllers, Clocks such as clocks and wall clocks, cordless handsets, transceivers, mobile phones, car phones, portable or stationary game machines, pedometers, calculators, portable information terminals, electronic notebooks, electronic books, electronic translators, microphones Voice input devices such as stills and cameras, cameras such as video cameras, toys, electric shavers, high-frequency heating devices such as electric toothbrushes and microwaves, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, fans, hair Air conditioners such as dryers, humidifiers, dehumidifiers and air conditioners, dishwashers, dishware drying , Clothes dryer, bed dryer, electric refrigerator, electric freezer, electric refrigerator-freezer, DNA storage freezer, flashlight, electric tool, smoke detector, hearing aid, cardiac pacemaker, portable X-ray imaging device, radiation measuring instrument, Examples include health devices such as an electric massager and a dialysis device and medical devices. In addition, guide lights, traffic lights, measuring instruments such as gas meters and water meters, belt conveyors, elevators, escalators, vending machines, automatic ticket vending machines, cash dispensers (CD; abbreviation for Cash Dispenser) and cash dispensers ( ATM.
Industrial equipment such as AutoMated Teller Machine), digital signage (electronic signboard), industrial robots, wireless relay stations, mobile phone base stations, power storage systems, power leveling and storage devices for smart grids. It can be mentioned. In addition, moving objects (transporters) and the like that are propelled by a motor using electric power from a power storage device are also included in the category of electrical devices. For example, an electric vehicle (EV), a hybrid vehicle (HEV) having a combination of an internal combustion engine and a motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an endless track, an agricultural machine Motorized bicycles including motor-assisted bicycles, motorbikes, motorized wheelchairs, motorized carts, small or large ships, submarines, aircrafts such as fixed wing aircraft and rotary wing aircraft, rockets, artificial satellites, space probes and planet probes A spacecraft etc. are mentioned.

Note that the above-described electric device can use the power storage device according to one embodiment of the present invention as a main power source for covering almost all of the power consumption. In addition, the electric device is a power storage device according to one aspect of the present invention as an uninterruptible power supply capable of supplying power to the electric device when the supply of power from the main power source or the commercial power source is stopped. It can be used. Alternatively, the electrical device
The power storage device according to one embodiment of the present invention can be used as an auxiliary power supply for supplying power to an electric device in parallel with the supply of power from the main power supply or the commercial power supply to the electric device.

[8.3. Example of power system network]
The electric devices described above are not limited to the case where the power storage devices are individually mounted, and a power system network (power network) in which a plurality of electric devices, the power storage devices, and a control device for controlling the power system are connected by wire or wirelessly. May be formed. By controlling the power system network with the control device, it is possible to improve the power use efficiency in the entire network.

FIG. 23A shows a HEM in which a plurality of home appliances, a control device, a power storage device, and the like are connected in a house.
S (Home energy management system. Home Energy Management
An example of System) is shown. Such a system makes it possible to easily grasp the power consumption of the entire house. In addition, the operation of a plurality of home appliances can be remotely controlled. In addition, in the case of automatically controlling a home appliance using a sensor or a control device, it can also contribute to saving of power.

The distribution board 8003 installed in the house 8000 has a power grid 800 via a lead-in wire 8002.
Connected to 1 The distribution board 8003 supplies AC power, which is commercial power supplied from the lead-in wire 8002, to each of a plurality of home appliances. Control device 8004 is a distribution board 8
While being connected to 003, it is connected to a plurality of home appliances, a storage system 8005, a solar power generation system 8006 and the like. In addition, the control device 8004 can be parked outside the house 8000 or the like, and can also be connected to an electric vehicle 8012 independent of the distribution board 8003.

The control device 8004 connects a distribution board 8003 and a plurality of home appliances to form a network, and controls a plurality of home appliances connected to the network.

Also, the control device 8004 is connected to the Internet 8011, and the Internet 801.
It is possible to connect with the management server 8013 via 1. The management server 8013 can receive the power usage status of the user and build a database, and can provide various services to the user based on the database. Also, management server 8013
For example, it is possible to provide the user with charge information of power according to the time zone as needed, and the control device 8004 can also set an optimum usage pattern in the house 8000 based on the information.

For example, the plurality of home appliances include the display device 8007 and the lighting device 8008 illustrated in FIG.
Although the air conditioning equipment 8009 and the electric refrigerator 8010 are, of course, not limited thereto, they indicate all electric devices that can be installed in a house, such as the electric devices described above.

For example, the display device 8007 includes a liquid crystal display device, an organic EL (Electro Lu
light-emitting device provided with a light-emitting element such as a light-emitting element such as a light-emitting element, etc., an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Pl
asma Display Panel), FED (Field Emission D)
A semiconductor display device such as isplay) is incorporated, and includes one that functions as a display device for displaying information, such as for personal computers, for displaying advertisements, as well as for receiving TV broadcasts.

In addition, the lighting device 8008 includes an artificial light source that artificially obtains light using electric power, and as the artificial light source, a discharge lamp such as an incandescent lamp or a fluorescent lamp, an LED (Light Emi
A light emitting element such as tting diode) or an organic EL element can be used. Figure 23
Although the lighting device 8008 shown in (A) is installed on a ceiling, it may be an installation type provided on a wall surface, a floor, a window, or the like, or a desktop type.

In addition, the air conditioning facility 8009 has a function of adjusting the indoor environment such as temperature, humidity, and air cleanliness. FIG. 23A shows an air conditioner as an example. The air conditioner includes an indoor unit in which a compressor and an evaporator are integrated, an outdoor unit (not shown) in which a condenser is built in, an unit in which these are integrated, and the like.

The electric refrigerator 8010 is an electric device for storing food products and the like at a low temperature, and includes a freezer for freezing at 0 ° C. or lower. The inside of the electric refrigerator 8010 is cooled by removing heat when the refrigerant in the pipe compressed by the compressor is vaporized.

Each of the plurality of home appliances may have a power storage device, or may use the power of the power storage system 8005 or the power from a commercial power source without the power storage device. When the home electric appliance has a power storage device inside, even if power supply from the commercial power source can not be received due to a power failure or the like, the home electric appliance can be used by using the power storage device as an uninterruptible power source It becomes.

Power detection means such as a current sensor can be provided in the vicinity of the power supply terminals of the above-described home appliances. By transmitting the information detected by the power detection means to the control device 8004, the user can grasp the power consumption of the whole house, and based on the information, the control device 8004 sends a plurality of home appliances. The distribution of power can be set to provide efficient or economical use of power within the home 8000.

Also, in the time zone where the power usage rate is low among the total power that can be supplied by the commercial power supply source,
The storage system 8005 can be charged from a commercial power supply. Further, the solar storage system 8006 can charge the storage system 8005 during the daytime. A target to be charged is not limited to the storage system 8005, and may be a storage device mounted on an electric vehicle 8012 connected to the control device 8004, or may be a storage device included in a plurality of home appliances.

In this manner, efficient and economical use of power can be performed in the house 8000 by the control device 8004 efficiently allocating and using the power charged in various power storage devices.

As described above, a domestic-scale power network has been shown as an example of controlling the power system by networking, but the present invention is not limited to this. A city-scale or national-scale power network combining control functions and communication functions such as smart meters ( You can also build a smart grid. In addition, it is possible to construct a microgrid consisting of an energy supply source and a consumer facility at the scale of a factory or business site.

[8.4. Example of electric device (example of electric car)]
Next, an example of a mobile object as an example of the electric device will be described with reference to FIGS. 23B and 23C. The power storage device according to one embodiment of the present invention can be used as a power storage device for controlling a mobile body.

FIG. 23B shows an example of the internal structure of the electric vehicle. The electric car 8020
A chargeable / dischargeable power storage device 8024 is mounted. The power of the power storage device 8024 is referred to as an electronic control unit 8025 (also referred to as an ECU. Electronic Control Uni
The output is adjusted by the abbreviation of t) and supplied to the traveling motor unit 8027 via the inverter unit 8026. The inverter unit 8026 can convert DC power input from the power storage device 8024 into three-phase AC power, and can adjust the voltage, current and frequency of the converted AC power and output it to the traveling motor unit 8027.

Therefore, when the driver depresses the accelerator pedal (not shown), the traveling motor unit 8027 operates, and the torque generated by the traveling motor unit 8027 becomes the output shaft 8028 and the drive shaft 802.
It is transmitted to the rear wheel (drive wheel) 8030 through 9. The electric vehicle 8020 can be driven to travel by driving the front wheel 8023 together in accordance with this.

Each unit is provided with detection means such as, for example, a voltage sensor, a current sensor, a temperature sensor, etc.
The physical quantities at each part of the electric vehicle 8020 are appropriately monitored.

The electronic control unit 8025 is a processing device having a memory such as a RAM and a ROM (not shown) and a CPU. The electronic control unit 8025 is an operation information such as acceleration, deceleration, and stop of the electric vehicle 8020, traveling environment and temperature information of each unit, control information, charge state of the power storage device (SOC
And the like, based on the input information such as
The control signal is output to power storage device 8024. Various data and programs are stored in the memory.

The traveling motor unit 8027 can be used by combining a DC motor or these motors and an internal combustion engine, in addition to the AC motor.

Needless to say, as long as the power storage device according to one embodiment of the present invention is included, the mobile object is not particularly limited to the above.

The power storage device 8024 mounted on the electric vehicle 8020 can be charged by receiving power supply from an external charging facility by a plug-in method, a non-contact power feeding method, or the like. In FIG. 23C, a power storage device 8024 mounted on an electric vehicle 8020 from a ground-mounted charging device 8021.
Shows a state in which charging is performed via the cable 8022. At the time of charging, the charging method and the standard of the connector may be appropriately performed by a predetermined method such as CHAdeMO (registered trademark). The charging device 8021 may be a charging station provided in a commercial facility, or may be a home power source. For example, connection plug 8 connected to power storage device 8024 shown in FIG.
According to the plug-in technology of electrically connecting 031 with the charging device 8021, the power storage device 8024 mounted on the electric vehicle 8020 can be charged by external power supply. The charging can be performed by converting it into a DC constant voltage having a constant voltage value through a converter such as an AC / DC converter.

Further, although not shown, the power receiving device may be mounted on a moving body, and power may be supplied contactlessly from the ground power transmitting device for charging. In the case of this non-contact power feeding method, charging can be performed not only while the vehicle is stopped but also while it is traveling by incorporating the power transmission device on the road or the outer wall. In addition, power may be transmitted and received between moving bodies using this method of non-contact power feeding. Furthermore, a solar cell may be provided in the exterior of the moving body, and charging of power storage device 8024 may be performed when the vehicle is stopped or traveling. For such non-contact power supply, an electromagnetic induction method or a magnetic resonance method can be used.

In addition, when a mobile body is an electric vehicle for railways, the electrical storage apparatus mounted can be charged by the electric power supply from an overhead wire or a conductive rail.

When the power storage device according to one embodiment of the present invention is mounted as the power storage device 8024, cycle characteristics of the power storage device can be favorable and convenience can be improved. In addition, a power storage device 8024
If the power storage device 8024 can be reduced in size and weight by the improvement of the characteristics of the above, the fuel consumption can be improved because it contributes to the weight reduction of the vehicle. In addition, since the power storage device 8024 mounted on a moving body has a relatively large capacity, it can also be used as a power supply source such as indoors. In this case, it is possible to avoid using a commercial power supply at the peak of the power demand.

[8.5. Example of electric device (example of portable information terminal)]
Furthermore, an example of a portable information terminal as an example of the electric device will be described with reference to FIG.

FIG. 24A is a perspective view showing the front and the side of the portable information terminal 8040. FIG. As an example, the portable information terminal 8040 can execute various applications such as mobile telephone, electronic mail, text browsing and creation, music reproduction, Internet communication, computer games, and the like. A portable information terminal 8040 has a display portion 8042, a camera 8045, a microphone 8046, and a speaker 8047 on the front of a housing 8041, and has a button 8043 for operation on the left side of the housing 8041 and a connection terminal 8048 on the bottom .

For the display portion 8042, a display module or a display panel is used. As a display module or display panel, a light emitting device including a light emitting element represented by an organic light emitting element (OLED) in each pixel, a liquid crystal display device, electronic paper for displaying by electrophoretic method, electronic powder fluid method, or the like
DMD (Digital Micromirror Device), PDP (Plass
ma Display Panel), FED (Field Emission Dis)
play), SED (Surface Conduction Electron-em
bitter Display), LED (Light Emitting Diode)
Displays, carbon nanotube displays, nanocrystal displays, quantum dot displays, etc. can be used.

Although a portable information terminal 8040 shown in FIG. 24A is an example in which one display portion 8042 is provided in a housing 8041, the present invention is not limited to this. The display portion 8042 may be provided on the back surface of the portable information terminal 8040 Alternatively, two or more display units may be provided as a foldable portable information terminal.

Further, the display portion 8042 is provided with a touch panel which can input information by an instruction unit such as a finger or a stylus as an input unit. Thus, the icon 8044 displayed on the display unit 8042 can be easily operated by the instruction unit. In addition, since the area for arranging the keyboard in the portable information terminal 8040 becomes unnecessary due to the arrangement of the touch panel, the display portion can be arranged in a wide area. In addition, since information can be input using a finger or a stylus, a user-friendly interface can be realized. As the touch panel, various methods such as a resistive film method, a capacitance method, an infrared method, an electromagnetic induction method, a surface acoustic wave method and the like can be adopted, but since the display portion 8042 is curved, the resistance is particularly high. It is preferable to use a membrane method or a capacitance method. In addition, such a touch panel may be of a so-called in-cell type combined with the above-described display module or display panel as one unit.

Further, the touch panel may function as an image sensor. In this case, personal identification can be performed, for example, by touching the display portion 8042 with a palm or finger to capture a palm print, a fingerprint, or the like. In addition, when a backlight which emits near-infrared light or a sensing light source which emits near-infrared light is used for the display portion 8042, an image of a finger vein, a palm vein, or the like can be taken.

In addition, a keyboard may be provided in the display portion 8042 without providing a touch panel, or both of the touch panel and the keyboard may be provided.

The operation button 8043 can have various functions in accordance with the application. For example, the home screen may be displayed on the display portion 8042 by using the button 8043 as a home button and pressing the button 8043. Alternatively, the main power supply of the portable information terminal 8040 may be turned off by pressing the button 8043 for a predetermined time. In addition, when transitioning to the sleep mode state, the button 8043 may be pressed to recover from the sleep mode state. In addition, it can be used as a switch for activating various functions by, for example, keeping pressing and pressing simultaneously with other buttons.

Alternatively, the button 8043 may be a volume adjustment button or a mute button, and may have a function of adjusting the volume of the speaker 8047 for sound output. From the speaker 8047, various sounds such as sounds set during specific processing such as startup sound of operating system (OS), sounds by sound files executed in various applications such as music from music playback application software, ring tones of e-mail, etc. Output Although not shown, a connector for outputting sound to a device such as a headphone, an earphone, or a headset may be provided in place of the speaker 8047 or in place of the speaker 8047.

Thus, the button 8043 can be provided with various functions. In FIG. 24 (A),
Although the portable information terminal 8040 in which two buttons 8043 are provided on the left side is shown, it goes without saying that the number of buttons 8043 and the arrangement position thereof are not limited to this and can be designed appropriately.

The microphone 8046 can be used for voice input and recording. Also, the camera 804
The display unit 8042 can display the image acquired by the step S5.

In addition to the touch panel and button 8043 provided in the display portion 8042 described above, the operation of the mobile information terminal 8040 uses the camera 8045, a sensor incorporated in the mobile information terminal 8040, and the like to recognize the user's operation (gesture) It is also possible to perform an operation (called a gesture input). Alternatively, the microphone 8046 can be used to recognize the user's voice and perform an operation (referred to as voice input). As described above, the operability of the portable information terminal 8040 can be further improved by implementing the NUI (Natural User Interface) technology for inputting to the electric device by natural human behavior.

The connection terminal 8048 is an input terminal for signals for communication with an external device and power for power supply. For example, in order to drive an external memory in the portable information terminal 8040, the connection terminal 80
48 can be used. As an external memory drive, for example, an external HDD (hard disk drive), a flash memory drive, a DVD (Digital Versat)
ile Disk) drive and DVD-R (DVD-Recordable) drive,
DVD-RW (DVD-ReWritable) drive, CD (Compact Dire)
sc) drive, CD-R (Compact Disc Recordable) drive, CD-RW (Compact Disc Rewritable) drive, MO
Magneto-Optical Disc drive, FDD (Floppy Di)
sk Drive or other non-volatile solid state drive (Solid St)
recording media drives such as ate Drive (SSD) devices. In addition, although the portable information terminal 8040 has a touch panel on the display portion 8042, a keyboard may be provided on the housing 8041 instead, or a keyboard may be externally attached.

Although FIG. 24A illustrates a portable information terminal 8040 in which one connection terminal 8048 is provided on the bottom surface, the number and arrangement position of the connection terminals 8048 are not limited to this, and can be appropriately designed. .

FIG. 24B is a perspective view showing the back and the side of the portable information terminal 8040. A portable information terminal 8040 has a solar cell 8049 and a camera 8050 on the surface of a housing 8041, and further has a charge / discharge control circuit 8051, a power storage device 8052, a DCDC converter 8053, and the like. Note that in FIG. 24B, as an example of the charge and discharge control circuit 8051, a power storage device 8052, DC can be used.
The structure including the DC converter 8053 is shown, and the power storage device according to one embodiment of the present invention described in the above embodiment is used as the power storage device 8052.

Electric power can be supplied to the display portion, the touch panel, the video signal processing portion, or the like by the solar battery 8049 mounted on the back surface of the portable information terminal 8040. Note that the solar cell 8049 can be provided on one side or both sides of the housing 8041. By mounting the solar cell 8049 in the portable information terminal 8040, the power storage device 8052 of the portable information terminal 8040 can be charged even in a place where there is no means for supplying power such as outdoor.

As the solar cell 8049, single crystal silicon, polycrystalline silicon, microcrystalline silicon,
Amorphous silicon or silicon-based solar cells made of stacked layers of these, InGaAs-based, G
aAs-based, CIS-based, Cu ₂ ZnSnS ₄ , CdTe-CdS-based solar cells, dye-sensitized solar cells using organic dyes, organic thin-film solar cells using conductive polymers or fullerenes, p
A quantum dot type solar cell or the like in which a quantum dot structure of silicon or the like is formed in the i layer in the in structure can be used.

Here, an example of a structure and operation of the charge and discharge control circuit 8051 illustrated in FIG. 24B will be described with reference to a block diagram illustrated in FIG.

A solar cell 8049, a power storage device 8052, a DCDC converter 8053 are illustrated in FIG.
, The converter 8057, the switch 8054, the switch 8055, the switch 8056, and the display portion 8042, and the power storage device 8052, the DCDC converter 8053, the converter 8057, the switch 8054, the switch 8055, and the switch 8056 are shown in FIG.
It corresponds to the charge / discharge control circuit 8051 shown in B).

The electric power generated by the solar cell 8049 by the outside light is boosted or lowered by the DCDC converter 8053 to obtain a voltage necessary to charge the power storage device 8052. When the power from the solar cell 8049 is used for the operation of the display portion 8042, the switch 8054 is used.
Is turned on, and the converter 8057 boosts or steps down the voltage required for the display portion 8042. When display on the display portion 8042 is not performed, the switch 8054 is turned off and the switch 8055 is turned on to charge the power storage device 8052.

Although the solar cell 8049 is shown as an example of the power generation means, the present invention is not limited to this, and charging of the power storage device 8052 is performed using other power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). You may go. Further, the method for charging the power storage device 8052 of the portable information terminal 8040 is not limited to this. For example, the connection terminal 8048 described above may be connected to a power supply to perform charging. Alternatively, a non-contact power transmission module may be used which wirelessly transmits and receives power to charge the battery, or the above charging methods may be combined.

Here, the state of charge of the power storage device 8052 (SOC: abbreviation of State Of Charge)
Is displayed on the upper left of the display portion 8042 (within the dashed line frame). Accordingly, the user can grasp the charge state of power storage device 8052, and can accordingly select portable information terminal 8040 as a power saving mode. When the user selects the power saving mode, the user operates, for example, the button 8043 or the icon 8044 described above to configure a display module or display panel mounted on the portable information terminal 8040, an arithmetic device such as a CPU, a memory, etc. The part can be switched to the power saving mode. Specifically, stopping at each of these components reduces the frequency of use of any function. In the power saving mode, it may be configured to automatically switch to the power saving mode according to the setting according to the charge state. In addition, by providing detection means such as an optical sensor in the portable information terminal 8040 and detecting the amount of external light when using the portable information terminal 8040 to optimize display luminance, power consumption of the power storage device 8052 can be reduced. be able to.

In addition, at the time of charging by the solar battery 8049 or the like, as illustrated in FIG.
An image etc. showing it may be displayed on the upper left of 2 (within the broken line frame).

Needless to say, the device is not limited to the electric device illustrated in FIG. 24 as long as the power storage device according to one embodiment of the present invention is included.

[8.6. Example of electrical device (example of power storage system)]
Further, an example of a power storage system as an example of the electric device will be described with reference to FIG.
The storage system 8100 described here can be used at home as the storage system 8005 described above. Moreover, although the household electrical storage system is demonstrated as an example here, it is not restricted to this, It can use for business use or another use.

As shown in FIG. 25, the storage system 8100 has a plug 8101 for electrically connecting to the system power supply 8103. Power storage system 8100 is electrically connected to distribution board 8104 provided in the home.

Further, the storage system 8100 may have a display panel 8102 or the like for indicating an operation state or the like. The display panel may have a touch screen. In addition to the display panel, a switch for turning on and off the main power supply, a switch for operating the storage system, and the like may be included.

Although not shown, in order to operate the storage system 8100, for example, an operation switch may be provided on a wall of the room separately from the storage system 8100. Alternatively, storage system 810
Alternatively, the storage system 8100 may be operated indirectly by connecting it to a personal computer, a server, or the like provided in the home. Furthermore, the storage system 8100 may be remotely operated using an information terminal such as a smartphone or the Internet. In these cases, a mechanism may be provided in the storage system 8100 for performing communication with the storage system 8100 and the other devices in a wired or wireless manner.

Power storage system 8100 includes, for example, a plurality of power storage elements shown in FIG. 21 and a control system.

The control system has a function of monitoring and controlling the states of the plurality of storage elements and capable of protecting the storage elements. Specifically, the control system includes: cell voltage of storage element, collection of cell temperature data, monitoring of overcharge and overdischarge, monitoring of over current, cell balancer control, management of battery deterioration state, battery remaining amount ((charge rate ) Calculation calculation of State Of Charge (SOC), control of the cooling fan of the drive storage device, control of failure detection, and the like.

Note that charging of the storage system 8100 is not limited to the system power supply 8103 described above, and for example, power may be supplied from a solar power generation system installed outdoors, or may be supplied from a storage system mounted on an electric vehicle .

DESCRIPTION OF SYMBOLS 10_1 storage element 10_2 storage element 10_3 storage element 11 switch 11a switch 12b switch 12a switch 12b switch 13 switch 13a switch 13b switch 20_1 storage element 20_2 storage element 20_3 storage element 21 switch 21a switch 21b switch 22b switch 22a switch 22b switch 23 switch 23a switch 23b switch 30_1 storage element 30_2 storage element 30_3 storage element 31 switch 31a switch 31b switch 32 switch 32a switch 32b switch 33 switch 33 switch 33 switch 33 switch 33 switch 33 switch switch 51 switch 61 switch 61 switch 71 connection terminal 71 a connection terminal 71 b connection terminal 72 connection Terminal 72a Connection Terminal 72b Connection Terminal 91 Power supply 92 Load 100_1 Cell 100_2 Cell 100_3 Cell 200 Circuit 201 Connection terminal 201a Connection terminal 201b Connection terminal 202 Connection terminal 202a Connection terminal 202b Connection terminal 203 Connection terminal 203a Connection terminal 203b Connection terminal 204 Connection terminal 204a Connection terminal 204a Connection terminal 204b Connection terminal 240 Encoder 241_1 Inverter 241_2 Inverter 241_3 Inverter 241_4 Inverter 243 Logic circuit 244 Resistance element 246 Current detection circuit 246 Semiconductor circuit 247 Logic circuit 251 Transistor 252 Transistor 400 Substrate 401 Gate electrode 402 Gate insulating film 403 n-type region 404 Oxide film 405a Source electrode 405b Drain Electrode 406 Insulating film 408 Insulating film 409 Gate insulating film 410 Gate electrode 421 Transistor 422 Transistor 423 Transistor 631 Transistor 632 Transistor 633 Transistor 635 Transistor 636 Inverter 637 Capacitive element 651 Memory circuit 652 Memory circuit 652 Selector 654 Selector 701 Unit 702 Unit 703 Unit 704 Unit 710 Processor 711 Bus bridge 712 Memory 713 Memory interface 715 Clock generation circuit 720 controller 721 controller 722 I / O interface 730 power gate unit 731 switch 732 switch 740 clock generation circuit 741 crystal oscillation circuit 742 oscillator 743 crystal oscillator 745 timer circuit 746 I / O interface 750 I / O port 751 comparator 752 I O interface 761 bus line 762 bus line 763 bus line 764 data bus line 770 connection terminal 771 connection terminal 772 connection terminal 773 connection terminal 774 connection terminal 775 connection terminal 776 connection terminal 780 register 783 register 784 register 785 register 786 register 787 register 800 housing Body 810 storage element 811a connection terminal 811b connection terminal 812a connection terminal 812b connection terminal 850 circuit board 851 chip 852 connector 860 antenna 993 wound body 950 secondary battery 951 positive electrode can 952 negative electrode can 953 gasket 954 positive electrode 955 positive current collector 956 positive electrode Active material layer 957 Negative electrode 958 Negative electrode current collector 959 Negative electrode active material layer 960 Separator 970 Secondary battery 971 Positive electrode current collector 972 Positive electrode active material layer 973 Anode 974 Anode current collector 975 Anode active material layer 976 Anode 977 Separator 978 Package 980 Secondary battery 981 Cathode 981 Battery can 983 Cathode terminal 984 Cathode 985 Separator 986 Anode 987 Anode terminal 988 Insulating plate 989 Insulating plate 991 PTC element 992 Safety valve mechanism 994 negative electrode 995 positive electrode 996 separator 997 terminal 998 terminal 3004 logic circuit 3400 a memory cell array 3400 n memory cell array 6000 positive electrode 6001 positive electrode current collector 6002 positive electrode active material layer 6003 positive electrode active material 6004 graphene 6005 binder 6100 binder 6100 negative electrode current collector 6102 negative electrode Active material layer 6103 Negative electrode active material 6104 Film 6105 Binder 8000 House 8001 Power grid 8002 Line 8003 Distribution board 8004 Controller 8005 Electric system 8006 Photovoltaic system 8007 Display 8008 Lighting system 8009 Air conditioning equipment 8010 Electric refrigerator 8011 Internet 8012 Electric car 8013 Management server 8020 Electric car 8021 Charging device 8022 Cable 8023 Front wheel 8024 Storage device 8025 Electronic control unit 8026 Inverter unit 8027 Traveling Motor unit 8028 Output shaft 8029 Drive shaft 8031 Connection plug 8040 Portable information terminal 8041 Case 8042 Button 8044 Icon 8045 Camera 8046 Microphone 8047 Speaker 8048 Connection terminal 8049 Solar battery 8050 Camera 8051 Charge / discharge control circuit 8052 Power storage device 8053 DC DC converter 8054 Switch 8055 Switch 8056 Switch 8057 Converter 8100 Power storage system 8101 Plug 8102 Display panel 8103 System power supply 8104 Distribution board

Claims (1)

At least a first assembled battery to a fourth assembled battery;
At least a first switch to an eighth switch;
The ninth switch,
And a tenth switch,
Each of the first to eighth switches and the ninth and tenth switches connect each of the first to fourth assembled batteries in parallel, or Has a function to select or connect in series,
Each of the first to eighth switches includes a first input / output terminal, a second input / output terminal, a third input / output terminal, a first control terminal, and a second control. A terminal, a first transistor, and a second transistor,
One of the source and the drain of the first transistor is electrically connected to the first input / output terminal,
The other of the source and the drain of the first transistor is electrically connected to the second input / output terminal,
The gate of the first transistor is electrically connected to the first control terminal,
One of the source or the drain of the second transistor is electrically connected to the third input / output terminal,
The other of the source and the drain of the second transistor is electrically connected to the second input / output terminal,
The gate of the second transistor is electrically connected to the second control terminal,
The second input / output terminal of the first switch is electrically connected to the positive electrode of the first assembled battery,
The second input / output terminal of the second switch is electrically connected to the negative electrode of the first assembled battery,
The second input / output terminal of the third switch is electrically connected to the positive electrode of the second assembled battery,
The second input / output terminal of the fourth switch is electrically connected to the negative electrode of the second assembled battery,
The second input / output terminal of the fifth switch is electrically connected to the positive electrode of the third assembled battery,
The second input / output terminal of the sixth switch is electrically connected to the negative electrode of the third assembled battery,
The second input / output terminal of the seventh switch is electrically connected to the positive electrode of the fourth assembled battery,
The second input / output terminal of the eighth switch is electrically connected to the negative electrode of the fourth assembled battery,
One of the source or drain of the transistor included in the ninth switch is electrically connected to the third input / output terminal of the second switch and the third input / output terminal of the fourth switch And
The other of the source and the drain of the transistor of the ninth switch is electrically connected to the third input / output terminal of the fifth switch and the third input / output terminal of the seventh switch And
One of the source and the drain of the transistor of the tenth switch is electrically connected to the third input / output terminal of the first switch and the third input / output terminal of the third switch And
The other of the source and the drain of the transistor included in the tenth switch is electrically connected to the third input / output terminal of the fifth switch and the third input / output terminal of the seventh switch And
Charging of the first to fourth assembled batteries is performed in the parallel connection.
A control system of a power storage device, wherein the discharging of the first to fourth assembled batteries is performed in the series connection.

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