JP6501789B2 - マルチスレッディングの動的有効化のためのコンピュータ・システム、コンピュータ実装方法およびコンピュータ・プログラム製品 - Google Patents
マルチスレッディングの動的有効化のためのコンピュータ・システム、コンピュータ実装方法およびコンピュータ・プログラム製品 Download PDFInfo
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Description
キー動作の結果としてマルチスレッディング機構が無効化される場合、非ゼロスレッド識別情報を有するすべてのCPUのアーキテクテッド・レジスタ・コンテキストを保持することができる。クリア・リセットの介在なしにマルチスレッディング機構が後で再度有効化される場合、非ゼロのスレッド識別情報を有するすべてのCPUのアーキテクテッド・レジスタ・コンテキストが復元される。
Claims (20)
- コンピュータ・システムであって、
シングル・スレッド(ST)モードとマルチスレッディング(MT)モードとの間で切換え構成可能なコアを含む構成であって、前記STモードは一次スレッドを扱い、前記MTモードは前記一次スレッドと前記コアの共用資源上の1つまたは複数の二次スレッドとを扱う、前記構成と、
前記構成を制御して方法を実行するように構成されたマルチスレッディング機構とを含み、
前記方法は、
前記STモードで前記一次スレッドにおいてMTモード設定命令を実行することと、
前記MTモード設定命令によって指定された記憶場所から要求スレッド数を取得することと、
前記要求スレッド数が複数のスレッドを示すとの判断に基づいて、前記一次スレッドと前記1つまたは複数の二次スレッドとを含む前記複数のスレッドを実行するために前記MTモードを有効化することとを含む、コンピュータ・システム。 - 前記MTモード設定命令はオペレーティング・システムからのシグナル・プロセッサ(SIGP)命令であり、前記SIGP命令はMT設定命令(order)と、前記要求スレッド数に関連づけられたプログラム指定最大スレッドid(PSMTID)とを含む、請求項1に記載のコンピュータ・システム。
- 前記PSMTIDが非ゼロ値である前記MT設定命令(order)の実行に基づいて、前記MTモードを有効化することと、
前記PSMTIDがゼロ値である前記MT設定命令(order)の実行に基づいて、前記STモードを維持するとともに前記MTモードの有効化を防止することとをさらに含む、請求項2に記載のコンピュータ・システム。 - 前記MT設定命令(order)が、無効な命令(order)と、不正な状態と、無効なパラメータとのうちの1つまたは複数とともに発行されたとの判断に基づいて、エラー標識が出力されるとともに前記MTモードの有効化が防止される、請求項3に記載のコンピュータ・システム。
- 前記構成のリセットまたは非活動化に基づいて前記MTモードが無効化され、1つまたは複数の二次スレッド・コンテキストと直前設定PSMTIDとが、非クリア・リセットの場合には保持され、クリア・リセットの場合にはゼロにされる、請求項2に記載のコンピュータ・システム。
- 前記構成の前記リセットまたは前記非活動化または起動時に、前記構成がデフォルトの前記STモードになる、請求項5に記載のコンピュータ・システム。
- サービス呼出し(SERVC)命令またはシステム情報ストア(STSI)命令に対する応答に基づいて、最大スレッドidの標識が実行プログラムに提供される、請求項1に記載のコンピュータ・システム。
- 複数の構成をさらに含み、前記コンピュータ・システムの前記構成のそれぞれが、同時に有効化された異なる数のスレッドを前記構成のそれぞれでサポートするために、異なる数の最大スレッドidを備えて構成され得る、請求項1に記載のコンピュータ・システム。
- シングル・スレッド(ST)モードとマルチスレッディング(MT)モードとの間で切換え構成可能なコアを含む構成におけるマルチスレッディングの動的有効化のためのコンピュータ実装方法であって、前記STモードは一次スレッドを扱い、前記MTモードは前記一次スレッドと前記コアの共用資源上の1つまたは複数の二次スレッドとを扱い、前記方法は、
前記STモードで前記一次スレッドにおいてMTモード設定命令を実行することと、
前記MTモード設定命令によって指定された記憶場所から要求スレッド数を取得することと、
前記要求スレッド数が複数のスレッドを示すとの判断に基づいて、前記一次スレッドと前記1つまたは複数の二次スレッドとを含む前記複数のスレッドを実行するために前記MTモードを有効化することとを含む、コンピュータ実装方法。 - 前記MTモード設定命令はオペレーティング・システムからのシグナル・プロセッサ(SIGP)命令であり、前記SIGP命令はMT設定命令(order)と、前記要求スレッド数に関連づけられたプログラム指定最大スレッドid(PSMTID)とを含む、請求項9に記載の方法。
- 前記PSMTIDが非ゼロ値である前記MT設定命令(order)の実行に基づいて、前記MTモードを有効化することと、
前記PSMTIDがゼロ値である前記MT設定命令(order)の実行に基づいて、前記STモードを維持するとともに前記MTモードの有効化を防止することとをさらに含む、
請求項10に記載の方法。 - 前記MT設定命令(order)が、無効な命令(order)と、不正な状態と、無効なパラメータとのうちの1つまたは複数とともに発行されたとの判断に基づいて、エラー標識が出力されるとともに前記MTモードの有効化が防止される、請求項11に記載の方法。
- 前記構成のリセットまたは非活動化に基づいて前記MTモードが無効化され、1つまたは複数の二次スレッド・コンテキストと直前設定PSMTIDとが、非クリア・リセットの場合には保持され、クリア・リセットの場合にはゼロにされる、請求項10に記載の方法。
- サービス呼出し(SERVC)命令またはシステム情報ストア(STSI)命令に対する応答に基づいて、最大スレッドidの標識が実行プログラムに提供される、請求項9に記載の方法。
- 前記構成を含むコンピュータ・システムは、複数の構成をさらに含み、前記コンピュータ・システムの前記複数の構成のそれぞれが、同時に有効化された異なる数のスレッドを前記複数の構成のそれぞれでサポートするために、異なる数の最大スレッドidを備えて構成され得る、請求項9に記載の方法。
- シングル・スレッド(ST)モードとマルチスレッディング(MT)モードとの間で切換え構成可能なコアを含む構成におけるマルチスレッディングの動的有効化を実装するためのコンピュータ・プログラムであって、前記STモードは一次スレッドを扱い、前記MTモードは前記一次スレッドと前記コアの共用資源上の1つまたは複数の二次スレッドとを扱い、前記コンピュータ・プログラムは、コンピュータに、
前記STモードで前記構成の前記コア上の前記一次スレッドにおいてMTモード設定命令を実行することと、
前記MTモード設定命令によって指定された記憶場所から要求スレッド数を取得することと、
前記要求スレッド数が複数のスレッドを示すとの判断に基づいて、前記一次スレッドと前記1つまたは複数の二次スレッドとを含む前記複数のスレッドを実行するために前記MTモードを有効化することとを含む方法を実行させる、コンピュータ・プログラム。 - 前記MTモード設定命令はオペレーティング・システムからのシグナル・プロセッサ(SIGP)命令であり、前記SIGP命令はMT設定命令(order)と、前記要求スレッド数に関連づけられたプログラム指定最大スレッドid(PSMTID)とを含む、請求項16に記載のコンピュータ・プログラム。
- 前記PSMTIDが非ゼロ値である前記MT設定命令(order)の実行に基づいて、前記MTモードを有効化することと、
前記PSMTIDがゼロ値である前記MT設定命令(order)の実行に基づいて、前記STモードを維持するとともに前記MTモードの有効化を防止することとをさらに前記コンピュータに実行させる、請求項17に記載のコンピュータ・プログラム。 - 前記MT設定命令(order)が、無効な命令(order)と、不正な状態と、無効なパラメータとのうちの1つまたは複数とともに発行されたとの判断に基づいて、エラー標識が出力されるとともに前記MTモードの有効化が防止される、請求項18に記載のコンピュータ・プログラム。
- 前記構成のリセットまたは非活動化に基づいて前記MTモードが無効化され、1つまたは複数の二次スレッド・コンテキストと直前設定PSMTIDとが、非クリア・リセットの場合には保持され、クリア・リセットの場合にはゼロにされる、請求項17に記載のコンピュータ・プログラム。
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WO2015144544A1 (en) | 2015-10-01 |
US9354883B2 (en) | 2016-05-31 |
EP3123328B1 (en) | 2018-06-06 |
TWI594184B (zh) | 2017-08-01 |
CA2940905C (en) | 2022-08-16 |
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