WO2008155797A1 - 演算装置 - Google Patents

演算装置 Download PDF

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Publication number
WO2008155797A1
WO2008155797A1 PCT/JP2007/000650 JP2007000650W WO2008155797A1 WO 2008155797 A1 WO2008155797 A1 WO 2008155797A1 JP 2007000650 W JP2007000650 W JP 2007000650W WO 2008155797 A1 WO2008155797 A1 WO 2008155797A1
Authority
WO
WIPO (PCT)
Prior art keywords
arithmetic unit
instruction
threads
executed
mode
Prior art date
Application number
PCT/JP2007/000650
Other languages
English (en)
French (fr)
Inventor
Norihito Gomyo
Toshio Yoshida
Ryuichi Sunayama
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to CN2007800533324A priority Critical patent/CN101681260B/zh
Priority to PCT/JP2007/000650 priority patent/WO2008155797A1/ja
Priority to EP07790176A priority patent/EP2159687B1/en
Priority to KR1020097025991A priority patent/KR101109029B1/ko
Priority to EP11182687.1A priority patent/EP2423808B1/en
Priority to JP2009520138A priority patent/JP5099131B2/ja
Publication of WO2008155797A1 publication Critical patent/WO2008155797A1/ja
Priority to US12/638,760 priority patent/US8407714B2/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083Power or thermal control instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009Thread control instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Quality & Reliability (AREA)
  • Power Sources (AREA)
  • Executing Machine-Instructions (AREA)
  • Hardware Redundancy (AREA)
  • Retry When Errors Occur (AREA)
  • Advance Control (AREA)

Abstract

 複数のスレッドを同時に処理する演算装置であって、ハードウェアエラーが発生した場合であっても、全体としての処理能力の低下を最小限に抑えて処理を継続することができる演算装置を提供するために、演算装置100に、複数のスレッドの命令列を実行するモードと単一のスレッドの命令列を実行するモードとを選択的に実行可能な命令実行回路101と、命令実行回路101に対してスレッドモードの切り替えを指示する切り替え指示回路102と、を備える。
PCT/JP2007/000650 2007-06-20 2007-06-20 演算装置 WO2008155797A1 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN2007800533324A CN101681260B (zh) 2007-06-20 2007-06-20 运算装置
PCT/JP2007/000650 WO2008155797A1 (ja) 2007-06-20 2007-06-20 演算装置
EP07790176A EP2159687B1 (en) 2007-06-20 2007-06-20 Arithmetic unit
KR1020097025991A KR101109029B1 (ko) 2007-06-20 2007-06-20 연산 장치
EP11182687.1A EP2423808B1 (en) 2007-06-20 2007-06-20 Arithmetic device
JP2009520138A JP5099131B2 (ja) 2007-06-20 2007-06-20 演算装置
US12/638,760 US8407714B2 (en) 2007-06-20 2009-12-15 Arithmetic device for processing one or more threads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000650 WO2008155797A1 (ja) 2007-06-20 2007-06-20 演算装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/638,760 Continuation US8407714B2 (en) 2007-06-20 2009-12-15 Arithmetic device for processing one or more threads

Publications (1)

Publication Number Publication Date
WO2008155797A1 true WO2008155797A1 (ja) 2008-12-24

Family

ID=40155962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000650 WO2008155797A1 (ja) 2007-06-20 2007-06-20 演算装置

Country Status (6)

Country Link
US (1) US8407714B2 (ja)
EP (2) EP2423808B1 (ja)
JP (1) JP5099131B2 (ja)
KR (1) KR101109029B1 (ja)
CN (1) CN101681260B (ja)
WO (1) WO2008155797A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011124677A (ja) * 2009-12-09 2011-06-23 Nec Corp パケット処理装置、パケット振り分け装置、制御プログラム及びパケット分散方法
JP2013214331A (ja) * 2013-07-22 2013-10-17 Panasonic Corp コンパイラ
JP2017515203A (ja) * 2014-03-27 2017-06-08 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation コンピュータにおいて複数のスレッドをディスパッチするための方法、システム、およびコンピュータ・プログラム

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976206B (zh) * 2010-10-28 2016-04-20 北京中星微电子有限公司 一种中断处理方法和装置
TWI439925B (zh) * 2011-12-01 2014-06-01 Inst Information Industry 內嵌式系統及其執行緒與緩衝區管理方法
US8930950B2 (en) * 2012-01-19 2015-01-06 International Business Machines Corporation Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors
US8982878B1 (en) * 2013-02-15 2015-03-17 Sprint Communications Company L.P. Centralized circuit switch provisioning system
US9218185B2 (en) * 2014-03-27 2015-12-22 International Business Machines Corporation Multithreading capability information retrieval
US9804846B2 (en) 2014-03-27 2017-10-31 International Business Machines Corporation Thread context preservation in a multithreading computer system
US10102004B2 (en) 2014-03-27 2018-10-16 International Business Machines Corporation Hardware counters to track utilization in a multithreading computer system
US9921848B2 (en) 2014-03-27 2018-03-20 International Business Machines Corporation Address expansion and contraction in a multithreading computer system
US9417876B2 (en) * 2014-03-27 2016-08-16 International Business Machines Corporation Thread context restoration in a multithreading computer system
US9594660B2 (en) 2014-03-27 2017-03-14 International Business Machines Corporation Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores
US9354883B2 (en) 2014-03-27 2016-05-31 International Business Machines Corporation Dynamic enablement of multithreading
US9753776B2 (en) * 2015-12-01 2017-09-05 International Business Machines Corporation Simultaneous multithreading resource sharing
US10339060B2 (en) * 2016-12-30 2019-07-02 Intel Corporation Optimized caching agent with integrated directory cache
US10817295B2 (en) * 2017-04-28 2020-10-27 Nvidia Corporation Thread-level sleep in a multithreaded architecture
CN108337295B (zh) * 2018-01-12 2022-09-23 青岛海尔智能家电科技有限公司 一种物联网通信方法、服务器及系统
CN108600368B (zh) * 2018-04-25 2021-10-08 海信视像科技股份有限公司 一种hls网络视频下载优化方法及装置
KR102549837B1 (ko) 2022-12-06 2023-06-29 오길식 서랍식 컨버터교체를 위한 혁신적인 엘이디조명등
KR102642044B1 (ko) 2023-12-06 2024-02-27 오길식 컨버터 및 엘이디모듈을 서랍식으로 교체하도록 한 혁신적인 엘이디조명등

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005514698A (ja) * 2001-12-31 2005-05-19 インテル コーポレイション マルチスレッドプロセッサのスレッドの実行のサスペンド処理
JP3683837B2 (ja) * 2000-08-15 2005-08-17 インターナショナル・ビジネス・マシーンズ・コーポレーション スレッド能力を変更する方法及びマルチスレッド・コンピュータ・システム
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100500002B1 (ko) * 1996-08-27 2005-09-08 마츠시타 덴끼 산교 가부시키가이샤 복수의명령흐름을독립적으로처리하고,명령흐름단위로처리성능을유연하게제어하는멀티스레드프로세서
JP3760035B2 (ja) 1996-08-27 2006-03-29 松下電器産業株式会社 複数の命令流を独立に処理し、命令流単位に処理性能を柔軟に制御するマルチスレッドプロセッサ
US6233599B1 (en) * 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US6889319B1 (en) * 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US7051329B1 (en) * 1999-12-28 2006-05-23 Intel Corporation Method and apparatus for managing resources in a multithreaded processor
US6715062B1 (en) * 2000-07-26 2004-03-30 International Business Machines Corporation Processor and method for performing a hardware test during instruction execution in a normal mode
US6651158B2 (en) * 2001-06-22 2003-11-18 Intel Corporation Determination of approaching instruction starvation of threads based on a plurality of conditions
US7363474B2 (en) 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
TWI261198B (en) * 2003-02-20 2006-09-01 Samsung Electronics Co Ltd Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating
US7000233B2 (en) * 2003-04-21 2006-02-14 International Business Machines Corporation Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread
US7657893B2 (en) 2003-04-23 2010-02-02 International Business Machines Corporation Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor
US7155600B2 (en) 2003-04-24 2006-12-26 International Business Machines Corporation Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor
US7496915B2 (en) * 2003-04-24 2009-02-24 International Business Machines Corporation Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes
US7290261B2 (en) * 2003-04-24 2007-10-30 International Business Machines Corporation Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor
US7404105B2 (en) * 2004-08-16 2008-07-22 International Business Machines Corporation High availability multi-processor system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3683837B2 (ja) * 2000-08-15 2005-08-17 インターナショナル・ビジネス・マシーンズ・コーポレーション スレッド能力を変更する方法及びマルチスレッド・コンピュータ・システム
JP2005514698A (ja) * 2001-12-31 2005-05-19 インテル コーポレイション マルチスレッドプロセッサのスレッドの実行のサスペンド処理
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2159687A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011124677A (ja) * 2009-12-09 2011-06-23 Nec Corp パケット処理装置、パケット振り分け装置、制御プログラム及びパケット分散方法
JP2013214331A (ja) * 2013-07-22 2013-10-17 Panasonic Corp コンパイラ
JP2017515203A (ja) * 2014-03-27 2017-06-08 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation コンピュータにおいて複数のスレッドをディスパッチするための方法、システム、およびコンピュータ・プログラム

Also Published As

Publication number Publication date
EP2159687A4 (en) 2011-03-09
EP2159687A1 (en) 2010-03-03
JPWO2008155797A1 (ja) 2010-08-26
US8407714B2 (en) 2013-03-26
EP2423808B1 (en) 2014-05-14
EP2159687B1 (en) 2012-12-05
EP2423808A1 (en) 2012-02-29
CN101681260A (zh) 2010-03-24
KR20100023866A (ko) 2010-03-04
KR101109029B1 (ko) 2012-01-31
CN101681260B (zh) 2013-04-17
US20100095306A1 (en) 2010-04-15
JP5099131B2 (ja) 2012-12-12

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