JP6468603B2 - Clock system switching control circuit and network device - Google Patents

Description

  The present invention relates to a clock system switching control circuit and a network device, and in particular, automatic clock system switching operation when a clock system failure such as a clock panel failure or a clock reception alarm occurs does not require control from the control panel. The present invention relates to a clock system switching control circuit and a network device that can be performed.

  In the case of a network device having two clock panels forming a redundant configuration, in the prior art, for example, as described in Japanese Patent Laid-Open No. 9-215073 “Clock Distribution Method” of Patent Document 1, In order to control switching of the panel system, a control panel different from the clock panel is required.

  FIG. 3 is a block diagram showing an example of a clock system switching control circuit in the prior art. This clock system switching control circuit is an example of a circuit that requires installation of a control panel different from the clock panel in order to control automatic switching of the clock panel system. 3 includes a clock panel 0 system 301, a clock panel 1 system 302, a backboard 303, a main signal panel 304,..., A main signal panel n 305, and a control panel. 306.

  In the clock system switching control circuit of FIG. 3, the clock panels that supply clocks to the main signal panel 1 304,..., The main signal panel n 305 are two clock panels, a clock panel 0 system 301 and a clock panel 1 system 302. Redundant configuration is adopted. Both clock panels are composed of the same components, and are composed of a bipolar / unipolar converter 401, a phase-locked oscillator 402, a selector 403, and a phase-locked oscillator 404. The main signal panel 1 304,..., And the main signal panel n 305 are all composed of the same components, and include an abnormality detection unit 407, a selector 408, and a phase-locked oscillator 409. The control panel 306 includes a control unit 410 and a determination unit 411.

  Each of the clock panel 0 system 301 and the clock panel 1 system 302 distributes the 0 system clock A01 and the 1 system clock A02 to a plurality of main signal panels 1304,. In addition, each of the plurality of main signal panels 1 304,..., Main signal panel n 305 includes main signal panel 1 detection 0 system / 1 system clock input abnormality signal, main signal panel including main signal panel 1 mounting information and failure information. 1 abnormality notification signal B01, ..., main signal panel n detection 0 system / 1 system clock input abnormality signal, main signal panel n abnormality notification signal B02 including mounting information and failure information of main signal panel n are notified to control panel 306 doing.

  Here, in the conventional clock system switching control circuit of FIG. 3, the selectors 403 of each of the two clock panels 0 system 301 / clock panel 1 system 302 forming a redundant configuration, and a plurality of main clock distribution destinations. When the selector 408 of each of the signal panel 1 304,..., The main signal panel n 305 is controlled, the control panel 306 is used separately from the clock panel 0 system 301 / clock panel 1 system 302. That is, the control panel 306 displays the abnormality information of the 0-system clock input abnormality and the 1-system clock input abnormality as the abnormality of each of the plurality of main signal panels 1 304,. The main signal panel 1304,..., The main signal panel n 305 are received from the detection unit 407 together with mounting information and failure information.

  The control panel 306 performs clock system switching control based on the main signal panel 1 abnormality notification signal B01,..., The main signal panel n abnormality notification signal B02 received from the main signal panel 1 304,. The determination unit 411 performs the determination. Then, using the determination result by the determination unit 411, the control unit 410 causes the selector control signal D 01 for the clock panel 0 system, the selector control signal D 02 for the clock panel 1 system, and the selector control signal C 01 for the main signal panel 1 304 to be used. ,..., Each of the selector control signals C02 of the main signal panel n 305 is generated.

  Thereafter, the control panel 306 sends the generated selector control signal D01, selector control signal D02, selector control signal C01,..., Selector control signal C02 to the clock panel 0 system 101 and the clock panel 1 system 102, respectively. Output to the selector 403 and the selectors 408 of the plurality of main signal panels 1 304,..., And the main signal panel n 305, to which the clock is distributed, to control the selectors 403 and 408, respectively.

  As described above, in the conventional technique, in order to control the switching of the clock system of the clock panel 0 system 301 and the clock panel 1 system 302, a control panel 306 different from the clock panel 0 system 301 and the clock panel 1 system 302 is used. Was necessary. If a control panel 306 other than the clock panel 0 system 301 and the clock panel 1 system 302 is not mounted as a clock system switching control circuit, a failure of the clock panel 0 system 301 and the clock panel 1 system 302, etc. Even if the clock system failure occurred, the clock system could not be switched automatically.

  That is, when control of the clock system automatic switching by detecting a failure of either the clock panel 0 system 301 or the clock panel 1 system 302 is performed by the control panel 306 as the clock system switching control circuit, the control is performed in maintenance work of the control panel 306 or the like. If the panel 306 is removed, the clock system cannot be automatically switched by detecting the clock system failure. Therefore, even if the conventional clock system switching control circuit of FIG. 3 is installed, if a clock system failure occurs while the control panel 306 is removed, the main signal in the network device or the like is affected. The risk given was inevitable.

  Further, as described in Japanese Patent Application Laid-Open No. 2005-173760, “Startup Master System Determination Method in Dual System Device”, for example, as a clock system switching control circuit, a clock panel 0 system 301, a clock When the control panel 306 different from the panel 1 system 302 is not mounted, the clock panel initial priority activation system when the network device is turned on is fixed to either the clock panel 0 system 301 or the clock panel 1 system 302. I could not. Here, without depending on the control panel 306 different from the clock panel 0 system 301 and the clock panel 1 system 302, the clock panel initial priority activation at the time of power-on of a device such as a network device equipped with a clock system switching control circuit. When the system is fixed to either the clock panel 0 system 301 or the clock panel 1 system 302 and forced to start up, the two clock panels of the clock panel 0 system 301 and the clock panel 1 system 302 are the same. When performing maintenance work, it is necessary to prepare two types of clock panels separately.

  Also, when priority setting information such as a priority system that starts earlier and a non-priority system that starts later is set in the two clock panels of the clock panel 0 system 301 and the clock panel 1 system 302, the priority setting information is set. If, for example, clock panels set to different priority setting information are installed in the 0 system and the 1 system, the clock panel initial priority activation system when the network device is turned on cannot be fixed. The problem that occurred.

Japanese Patent Laid-Open No. 9-215073 JP 2005-173760 A

  As described above, the conventional clock system switching control circuit has the following problems.

  The first problem is that, for example, if the control panel is removed for maintenance work due to a control panel failure or the like, the clock system cannot be automatically switched by detecting the failure of the clock system. As a result, there is a possibility of causing an error in the main signal in the apparatus.

  This is because, in the prior art, as described above, a circuit for controlling automatic switching of the clock panel system is provided in a control panel different from the clock panel. And in the control panel, because collection and determination of various information by clock failure detection and clock panel switching control are performed, in the case of maintenance work accompanying control panel failure etc., if the control panel is removed, This means that it becomes impossible to automatically switch the clock system by detecting the failure of the clock.

  The second problem is that the automatic switching control of the clock panel is performed only by the clock panel without depending on the control panel different from the clock panel, even if the clock system switching control circuit is mounted, the network The initial priority startup system of the clock panel at the time of power-on of a device such as a device cannot be started up with either the 0 system or the 1 system fixed. As a result, when a service such as a network device is started up after the power is turned on, if the system is started up with a separate clock panel for each device, the operation system of the clock panel should be unified. This means that the person (user) had to manually set the operation system of the clock panel of each device.

  The reason is that both the 0-system and 1-system clock panels are panels with the same function, so the initial priority activation system of the clock panel when the device is turned on is the clock panel that has been activated by chance when the power is turned on. This is because the initial priority startup system depends on the individual performance error of the startup time required to complete the startup of each clock panel.

  The third problem is that the initial priority startup system at the time of power-on of the device is fixed to either the 0 system or the 1 system every time without forcing the control panel to start up forcibly. This means that the two clock panels must be of two types, a priority panel and a non-priority panel. As a result, the number of clock panel types increases, and in the scenes of production, operation, maintenance, etc., the number of management man-hours required when using the same type of clock panel is required.

  The reason for this is that the initial priority startup system at the time of power-on of the device is fixed in either the 0 system or the 1 system each time and is forced to start up without using the control panel. As such, there are two types of clock panels: a clock panel that has a function to start up as an initial selection system (initial priority startup system) and a clock panel that has a function to start up as an initial non-selection system (initial non-priority startup system) when the device is turned on. This is because it is necessary to use a clock panel.

  The fourth problem is common to one type of clock panel. For example, by setting priority setting information using a switch or a non-volatile memory, an initial selection system (initial priority startup system) and an initial non-selection system (initial non-priority) When the system is configured so that the user can arbitrarily change the startup system), the priority setting information of the clock panel is set incorrectly and installed in the 0 system and 1 system. This means that the initial priority startup system at power-on cannot be fixed.

  The reason is that the priority setting information of the initial priority activation system set in advance in the clock panels of the 0 system and the 1 system at the time of setting operation of the switch or the non-volatile memory mounted on the clock panel is mistakenly set. If it is mounted on the 1st system and the 1st system, both systems will become a priority system or a non-priority system clock panel. Therefore, the initial priority startup system needs to be started before each clock panel is started up. This is because it depends on the individual performance error of time, and as a result, the initial priority startup system at the time of power-on of the apparatus cannot be fixed.

(Object of the present invention)
The present invention has been made in view of the above problems, and relates to a clock system switching control circuit and a network device having two clock panels forming a redundant configuration. From the control panel, an automatic clock system switching operation is performed. It is possible to automatically switch the clock system even if the control panel is removed during maintenance work, etc., and as an initial priority startup system when the device is turned on without increasing the number of clock panel types It is possible to fix and start up each time using either the 0 system or the 1 system clock panel system, and if the initial priority startup system can be arbitrarily selected by user settings, the settings are incorrect. Even in such a case, the clock system switching control circuit and network that can fix the initial priority startup system when the device is turned on To provide a click device, it is an object.

  In order to solve the above-described problems, the clock system switching control circuit and the network device according to the present invention mainly adopt the following characteristic configuration.

(1) A clock system switching control circuit according to the present invention includes a clock system switching circuit including two clock panels, one or more main signal panels, and a backboard that form a redundant configuration of the 0 system and the 1 system. A control circuit,
Each of the one or more main signal panels includes an abnormality detection unit that detects an abnormality of each of the two clocks distributed from each of the two clock panels, and a selector that selects and outputs one of the two clocks And at least comprising
Each of the two clock panels includes a selector that selects whether or not to distribute the clock to each of one or more main signal panels, and a determination unit that determines switching control of the clock system between the active system and the non-operating system And at least a control unit that controls a selection operation of the selector in the own clock panel and the selector in the main signal panel based on a determination result of the determination unit,
The determination unit of each of the two clock panels includes, from each of the main signal panels to which a clock is distributed, clock input abnormality information from the own clock panel, clock input abnormality information from another system clock panel, and Based on the result of receiving the mounting information and failure information of each main signal panel, it is determined whether to switch the clock system between the active system and the non-operating system, and notifies the control unit of the own clock panel The switching between the selector of the own clock panel and the selector of each of the main signal panels is performed.

  (2) In the network device according to the present invention, a clock system switching control circuit for controlling switching of the two clock panels in a network device having two clock panels forming a redundant configuration of the 0 system and the 1 system, It comprises at least the clock system switching control circuit described in (1).

  According to the clock system switching control circuit and the network device of the present invention, the following effects can be obtained mainly.

  That is, in the present invention, the clock system can be automatically switched by the cooperative operation of the clock panels, and unlike the prior art, it is not necessary to mount the clock system automatic switching control circuit in the control panel. Therefore, even if the control panel is removed, the clock system can be automatically switched by detecting a clock failure.

  The reason for this is that in the clock system switching control circuit of the present invention, each of the 0 system / 1 system clock panels forming the redundant configuration has its own system clocks from one or more main signal panels to which the clock is distributed. By collecting information on input abnormality from the panel and input abnormality from other system clock panels, and mounting information and failure information on each of one or more main signal panels, the clock panels can be connected to each other without going through the control panel. This is because the clock system can be automatically switched by the cooperative operation.

It is a block block diagram which shows an example of the block configuration of the clock system switching control circuit which concerns on one Embodiment of this invention. FIG. 1 is a flowchart for explaining an example of the operation of the determination unit of the clock system switching control circuit illustrated as an embodiment of the present invention in FIG. It is a block configuration diagram showing an example of a conventional clock system switching control circuit.

  Preferred embodiments of a clock system switching control circuit and a network device according to the present invention will be described below with reference to the accompanying drawings. In the following description, a clock system switching control circuit for controlling switching between the active system and the non-operating system (standby system) will be described with respect to two clock panels having a redundant configuration. It goes without saying that the system switching control circuit may be mounted on various network devices that implement a communication function. In addition, it is needless to say that the drawing reference numerals attached to the following drawings are added for convenience to the respective elements as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiments. Yes.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. In the present invention, each of the 0-system / 1-system clock panels forming the redundant configuration is connected to each of one or more main signal panels to which the clock is distributed, from the input abnormality from the own-system clock panel and from the other-system clock panels. Input error information, mounting information and failure information of each main signal panel, and using the information, the clock panel cooperates with each other, and unlike the conventional technology, it passes through the control panel. The main feature is that it has a mechanism to automatically switch the clock panel.

  Also, when a device equipped with a clock system switching control circuit is turned on, the clock panel mounting position (that is, the clock panel identification information of the 0 system and the 1 system) from the backboard on which two clock panels forming a redundant configuration are mounted. ), And by using the acquired slot ID information, the initial priority activation system at the time of power-on of the device is fixed to either the 0 system or the 1 system without using the control panel. One of the features is that it has a mechanism that enables

  In addition, when a device equipped with a clock system switching control circuit is turned on, slot ID information fetched from a backboard on which two clock panels forming a redundant configuration are mounted, and each of the 0 system and 1 system clock panels By using information (priority setting information) indicating the initial priority startup system set in advance, the initial priority startup system at the time of power-on of the device is set to either 0 system or 1 system without using the control panel. One of the features is that it has a mechanism that allows them to be selected and fixed.

  Further, when the device equipped with the clock system switching control circuit is turned on, the slot ID information fetched from the backboard on which the two clock panels forming the redundant configuration are mounted, and the 0 system and 1 system clock panels, respectively. By using the pre-set initial priority start system information (priority setting information), the initial priority start system when the device is turned on is either 0 system or 1 system without going through the control panel. By collecting the priority setting information for fixing the initial priority activation system of the clock panel on the other system side, with respect to the clock system switching control circuit as described above that can be selected and fixed. Even when the priority setting information for fixing the initial priority startup system of both clock panels is set incorrectly, the device is turned on. That it comprises a mechanism that allows to initial first boot system securely fix it is also one of the features.

  In the prior art described in Patent Document 2, the master-slave relationship between the master system and slave system of the clock panel is determined. However, the present invention relates to the master-slave relationship between the master system and slave system of the clock panel. However, it is only related to the clock panel 0 system and the clock panel 1 system that have an equal relationship. The present invention also discloses a technique for setting a clock panel initial startup system at the time of power-on of a device such as a network device in which two clock panels having such a redundant configuration are mounted. In other words, unlike the case of Patent Document 2, in the present invention, the operations of the clock panel 0 system and the clock panel 1 system after startup are also in an equal relationship, and the master system and slave system of the clock panel are the same. Therefore, the circuit scale for realizing the clock system switching control circuit can be reduced.

  Further, in the present invention, as one of the concrete realization means, a time difference is provided between the start completion times of the two clock panels, and the start completion system is always fixed and determined first. It is not only the invention of providing such a time difference itself, but also a feature of how to implement setting means for providing a time difference between the activation completion times of the two clock panels.

  That is, in the present invention, the following mechanism is provided as setting means for providing a time difference between the start completion times of the two clock panels. In other words, each of the two clock panels includes two types of delay circuits that give two types of start-up completion times. When each of the two clock panels is mounted on the backboard of the apparatus, Slot ID information for identifying whether the system is 0 or 1 is fetched from the backboard, and based on the fetched slot ID information, one of the two types of delay circuits of the own clock panel is selected, The start completion time of the own clock panel is determined. Thus, it is possible to set a time difference in the startup completion time between the two clock panels, and as a result, the clock panel of the initial priority startup system at the time of power-on of the device in which the two clock panels are mounted. Can be fixed to either 0 system or 1 system.

  Further, in the present invention, priority setting information indicating whether the initial priority activation system at the time of power-on of the device on which the two clock panels are mounted is the 0 system clock panel or the 1 system clock panel is provided. A switch or non-volatile memory that can be set to an appropriate value by the user, in other words, a switch or non-volatile memory that allows the user to select one of two types of delay circuits is mounted on each of the two clock panels. ing. The switch or nonvolatile memory mounted on each of the two clock panels is operated in advance by the user and then installed in a device such as a network device. The user can arbitrarily select and set both the clock panel 0 system and the clock panel 1 system. By adopting the configuration described above, the two clock panels can be configured in the same hardware configuration, have the same model number, and have a management burden in the production and maintenance of the clock panel. Can be reduced.

  Furthermore, in the present invention, as described above, the setting of the switches of the two clock panels or the setting of the nonvolatile memory is mistakenly inconsistent and installed in a device such as a network device. However, it is also characterized by having a mechanism to operate normally. In other words, if the switch of the two clock panels or the setting of the non-volatile memory is set in an inconsistent state and installed in the device, the clock panel of the initial priority startup system at the time of power-on of the device, It has a mechanism that can be fixed to either 0 or 1 system.

  In addition, the present invention is characterized in that it is not necessary to provide activation panel selection information and a selection circuit on a panel other than the backboard or the clock panel. As described above, only the slot ID information indicating the mounting position of the clock panel that can identify whether the clock panel is the 0 system or the 1 system is obtained from the backboard. The selection information and the selection circuit are provided in two clock panels of the clock panel 0 system and the clock panel 1 system.

  Furthermore, in the present invention, as described above, each of the two clock panels has the mounting information and failure information of each of the one or more main signal panels, the input abnormality from the own system clock panel, and the other system clock panel. It is also characterized by having a mechanism for obtaining information on abnormal input from As a result, when each main signal panel is not mounted or malfunctions, the clock panel can ignore the information from the corresponding main signal panel, and the own clock panel and other clock panels When there is an abnormality in the output of the clock supplied from each to the main signal panel, the clock system can be automatically switched without intervening the control panel by the cooperative operation of the two clock panels.

  In the prior art described in Patent Document 1, a technique related to a selection unit that selects clocks of two systems (N system and E system) output from two digital clock supply devices (DCS) is described. However, the selection unit is a selector on the clock receiving unit side in the clock panel, and corresponds to the selector 403 in FIG. Furthermore, in the prior art described in Patent Document 1, it is not possible to select an initial clock starting system when a device equipped with two digital clock supply devices (DCS) is turned on.

  In contrast, in the present invention, not only the selector on the clock receiving unit side in the clock panel but also the selector on the clock transmitting unit side mounted in each main signal panel (a selector corresponding to the selector 408 in FIG. 3). ) Is also a target for selecting an initial startup clock panel when a device such as a network device equipped with a clock panel is turned on.

(Configuration example of embodiment of the present invention)
Next, a specific configuration example of the clock system switching control circuit according to the present invention will be described in detail with reference to FIG. FIG. 1 is a block configuration diagram showing an example of a block configuration of a clock system switching control circuit according to an embodiment of the present invention. 1 includes a clock panel 0 system 101, a clock panel 1 system 102, a backboard 103, a main signal panel 104,..., And a main signal panel n 105. The clock system switching control circuit shown in FIG. Unlike the prior art as shown in FIG. 3, it is not necessary to mount a control function for automatic clock system switching on a control panel different from the clock panel 0 system 101 and the clock panel 1 system 102. It is configured to do.

  That is, in order to switch the clock system, the selector 203 of each of the two clock panels 0 system 101 and the clock panel 1 system 102 forming the redundant configuration and the main signal panel 1 104 to which the clock is distributed,. 105, when the control of each selector 208 is performed, the determination unit 206 and the control unit 205 mounted in each of the clock panel 0 system 101 and the clock panel 1 system 102 are configured to perform control. It is unnecessary to mount a circuit unit for automatic switching control of the clock system in a control panel different from the system 101 and the clock panel 1 system 102.

  In the present embodiment illustrated in FIG. 1, a case where the main signal panel is mounted on the main signal panel 1 104,..., The main signal panel n 105 and n (plural) is described. Needless to say, the following description is exactly the same even if only the above is implemented.

  In the clock system switching control circuit of FIG. 1, the clock panel for supplying clocks to the main signal panel 1 104,..., The main signal panel n 105 is the same as in the prior art of FIG. A redundant configuration using two clock panels of the panel 1 system 102 is adopted, and each internal configuration is composed of the same components. However, each of the clock panel 0 system 101 and the clock panel 1 system 102 in FIG. 1 is different from the prior art in FIG. 3 in that the bipolar unipolar conversion unit 201, the phase synchronous oscillator 202, the selector 203, and the phase synchronous oscillator 204 are included. In addition, it further includes a control unit 205 and a determination unit 206 for automatic clock system switching. The selector 203 is a circuit for selecting whether or not to distribute the clock to each of one to a plurality of main signal panels 1 104,..., Main signal panel n 105, as in the case of the prior art of FIG. The determination unit 206 additionally installed in the present embodiment is a circuit that determines switching control of the clock system between the active system and the non-operation system, and the control unit 205 is based on the determination result of the determination unit 206. This is a circuit that controls the selection operation of the selector 203 in the system clock panel, the main signal panel 1104,..., The selector 208 in the main signal panel n105.

  Further, the main signal panel 1 104,..., The main signal panel n 105 have the same components, and the abnormality detection unit 207, selector 208, phase synchronization, and the like, as in the case of the prior art of FIG. An oscillator 209 is included. The abnormality detection unit 207 is a circuit that detects an abnormality of each of the two clocks distributed from the two clock panel 0 system 101 / clock panel 1 system 102, and the selector 208 selects one of the two clocks. In this way, it is a circuit that outputs to the subsequent phase-locked oscillator 209.

  Each of the clock panel 0 system 101 and the clock panel 1 system 102 distributes the 0 system clock A11 and the 1 system clock A12 to the plurality of main signal panels 1104,. Each of the plurality of main signal panels 1 104,..., Main signal panel n 3105 includes a main signal panel 1 detection 0 system / 1 system clock input abnormal signal, main signal panel 1 including main signal panel 1 mounting information and failure information. 1 abnormality notification signal B11,... Main signal panel n detection 0 system / 1 system clock input abnormality signal, main signal panel n abnormality notification signal B12 including mounting information and failure information of main signal panel n , Each clock panel 1 system 102 is notified.

  In the clock system switching control circuit of FIG. 1, the selector 203 of each of the two clock panels 0 system 101 / clock panel 1 system 102 forming a redundant configuration, and a plurality of main signal panels 1 104 as clock distribution destinations, ... When controlling the selector 208 of each main signal panel n 305, the control is performed using the clock panel 0 system 101 / clock panel 1 system 102, respectively. That is, each of the clock panel 0 system 101 / clock panel 1 system 102 has a 0 system clock detected by the abnormality detection unit 207 of each of the plurality of main signal panels 1 104,. The abnormality information of the input abnormality and the 1-system clock input abnormality is sent from the abnormality detection unit 207 of each of the main signal panel 1 104,..., Main signal panel n 105 to each main signal panel 1 104,. The main signal panel 1 abnormality notification signal B11,... and the main signal panel n abnormality notification signal B12 are received together with the mounting information and failure information of n105.

  Each of the clock panel 0 system 101 / clock panel 1 system 102 includes a main signal panel 1 abnormality notification signal B11,..., A main signal panel n abnormality notification signal B12 received from the main signal panel 1 104,. And the slot ID information F11 / slot ID information F12 (the ID position information indicating whether the own clock panel is installed in the own clock panel, that is, the ID information indicating whether the own clock panel is the 0 system or the 1 system). The switching control is determined by the determination unit 206.

  Then, using the determination result by the determination unit 206, the control unit 205 generates the clock panel 0-system selector control signal D11 and the clock panel 1-system selector control signal D12, respectively. .., Selector control signal C11 output to each of the main signal panel n 105, selector control signal C11 output from the clock panel 1 system 102 to each of the main signal panel 1 104,. Each of the signals C12 is generated.

  Thereafter, each of the clock panel 0 system 101 / clock panel 1 system 102 transmits the generated selector control signal D11, selector control signal D12, selector control signal C11, and selector control signal C12 to the clock panel 0 system 101, Output to the selector 203 of each of the clock panel 1 system 102 and the plurality of main signal panels 1 104,... 208 is controlled.

  In addition, in each determination unit 206 of the clock panel 0 system 101 / clock panel 1 system 102, when the own clock panel is mounted on the backboard 103 and mounted on a device such as a network device, the slot ID is received from the backboard 103. Information F11 / slot ID information F12 is fetched. Then, based on the result of determining whether the own clock panel is the 0 system or the 1 system based on the acquired slot ID information F11 / slot ID information F12, the clock panel 0 system 101 / clock panel 1 The power on clear time (startup completion time) of each of the systems 102 is changed, and a time difference is set between the start completion times of the clock panel 0 system 101 / clock panel 1 system 102.

  That is, each of the two clock panel 0 system 101 / clock panel 1 system 102 has two types of delay circuits for giving two types of power-on-clear time (start-up completion time), and further powers on the device. A switch or nonvolatile memory in which the user can set priority setting information indicating whether the initial priority activation system at the time is to be a 0-system clock panel or a 1-system clock panel to an appropriate value, in other words, A switch or a non-volatile memory for allowing the user to select one of the two types of delay circuits is mounted on each of the two clock panel 0 system 101 / clock panel 1 system 102. As a result, when two clock panels 0-system 101 / clock panel 1-system 102 are mounted, it is possible to set a time difference between the start completion times of the two clock panels 0-system 101 / clock panel 1-system 102. In addition, the user can arbitrarily select and set the initial activation system at the time of power-on of a device such as a network device as either the clock panel 0 system 101 or the clock panel 1 system 102. That is, it is possible to start up the clock panel with the shorter start completion time as the initial startup system (active system) and the longer clock panel as the initial non-startup system (non-active system or standby system).

  It should be noted that the determination units 206 of the clock panel 0 system 101 and the clock panel 1 system 102 each perform the clock system switching control at the time of power-on in a coordinated manner so that the clock system 0 system 101 and the clock panel 1 system 102 can be normally activated. And the setting information notification signal E12 fixed to the initial priority activation system of the other clock panel are mutually transmitted.

  That is, although not shown in FIG. 1, a switch or a non-volatile memory is mounted on each of the clock panel 0 system 101 / clock panel 1 system 102, and the clock panel 0 system 101 / clock panel 1 system 102 respectively. , The priority setting information F21 for initial priority activation system fixation indicating that the user has previously selected and instructed that the network device or the like be fixed as the initial priority activation system at power-on. The setting information F22 can be set in advance in each switch or nonvolatile memory.

  Then, the determination unit 206 of each of the clock panel 0 system 101 / clock panel 1 system 102 uses a switch or a non-volatile memory of each of the clock panel 0 system 101 / clock panel 1 system 102 when a device such as a network device is turned on. The preset priority setting information F21 fixed to the initial priority activation system / priority priority setting information F22 fixed to the initial priority activation system can be fetched, and the activation of the clock panel of the other system can be completed. Separately from the transmission operation of the start completion notification signal E11 shown, it can be transmitted as the setting information notification signal E12 fixed to the initial priority start system.

  Then, the determination unit 206 of each of the clock panel 0 system 101 / clock panel 1 system 102 receives priority setting information F21 / initial priority fixed system fixed priority setting information that is fetched from the switch or the nonvolatile memory. By using F22, the start completion notification signal E11 of the other clock panel notified from the other clock panel, and the respective slot ID information F11 / slot ID information F12 fetched from the backboard 103, the conventional system is used. In an environment where only one type of clock panel is used instead of two types of control panels as in the case of technology, the initial priority startup system at the time of power-on of a device such as a network device is 0 or It is possible to select and fix either clock panel of system 1 It is set to.

  Furthermore, the determination unit 206 of each of the clock panel 0 system 101 / clock panel 1 system 102 mutually transmits a setting information notification signal E12 for fixing the initial priority activation system of the other clock panel to the other system clock panel. Therefore, even if the setting information for the initial priority startup system fixed for both systems is set differently, the initial priority startup system at the time of power-on of a device such as a network device can be operated normally without contradiction. It is possible to fix.

  An example of an initial priority activation system determination table according to an embodiment of the present invention is shown in Table 1 below.

  In the example of the initial priority activation system determination table shown in Table 1, when the slot ID information F11 / slot ID information F12 of each of the clock panel 0 system 101 / clock panel 1 system 102 is 'A' / 'B' Is shown. As shown in Table 1, for example, priority setting information F21 of initial priority start system fixed and fixed of initial priority start system fixed in advance for each switch or nonvolatile memory of clock panel 0 system 101 / clock panel 1 system 102 When the priority setting information F22 is set to “A” (clock panel 0 system priority), each of the determination units 206 of the clock panel 0 system 101 / clock panel 1 system 102 determines the clock. The panel 0 system priority is determined. Similarly, initial priority startup system fixed priority setting information F21 / initial priority startup system fixed priority setting information F22 set in advance in each switch or nonvolatile memory of clock panel 0 system 101 / clock panel 1 system 102, When both are set to 'B' (clock panel 1 system priority), the determination units 206 of the clock panel 0 system 101 / clock panel 1 system 102 respectively determine that the clock panel 1 system priority has priority. To do.

  On the other hand, when the priority setting information fixed to the initial priority activation system of both systems of the clock panel 0 system 101 / clock panel 1 system 102 is set differently, that is, the clock panel 0 system 101 / clock panel 1 Both the priority setting information F21 fixed to the initial priority activation system and the priority setting information F22 fixed to the initial priority activation system, which are preset in each switch or nonvolatile memory of the system 102, are different information, and one of them is 'A' ( Clock panel 0 system priority) and the other is set inconsistent with 'B' (clock panel 1 system priority), the clock panel 0 system in the example of the initial priority activation system determination table shown in Table 1 Each of the determination units 206 of the 101 / clock panel 1 system 102 determines that the clock panel 0 system has priority.

  As a result, even if the priority setting information for fixing the initial priority start system for both systems is set differently, the initial priority start system at the time of power-on of a device such as a network device is fixed to the clock panel 0 system. Can be made. When the priority setting information fixed for the initial priority activation system for both systems is set differently, the example of Table 1 shows an example in which the clock panel 0 system priority is determined. Instead, it is of course possible to determine that the clock panel 1 system is preferred. In other words, in preparation for the case where the priority setting information fixed for the initial priority activation system of both systems is set differently, the determination unit 206 of each of the clock panel 0 system 101 / clock panel 1 system 102 has a determination at power-on. Information on whether the clock panel of the initial priority activation system is set to 0 or 1 may be set in advance.

(Description of operation of this embodiment)
Next, an example of the operation of the clock system switching control circuit illustrated in FIG. 1 as an embodiment of the present invention will be described in detail with reference to the flowchart of FIG. FIG. 2 is a flowchart for explaining an example of the operation of the determination unit 206 of the clock system switching control circuit exemplified in FIG. 1 as an embodiment of the present invention.

  In the flowchart of FIG. 2, the determination unit 206 of each of the clock panel 0 system 101 / clock panel 1 system 102 receives a back-up when a device such as a network device equipped with a clock system switching control circuit is turned on (step S501). The slot ID information F11 / slot ID information F12 of the clock panel 0 system 101 / clock panel 1 system 102 is read from the board 103 (step S502). Thereafter, the preset priority setting information F21 / initial priority startup system fixed priority setting information F22 set in advance from the respective switches or nonvolatile memories of the clock panel 0 system 101 / clock panel 1 system 102 are stored. Then, it is determined whether the slot ID information F11 / slot ID information F12 read from the backboard 103 match (step S503).

  The determination unit 206 of each of the clock panel 0 system 101 and the clock panel 1 system 102 has the respective slot ID information F11 / slot ID information F12 read from the backboard 103 and the respective initial priority activations fetched from the switch or nonvolatile memory. When the priority setting information F21 fixed to the system / priority setting information F22 fixed to the initial priority activation system is matched (Yes in step S503), it is determined as the initial priority activation system when the network device or the like is turned on. By selecting a delay circuit that gives a short delay time from the two types of delay circuits mounted on each of the clock panel 0 system 101 and the clock panel 1 system 102, the power-on clear time (startup completion time) is reduced. A predetermined short value is set (step S504). On the other hand, if it does not match the priority setting information F21 fixed to the initial priority activation system / priority setting information F22 fixed to the initial priority activation system (No in step S503), the initial setting at the time of power-on of a device such as a network device is performed. By determining a non-priority activation system and selecting a delay circuit that gives a long delay time from the two types of delay circuits, the power-on clear time (activation completion time) is set to a predetermined long value (step S505).

  As a result, a time difference occurs between the clock panel 0 system 101 and the clock panel 1 system 102 until the power-on-clear is canceled (start-up completion time), and the clock panel system determined as the initial priority start-up system However, the power-on clear is canceled first, and the system of the clock panel determined to be the initial non-priority activation system will release the power-on clear after a delay (step S506).

  Note that in step S503, in order to improve the convenience for the user, the priority setting information F21 for initial priority activation system fixed / priority setting information for initial priority activation system that is set in advance in the switch or the nonvolatile memory by the user. A case where the setting value of F22 is collated with the slot ID information F11 / slot ID information F12 is shown. However, in some cases, the determination may be made using only information indicating whether the value of the slot ID information F11 / slot ID information F12 is 0 series or 1 series. In other words, the clock panel of the initial priority startup system at the time of power-on of the device on which the two clock panels are mounted is fixed to either the 0 system or the 1 system without using a switch or a non-volatile memory. If the value of the ID information F11 / slot ID information F12 is a value indicating an initial priority activation system clock panel, the process proceeds to step S504, and if the value is not a value indicating an initial priority activation system clock panel. Alternatively, the process may move to step S505.

  Thereafter, the determination units 206 of the clock panel 0 system 101 and the clock panel 1 system 102 each notify the activation completion notification signal E11 to the determination unit 206 of the other clock panel when the activation of the clock panel is completed. In addition, a setting information notification signal E12 fixed to the initial priority activation system is also transmitted to each other (step S507). When the transmission of the start completion notification signal E11 is completed, the determination units 206 of the clock panel 0 system 101 / clock panel 1 system 102 determine whether or not the start completion notification signal E11 is received from the clock panel of another system. (Step S508).

  When the activation completion notification signal E11 from the other system clock panel has not been received yet (No in step S508), it is determined that the own clock panel has been activated first, and is the initial priority activation system. Determining that the other system clock panel is the initial non-priority activation system, and sending the own system selection instruction information instructing to select the selector 203 of the own system clock panel to the control of the own system clock panel. The data is output to the unit 205 (step S512). The control unit 205 that has received the own system selection instruction information outputs a selector control signal D11 or a selector control signal D12 that instructs the selector 203 of the own system clock panel to select and output the own system clock. At the same time, the selector control signal C11 or the selector control signal C12 instructing to select and output the own clock is output to the selector 208 of each of the main signal panel 1 104,. As a result, the own clock panel is activated as the active system (step S514).

  On the other hand, when the activation completion notification signal E11 is received from the other system clock panel (Yes in step S508), the determination unit 206 of the clock panel 0 system 101 or the clock panel 1 system 102 determines that the other system clock panel Recognizes that there is a high possibility that it is a clock panel of the initial priority startup system that has already been started first, and further, priority setting information for the initial priority startup system fixed in both the local and other clock panels In order to confirm that there is no contradiction in the setting value of F21 / initial priority startup system fixed priority setting information F22, an initial priority startup system fixed setting information notification signal E12 is received from another system clock panel (not yet received). If not, it waits until it is received) (step S509). When receiving the setting information notification signal E12 fixed to the initial priority activation system from the other clock panel, the setting information of the initial priority activation system fixed to the own clock panel fetched from the switch or the nonvolatile memory is received. It is determined whether or not it matches the information of the setting information notification signal E12 fixed to the initial priority activation system (step S510).

  When the setting information for fixing the initial priority activation system of the own clock panel fetched from the switch or the non-volatile memory matches the received information of the setting information notification signal E12 for fixing the initial priority activation system of the other clock panel (Yes in step S510), it is determined that the own clock panel is the initial non-priority activation system, the other clock panel is the initial priority activation system, and the own clock panel is designated as the initial non-operation activation system. The system is activated as (standby system) (step S513).

  On the other hand, the initial priority start system fixed setting information of the own clock panel fetched from the switch or the nonvolatile memory does not match the received initial priority start system fixed setting information notification signal E12 of the other clock panel. In this case (No in step S510), the setting information for the initial priority activation system fixed for both systems of the clock panel 0 system 101 / clock panel 1 system 102 is set differently. First, after temporarily stopping the clock transmission operation from another clock panel that has already been activated, as illustrated in Table 1, in this embodiment, the initial priority activation system is set to be the clock panel 0 system priority. Then, it is determined whether or not the own clock panel is the 0 system (step S511).

  If the own clock panel is the 0 system (Yes in step S511), the process proceeds to step S512 to instruct to select the selector 203 of the own clock panel (that is, the clock panel 0 system 101). Self-system selection instruction information is output to the control unit 205 of the self-system clock panel (step S512). The control unit 205 that has received the own system selection instruction information instructs the selector 203 of the own system clock panel (that is, the clock panel 0 system 101) to select and output the own system clock. D11 or selector control signal D12, and selector control signal C11 for instructing each selector 208 of main signal panel 1 104,..., Main signal panel n 105 to select and output the own clock. The selector control signal C12 is output. As a result, the own clock panel (that is, clock panel 0 system 101) is activated as the active system (step S514).

  On the other hand, if the own clock panel is not the 0 system (No in step S511), if the setting information for fixing the initial priority activation system for both systems is set differently, the own clock panel is initialized. Since it is a 1-system clock panel corresponding to the non-priority activation system, the process proceeds to step S513, and the own-system clock panel (that is, the clock panel 1-system 102) is activated as a non-operation system (step S513).

(Explanation of effect of embodiment)

  As described in detail above, the clock system switching control circuit according to the present embodiment can provide the following effects.

  The first effect is that the clock system can be automatically switched by the cooperative operation of the clock panel 0 system 101 / clock panel 1 system 102, and unlike the prior art, the clock system is automatically switched in the control panel. Since it is not necessary to mount a control circuit, even if the control panel is removed, the clock system can be automatically switched by detecting a clock failure.

  This is because, in the clock system switching control circuit according to the embodiment of the present invention, each of the two clock panels 0 system 101 / clock panel 1 system 102 forming the redundant configuration has a plurality of main signals to which clocks are distributed. Panel 1 104,..., Main signal panel n 105, information on the input abnormality from the own system clock panel and input abnormality from the other system clock panel, and a plurality of main signal panels 1 104,. 105. By collecting the mounting information and failure information of each of them as the main signal panel 1 abnormality notification signal B11,..., The main signal panel n abnormality notification signal B12, the clock panel 0 system 101 / clock without passing through the control panel. Because the clock system can be automatically switched by the cooperative operation of the panel 1 system 102. That.

  The second effect is that the switching control of the clock panel 0 system 101 / clock panel 1 system 102 is performed only by the clock panel without depending on a control panel different from the clock panel 0 system 101 / clock panel 1 system 102. Even in such a case, the initial startup system at the time of power-on of a device such as a network device equipped with a clock system switching control circuit can be fixed and started up on either the 0 system or 1 system clock panel. That is.

  The reason is that in the clock system switching control circuit according to the embodiment of the present invention, when a device such as a network device equipped with the clock system switching control circuit is turned on, two clock panels mounted on the device as a redundant configuration. The slot ID information F11 / slot ID information F12 of each of the 0 system 101 / clock panel 1 system 102 is fetched from the backboard 103, and different start completion times are given using the slot ID information F11 / slot ID information F12 2 By selecting one of the types of delay circuits and setting a time difference between the start completion times of the two clock panel 0 system 101 / clock panel 1 system 102, the initial time when the device is turned on without going through the control panel It is possible to fix the priority startup system to either the 0 system or 1 system clock panel Is because as a.

  The third effect is that the user can set either the 0-system or the 1-system clock panel as the initial priority activation system at the time of power-on of a device such as a network device equipped with the clock system switching control circuit without going through the control panel. It can be arbitrarily selected and fixed.

  The reason is that in the clock system switching control circuit according to the embodiment of the present invention, the slot ID information F11 / slot of each of the clock panel 0 system 101 / clock panel 1 system 102 captured from the backboard 103 when the apparatus is powered on. ID information F12 and initial priority startup system fixed priority setting information F21 / initial priority startup system fixed priority setting information F22 preset to a predetermined value by the user for each of clock panel 0 system 101 / clock panel 1 system 102. This makes it possible to select and fix either the 0-system or 1-system clock panel as the initial priority startup system when the device is turned on without using the control panel. is there.

  The fourth effect is that priority setting information for fixing the initial priority activation system for the priority setting information F21 for fixing the initial priority activation system for both systems, that is, priority setting information F21 for fixing the initial priority activation system / initial priority activation system fixing. Even if the user has mistakenly set the priority setting information F22, it is possible to fix the initial priority activation system at the time of power-on of a device such as a network device equipped with a clock system switching control circuit. That is.

  This is because, in the clock system switching control circuit according to the embodiment of the present invention, the priority setting information for fixing the initial priority activation system of the clock panel on the other system side is set as the setting information notification signal for fixing the initial priority activation system. When the settings of priority setting information for fixing the initial priority startup system of the own system and the priority setting information for fixing the initial priority startup system of the other system are incorrect by collecting each other by E12 Even so, it is possible to fix the initial priority activation system at the time of power-on of the apparatus by the slot ID information F11 / slot ID information F12 of the clock panel 0 system 101 / clock panel 1 system 102 taken in from the backboard 103. This is because it is possible.

  As an application example of the present invention, there is an apparatus, particularly a network apparatus, equipped with two clock panels forming a redundant configuration. According to the present invention, it is possible to automatically perform the system switching control of the 0 system / 1 system clock panel without using the control panel, and the apparatus can be simplified. In addition, since the control of the clock system is not controlled by the control panel, the clock system can be automatically switched even if the control panel is removed for maintenance work, etc. However, it is possible to provide a network device that does not affect the main signal of the device. In operation, it is also possible to provide a network device that enables the operation system of the clock panel to be unified in each device when the service is started after the device power is turned on.

  The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such embodiments are merely examples of the present invention and do not limit the present invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

101 Clock panel 0 system 102 Clock panel 1 system 103 Backboard 104 Main signal panel 1
105 Main signal panel n
201 Bipolar Unipolar Conversion Unit 202 Phase Synchronous Oscillator 203 Selector 204 Phase Synchronous Oscillator 205 Control Unit 206 Determination Unit 207 Abnormality Detection Unit 208 Selector 209 Phase Synchronous Oscillator 301 Clock Panel 0 System 302 Clock Panel 1 System 303 Backboard 304 Main Signal Panel 1
305 Main signal panel n
306 Control panel 401 Bipolar unipolar conversion unit 402 Phase synchronous oscillator 403 Selector 404 Phase synchronous oscillator 407 Abnormality detection unit 408 Selector 409 Phase synchronous oscillator 410 Control unit 411 Determination unit A01 0 system clock A02 1 system clock A11 0 system clock A12 1 system Clock B01 Main signal panel 1 error notification signal (main signal panel 1 detection 0 system / 1 system
Clock input abnormal signal, main signal panel 1 mounting information and failure information)
B02 Main signal panel n abnormality notification signal (main signal panel n detection 0 system / 1 system
Clock input abnormal signal, mounting information and failure information of main signal panel n)
B11 Main signal panel 1 abnormality notification signal (main signal panel 1 detection 0 system / 1 system
Clock input abnormal signal, main signal panel 1 mounting information and failure information)
B12 Main signal panel n abnormality notification signal (main signal panel n detection 0 system / 1 system
Clock input abnormal signal, mounting information and failure information of main signal panel n)
C01 Selector control signal C02 of the main signal panel 1 from the control panel Selector control signal C11 of the main signal panel n from the control panel Selector control signal C12 of the main signal panel from the clock panel 0 system Main signal panel from the clock panel 1 system Selector control signal D01 of the clock panel 0 system from the control panel D02 Selector control signal D11 of the clock panel 1 system from the control panel Selector control signal D12 of the clock panel 0 system Selector control signal E11 of the clock panel 1 system, etc. System clock panel startup completion notification signal E12 Setting information notification signal F11 fixed to the initial priority startup system of the other clock panel Slot ID information (: A) of the clock panel 0 system
F12 Slot ID information of clock panel 1 system (: B)
F21 Priority setting information fixed to the initial priority activation system of the clock panel 0 system F22 Priority setting information fixed to the initial priority activation system of the clock panel 1 system

Claims (4)

A clock system switching control circuit including two clock panels forming a redundant configuration of 0 system and 1 system, one or more main signal panels, and a backboard,
Each of the one or more main signal panels includes an abnormality detection unit that detects an abnormality of each of the two clocks distributed from each of the two clock panels, and a selector that selects and outputs one of the two clocks And at least comprising
Each of the two clock panels includes a selector that selects whether or not to distribute the clock to each of one or more main signal panels, and a determination unit that determines switching control of the clock system between the active system and the non-operating system And at least a control unit that controls a selection operation of the selector in the own clock panel and the selector in the main signal panel based on a determination result of the determination unit,
The determination unit of each of the two clock panels includes, from each of the main signal panels to which a clock is distributed, clock input abnormality information from the own clock panel, clock input abnormality information from another system clock panel, and Based on the result of receiving the mounting information and failure information of each main signal panel, it is determined whether to switch the clock system between the active system and the non-operating system, and notifies the control unit of the own clock panel , Switching between the selector of the own clock panel and the selector of the main signal panel,
Each of the two clock panels includes two types of delay circuits for setting two types of startup completion times,
The determination unit of each of the two clock panels displays slot ID information for identifying whether the own clock panel is the 0 system or the 1 system when the own clock panel is mounted on the backboard. By selecting one of the two types of delay circuits of the own clock panel based on the slot ID information fetched from the board and taking in, and determining the startup completion time of the own clock panel, A time difference is set in the start completion time between the two clock panels, and the clock panel of the initial priority startup system at the time of power-on of the device on which the two clock panels are mounted is set to either 0 system or 1 system. Fixed to crab,
The determination unit of each of the two clock panels notifies the other clock panel of the time when the activation of the own clock panel is completed with each other by an activation completion notification signal. The startup completion time is short, and the clock panel that has transmitted the startup completion notification signal to the other clock panel first is fixed and set as the initial priority startup system when the device equipped with the two clock panels is turned on. And
Priority setting information indicating whether the initial priority activation system at the time of power-on of the device on which the two clock panels are mounted is set to either the 0 system clock panel or the 1 system clock panel. Comprising a switch or nonvolatile memory that can be set by the user,
The determination unit of each of the two clock panels is based on the priority setting information set in the switch of the own clock panel or the nonvolatile memory and the slot ID information captured from the backboard. It is determined whether the clock panel is an initial priority startup system clock panel at power-on, and the clock panel side determined to be the initial priority startup system is the start completion of the two types of delay circuits The clock circuit side that is selected as the delay circuit with the shorter time and is determined not to be the initial priority startup system at the time of power-on is the delay circuit with the longer startup completion time of the two types of the delay circuits. A clock system switching control circuit characterized by being selected . The determination unit of each of the two clock panels, when the activation of the own clock panel is completed, the priority setting set in the switch or the nonvolatile memory of the own clock panel with respect to the other clock panel By notifying each other by a setting information notification signal, it is determined whether or not the priority setting information of the own clock panel matches the priority setting information of the other clock panel. Based on the priority setting information set in the switch or the nonvolatile memory of the own clock panel and the slot ID information fetched from the backboard, the own clock panel has two clock panels. It is determined whether or not the clock panel of the initial priority startup system at the time of power-on of the device equipped with Clock system switching control circuit according to claim 1. The determination unit of each of the two clock panels uses either the 0-system clock panel or the 1-system clock panel as an initial priority activation system clock panel when a device equipped with the two clock panels is turned on. If the priority setting information of the own clock panel does not match the priority setting information of the other clock panel, the information is set based on the slot ID information fetched from the backboard. , the own-system clock panels, one of the two said clock panel, according to claim 2, characterized in that determining whether a clock panel that has been previously set as an initial priority start system at power-on Clock system switching control circuit. In 0-system and the network device equipped with two clocks panels forming the redundant configuration of the 1-system, clock system switching control circuit for controlling the two switching of the clock panel, according to any one of claims 1 to 3 A network apparatus comprising: a clock system switching control circuit.

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