JP2000269945A - Clock non-hit switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a clock non-hit switching device that can realize a non-hit switching, only by providing a circuit simpler than a PLL in each slave unit. SOLUTION: A clock synchronization unit 100a and a clock synchronization unit 100b output clock CLK2, CLK4 that are highly phase-locked to a slave unit 200. A selector 12C selects a clock fed to a function section 16 which is under the control of a switching control section 15. The switching control section 15 controls the selector 12C, so that switching is conducted for a period when the clocks CLD2, CLK4 are both at L or H level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clockless instantaneous interruption switching device for switching a clock signal supplied to a functional unit using a clock signal without stopping the operation of the functional unit.

[0002]

2. Description of the Related Art An example of a clock instantaneous interruption switching device for switching a clock signal supplied to a functional unit using a clock signal without stopping the operation of the functional unit is disclosed in Japanese Patent Application Laid-Open No. H10-240375. A clock instantaneous interruption switching device is known.

FIG. 4 shows a configuration of the clock instantaneous interruption switching device.

[0004] In the figure, 0CLK0 and 0CLK1 which are duplicated and output from the clock supply device 41 are received by the clock receiving units 42a and 42b in the duplicated clock synchronization units 40a and 40b, respectively. In the clock synchronization units 40a and 40b, the delay circuits 43a and 43b
Generates a plurality of signals obtained by delaying the clocks CLK0 and CLK1 received by the clock receiving units 42a and 42b by different delay amounts. The clock synchronization unit 40
The comparison generation circuits 44a and 44b of a and 40b respectively select, from among a plurality of signals output by the delay circuits 43a and 43b, a signal selected by the other comparison generation circuit 44b and 44a and a signal having the same phase. Select, CLK2, C
Output as LK4.

On the other hand, a function unit 47 using a clock signal
In the slave device 48, which is a device including a clock signal, one of the clocks CLK2 and CLK4 is selected as the working clock in the receiving clock system selection 45, and the PLL 46 generates a clock signal phase-synchronized with the working clock, and finally uses this clock signal. It is supplied to the function unit 47 as a clock. Further, when a failure occurs in the working clock or the like, the clock signal to be selected as the working clock is switched between CLK2 and CLK4 in the reception clock system selection 45.

According to the clock non-interruption device, the clock signal phase-locked to the PLL 46 to the working clock selected in the reception clock system selection 45 is used as the used clock. When the clock signal selected as the working clock is switched in the clock system selection 45, generation of an instantaneous pulse that may cause a malfunction of the functional unit can be eliminated. For example, when the PLL is not used, when the working clock is switched to a clock signal immediately before the signal of the used clock becomes H and immediately before the signal changes from L to H at that time, a short momentary pulse is generated. That is, when the PLL is used, the clock to be used smoothly changes to the newly selected clock signal, and thus such an instantaneous pulse does not occur.

Therefore, when the clock signal for selecting the working clock is switched, a malfunction of the function unit 47 using the used clock, which may be caused by generation of an instantaneous pulse, can be eliminated. It is possible to realize instantaneous interruptionless clock switching for switching a clock signal for selecting a working clock without stopping operation.

[0008]

In the conventional clockless instantaneous interruption device, the function unit 47 using a clock signal is used.
When there are a plurality of slave units 48 including the slave unit 48, the PLL 46 and the reception clock system selection 45
It is necessary to provide every eight. Because a plurality of slaves 4
7, a single PLL 46 and a receive clock system selector 45
In this case, the clock signal is not duplicated at a location between the slave device 48 and the device provided with the PLL 48 and the reception clock system selector 45, and a sufficiently reliable system is provided. Because it cannot be done.

On the other hand, since the PLL 46 is a relatively large-scale circuit or element and is relatively expensive, its many uses increase the cost and the scale of the entire apparatus.

Therefore, according to the conventional clock non-interruption device, when there are a plurality of slave devices including a functional unit using a clock signal, a PLL must be provided for each slave device. According to the technique, the cost and the scale of the entire apparatus are increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock instantaneous interruption switching device capable of realizing instantaneous interruption switching simply by providing a circuit simpler than a PLL in each slave device.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is a clock instantaneous interruption switching device for selecting one of duplicated clock signals and supplying the selected clock signal to a functional unit using the clock signal. A selecting unit that selects one of the duplicated clock signals and supplies the selected clock signal to the functional unit; and a switching control unit that controls switching of a clock signal selected by the selecting unit. The switching control unit controls the switching of the selection unit so that the switching is performed during a period in which both of the duplicated clock signals are at the same level. I do.

According to such a clockless instantaneous interruption switching device, the switching of the clock signal is always performed during a period in which both of the duplicated clock signals are at the same level.
It is possible to eliminate a case in which a momentary pulse is generated at the time of switching and the functional unit malfunctions. That is, instantaneous interruption switching can be achieved without using a PLL.

Further, in order to achieve the above-mentioned object, the present invention relates to
A clockless instantaneous interruption switching device that selects one of the multiplexed input clock signals and supplies the selected clock signal to a functional unit that uses the clock signal, and is provided corresponding to each input clock signal.
Clock synchronizers each outputting an intermediate clock signal,
A selector provided for each functional unit, wherein each of the clock synchronizers converts a corresponding input clock signal into an intermediate clock signal having the same phase as the intermediate clock signal output by another clock synchronizer. A clock non-interruptible switching device including a PLL for converting and outputting, wherein the selecting unit selects one of the intermediate clock signals output from each clock synchronizing unit and supplies it to a functional unit. I do.

According to such a clock non-interruptible switching device, in the clock synchronizer provided corresponding to each input clock signal, a dual intermediate clock whose phase is aligned with high accuracy using a PLL. Generate a signal. Therefore, since the phases of the duplicated intermediate clock signals are aligned with high precision, no instantaneous pulse is generated when switching the intermediate clock signals in the selection unit.
As a result, malfunction of the functional unit can be eliminated. In other words, it is possible to achieve instantaneous interruption switching without using a PLL for each function unit while duplicating the clock signal input to the selection unit provided for each function unit.

[0016]

Embodiments of the present invention will be described below.

FIG. 1 shows a configuration of a clock instantaneous interruption switching device according to the present embodiment.

As shown in the figure, the clock instantaneous interruption switching device is a dual clock synchronizer 100a, 100b.
And one or more slave devices 200.

The clock synchronizers 100a and 100b receive the clock signal 0CLK from the clock supply device 11.
0 and 0CLK1 are supplied. Also, each slave device 200 receives a clock signal CLK from the clock synchronizer 100a.
2 is supplied, and CLK4 is supplied from the clock synchronizer 100b.
Is supplied.

Hereinafter, the clock synchronizers 100a and 100
b and the details of the slave device 200 will be described.

First, the clock synchronizers 100a, 100
b will be described.

The clock synchronizer 100a includes a selector 1
2a, a PLL 13a, and a clock output circuit 14a. The clock synchronizer 100b includes a selector 12b, a PLL 13b, and a clock output circuit 14b.

In the clock synchronizer 100a, the selector 12a normally selects 0CLK0 and outputs it as CLK0. If a failure occurs in 0CLK0, the selector 12a outputs 0CLK1.
And outputs it as CLK0. Also, in the clock synchronizer 100b, the selector 12b normally operates at 0
CLK1 is selected and output as CLK1, and when a failure occurs in 0CLK1, 0CLK0 is selected and output as CLK1.

The PLL 13a of the clock synchronizer 100a
Then, the PLL 13b of the clock synchronizer 100b adjusts the phase of the clock signal whose phase is synchronized with the input clock signal so that the phase matches the clock signal output by the other PLL, and outputs the adjusted signal. Specifically, the PLL 13a of the clock synchronizer 100a outputs the clock signal CLK0
From the PLL 1 of the clock synchronizer 100b.
3b generates and outputs a clock signal so that the phase thereof matches the clock signal output by the clock synchronizer 100b.
The PLL 13b generates and outputs a clock signal from the clock signal CLK1 such that its phase matches the phase of the clock signal output from the PLL 13a of the clock synchronizer 100a.

However, actually, the P-phase of the other clock synchronizer is adjusted so that the phase of the clock signal is the same as that of the clock signal output from the PLL of the currently used clock synchronizer.
The phase of the clock signal generated by the LL is adjusted and output.
Here, the clock synchronizer currently used is a clock synchronizer that outputs the clock signal CLK2 or CLK4 selected by a later-described selector 12C of the slave device 200.

It should be noted that the clock synchronizer 100
a and the clock synchronizer 100b are PLLs 13a, 13
b, no instantaneous pulse is generated at the outputs of the PLLs 13a and 13b even when the clocks are switched in the selectors 12a and 12b, as in the prior art.

Next, of the clock output circuit 14a of the clock synchronizer 100a and the clock output circuit 14b of the clock synchronizer 100b, the clock output circuit of the clock synchronizer which is not the current clock synchronizer is used for the clock synchronizer 100a. The phase of the input clock signal is adjusted and output so that the phase matches the clock signal output from the clock output circuit of the device. For example, if the clock synchronizer 100a is an active device, the clock synchronizer 10a
0b is the clock output circuit 1b.
4a, the phase of the input clock signal is adjusted so that the phase matches the output clock signal.
Output as 4.

The above-described clock synchronizers 100a and 100
By the operation of b, CLK2 output from the clock synchronizer 100a and CL output from the clock synchronizer 100b
K4 is a clock signal that is phase-synchronized with high precision.

Next, the slave device 200 will be described.

In slave device 200, clock signal CLK2 input from clock synchronizers 100a and 100b
And CLK4 are selected by the selector 12C and supplied to the functional unit 16.

The selection operation of the selector 12C is controlled by the switching control unit 15.

Hereinafter, the switching control unit 15 will be described.

FIG. 2 shows the configuration of the switching control unit 15.

In the figure, a clock monitor 22 monitors clock signals CLK2 and CLK4 to be inputted, and a switching logic 23 detects when an abnormality is detected in the clock signal currently selected by the selector 12C, and When a switch (for example, a microprocessor executing firmware) is instructed to switch by the switch control 21, a system switch control signal for instructing the selector 12C to switch the clock signal to be selected is output. This system switching control signal is once latched by the latch 28 in synchronization with the rising of the switching control clock output from the logic circuit 27, and then at the rising of the delay switching control clock obtained by delaying the system switching control clock by the delay circuit 25C. Synchronously latched by the latch 29,
It is supplied to the selector 12C. The selector 12C receives the system switching control signal output from the latch 29, and switches a clock signal to be supplied to the functional unit 16 as a used clock.

Here, the timings of the switching control clock and the delay switching control clock will be described with reference to the timing chart of FIG.

The switching control clock and the delay switching control clock are generated from clock signals CLK2 and CLK4 input to slave device 200. Here, the clock synchronizer 1
By the operations of 00a and 100b, the phase difference between CLK2 and CLK4 is guaranteed to be within d.
And CLK4 both have a duty ratio of 50:50,
It is assumed that the pulse width L is L> d.

Now, the switching control clock (27 outputs)
In the generation of the delay switching control clock (25c output), CL
A logic circuit 24a for performing an AND operation of K2 and CLK4;
A delay circuit 25a for delaying the output of the logic circuit 24a;
As shown in FIG. 3, the delay time (D1) of the delay circuit 25a from the time when both CLK2 and CLK4 become H as shown in FIG. A signal (output 26a) which is H for <Ld) is generated.

A logic circuit 24b for performing an AND operation on the inverted value of CLK2 and the inverted value of CLK4;
b, a delay circuit 25b for delaying the output of
The logic circuit 26b that performs an AND operation on the output of the delay circuit 25b and the inverted value of the output of the delay circuit 25b causes the delay time (D
A signal (26b output) that becomes H for 2 <Ld) is generated.

The logic circuit 27 performs an OR operation on the output of the logic circuit 26a and the output of the logic circuit 26b.
A switching control clock (27 outputs) is generated. The switching control clock becomes H at the time when both CLK2 and CLK4 become H, and at the time when both CLK2 and CLK4 become L.
The signal rises.

Next, the switching control clock is supplied to the delay circuit 2
The delay switching control clock (25c output) is obtained by delaying the delay time (D3 = (Ld) / 2) at 5C. As a result, the delay switching control clock is generated at the intermediate point in time during which both CLK2 and CLK4 are H,
The signal rises to H at an intermediate point in time during which both Ls are L.

Therefore, the switching of the clock signal of the selector 12C, which is performed in response to the system switching control signal latched by the latch 29 in synchronization with the rise of the delay switching control clock, always makes both CLK2 and CLK4 H. Is performed during the period in which both CLK2 and CLK4 are L.

As described above, CLK2 and CL are always
During the period in which both K4 is H, CLK2 and CLK
If switching between CLK2 and CLK4 is performed during the period when both L are low, it is possible to eliminate the generation of an instantaneous pulse at the time of switching, thereby eliminating the malfunction of the functional unit 16. it can.

Therefore, according to the present embodiment, the instantaneous interruption clock that switches the clock signal to be selected as the working clock without stopping the operation of the functional unit by using a simple logic circuit without using the PLL for the slave device 200. Switching can be realized.

In the above embodiment, CLK2 and CL output from the clock synchronizers 100a and 100b are used.
In a case where the entire apparatus is configured such that K4 can be input to the slave apparatus 200 with the same phase, the switching timing of the selector 12C may be arbitrary.

[0045]

As described above, according to the present invention, it is possible to provide a clockless instantaneous interruption switching device capable of realizing instantaneous interruption switching simply by providing a circuit simpler than a PLL in each slave device. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock instantaneous interruption switching device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a switching control unit 15 according to the embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of a switching control unit 15 according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional clock instantaneous interruption switching device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Clock supply device 12a, 12b selector 12C selector 13a, 13b PLL 14a, 14b Clock output circuit 15 Switching control part 16 Function part 100a, 100b Clock synchronizer 200 Slave device

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 1/22 H03K 5/00 X F term (Reference) 5J055 AX36 BX12 BX19 CX05 EZ10 EZ25 EZ39 EZ50 EZ60 FX13 FX18 FX21 FX22 FX31 GX01 GX02 GX04 5J106 AA03 BB02 DD09 EE06 GG19 HH10 KK12 KK34 5K014 AA05 CA02 FA01 5K021 AA09 DD02 DD07 EE01 FF03 FF11 5K047 AA11 AA16 GG02 GG07 GG09 GG11 KK18 KK12 KK12 KK12 KK12

Claims (4)

[Claims] 1. A non-interruptible clock switching apparatus for selecting one of duplicated clock signals and supplying the selected clock signal to a function unit using the clock signal, wherein one of the duplicated clock signals is selected. And select
A selection unit that supplies the function unit; and a switching control unit that controls switching of a clock signal selected by the selection unit. The switching control unit is configured so that both of the duplicated clock signals have the same level. A non-clock instantaneous interruption switching device that controls switching of the selection unit so that the switching is performed during a certain period. 2. A clockless instantaneous interruption switching device for selecting one of duplicated input clock signals and supplying the selected input clock signal to one or a plurality of functional units using the clock signal, comprising: A clock synchronization unit that converts a signal into a duplicated intermediate clock signal with a uniform phase and outputs the intermediate clock signal; and a clock selection unit that is provided for each of the functional units. Select one of the multiplexed intermediate clock signals,
A switching unit that controls switching of an intermediate clock signal selected by the selecting unit, wherein the switching control unit is configured to control the switching of the duplicated intermediate clock signals to the same level. Wherein the switching of the selection unit is controlled so that the switching is performed during a certain period. 3. A clockless instantaneous interruption switching device for selecting one of duplicated input clock signals and supplying the selected input clock signal to a function unit using the clock signal, wherein the switching device is provided for each input clock signal. A clock synchronizer that outputs an intermediate clock signal, and a selection unit provided for each functional unit, wherein each of the clock synchronizers outputs a corresponding input clock signal from the intermediate clock output by another clock synchronizer. A PLL for converting the clock signal into the intermediate clock signal having the same phase as the clock signal and outputting the intermediate clock signal, wherein the selecting unit selects one of the intermediate clock signals output from the respective clock synchronization units and supplies the selected intermediate clock signal to the functional unit. Clock instantaneous interruption switching device characterized by the above-mentioned. 4. The switching device according to claim 2, wherein the clock synchronization unit includes a clock synchronization device provided corresponding to each input clock signal and outputting an intermediate clock signal. Each of the clock synchronizers includes a PLL that converts a corresponding input clock signal into the intermediate clock signal having the same phase as the intermediate clock signal output from another clock synchronizer and outputs the converted intermediate clock signal. Clock non-stop switching device.