JP6447075B2 - Wiring substrate, semiconductor device, and manufacturing method of semiconductor device - Google Patents

Wiring substrate, semiconductor device, and manufacturing method of semiconductor device Download PDF

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Publication number
JP6447075B2
JP6447075B2 JP2014250171A JP2014250171A JP6447075B2 JP 6447075 B2 JP6447075 B2 JP 6447075B2 JP 2014250171 A JP2014250171 A JP 2014250171A JP 2014250171 A JP2014250171 A JP 2014250171A JP 6447075 B2 JP6447075 B2 JP 6447075B2
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layer
resin
semiconductor
support
wiring
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JP2016111303A (en
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徹勇起 土田
徹勇起 土田
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凸版印刷株式会社
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

  The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a semiconductor device.

  In recent years, semiconductor devices using semiconductor chips and external connection members have been used in various fields such as electronic devices and automobiles. Patent Document 1 below describes a method of manufacturing a semiconductor device in which an external connection member having a rewiring layer and an external connection terminal is directly formed on a semiconductor chip. In this manufacturing method, an external connection member having a rewiring layer and external connection terminals is formed in the semiconductor chip region. A semiconductor device provided by the manufacturing method is called a Fan-in type WLP (Wafer Level Package).

  In Patent Document 2 below, there is an external connection member that forms an insulating layer that covers the periphery of a semiconductor chip fixed to a support substrate, and that has a rewiring layer and an external connection terminal on the semiconductor chip and the insulating layer. A method of manufacturing the semiconductor device to be formed is described. In this manufacturing method, the external connection member having the rewiring layer and the external connection terminals is also formed in the peripheral region outside the outer edge of the semiconductor chip. A semiconductor device provided by the manufacturing method is called a fan-out type WLP.

JP-A-11-111896 JP 2011-187473 A JP 2014-7315 A JP 2007-242888 A

  In the manufacturing method described in Patent Document 1, since the external connection member is formed in the semiconductor chip region, the number and position of the external connection terminals are limited. In the manufacturing methods described in Patent Documents 1 and 2, since the external connection member is formed directly on the separated semiconductor chip, the manufacturing efficiency of the semiconductor device is lowered.

  In the semiconductor package substrate described in Patent Document 4, there is a limit to the miniaturization of wiring, and for example, it has been difficult to achieve L / S (line / space) = 5/5 μm.

  An object of the present invention is to provide a wiring board capable of forming fine wiring, a semiconductor device using the wiring board, and a manufacturing method thereof.

  The wiring board according to the present invention includes a support having transparency, an adhesive layer including a resin provided on the support and decomposable by light irradiation, and a first laminate provided on the adhesive layer. A first laminated body having two or more resin layers and one or more first wiring patterns provided between the resin layers; a glass layer provided on the first laminated body; and the glass layer The second laminated body is provided with a second laminated body having two or more resin layers and one or more second wiring patterns provided between the resin layers.

  By providing a smooth glass layer on the resin layer, the wiring can be further miniaturized.

  Although this wiring board has a glass layer as a core, since the first laminated body, the glass layer, and the second laminated body are laminated on the support, the handling property can be improved, and the wiring board and the semiconductor can be improved. Breakage of the glass core material during the manufacturing process of the device can be suppressed. In addition, the support has transparency, and the resin in the adhesive layer is decomposed by irradiating the adhesive layer with light through the support, so that the adhesive force of the adhesive layer can be weakened. Thereby, the wiring board which has a glass core can be easily peeled from a support body.

  The wiring board is provided with a laminate that functions as an external connection member for connecting the semiconductor chip to an external device. Since the semiconductor chip and the wiring substrate having the external connection member can be manufactured separately, the manufacturing efficiency of the semiconductor device is improved. In this wiring board, the support has transparency. Since the adhesive force of the adhesive layer can be weakened by irradiating the adhesive layer with light, the support can be easily peeled from the laminate after the semiconductor chip and the laminate of the wiring substrate are joined. .

  Moreover, it is preferable that the linear expansion coefficient of a support body is -1 ppm / degrees C or more and 10 ppm / degrees C or less. Since the semiconductor chip is manufactured from a substrate mainly composed of an inorganic material such as a silicon substrate, the linear expansion coefficient of the semiconductor chip and the linear expansion coefficient of the support are close to each other. Therefore, it is possible to suppress the positional deviation that occurs when the semiconductor chip is mounted on the wiring board.

  The support may be a glass substrate. In this case, the support is inexpensive, can be increased in strength, and can be easily increased in size. Moreover, the roughness of the surface of a support body can be adjusted easily.

  The maximum height roughness of the main surface of the support is preferably 0.01 μm or more and 5 μm or less. In this case, since the unevenness of the laminate provided on the support is reduced, disconnection and short circuit of the wiring pattern can be suppressed.

  The adhesive layer is provided on the main surface of the support and includes a release layer containing a resin that can be decomposed by light irradiation, and a protective layer provided on the release layer and protecting the first laminate from light. You may have. In this case, by providing the protective layer between the release layer and the first stacked body, it is possible to suppress the transmission of light energy to the first stacked body. Therefore, it can suppress that resin contained in the resin layer of a laminated body decomposes | disassembles.

  Moreover, 0.001 mm or more and 5 mm or less may be sufficient as the thickness of the 1st laminated body provided on a glass layer, respectively. In this case, the wiring pattern in the laminate can be protected by the plurality of resin layers, and the warping of the wiring board can be suppressed.

  The thickness of the glass layer may be 0.05 mm or more and 1 mm or less.

  In addition, a semiconductor device according to the present invention is manufactured using any one of the above wiring boards, and includes a first stacked body, a glass layer provided on the first stacked body, and a glass layer. A second stacked body is provided, and a protruding electrode is provided on the surface, and a semiconductor chip connected to the second wiring pattern of the second stacked body via the protruding electrode.

  Further, the second wiring pattern and the semiconductor chip may be connected to each other via a connection terminal containing solder. In this case, even when a positional deviation occurs between the wiring pattern and the semiconductor chip, the deviation can be filled by the connection terminals including the solder, and the connection failure generated between the semiconductor chip and the laminated body is eliminated. Can be suppressed.

  Further, the wiring pattern and the semiconductor chip may be connected to each other through a connection terminal including gold. In this case, the conductivity of the connection terminal is improved and corrosion of the connection terminal is suppressed.

  In addition, a method of manufacturing a semiconductor device according to the present invention uses any one of the above-described wiring boards. The semiconductor chip is mounted on the second stacked body of the wiring board, and the semiconductor chip is formed on the second wiring pattern. And detaching the support from the first laminate by irradiating the adhesive layer with light through the support.

  According to this method for manufacturing a semiconductor device, the resin is decomposed by irradiating the adhesive layer with light through the support, and the adhesive force of the adhesive layer can be weakened. Therefore, since the support can be easily peeled off from the laminate after the semiconductor chip and the laminate of the wiring substrate are bonded, the semiconductor device manufactured using the wiring substrate can be thinned. Furthermore, handling can be facilitated by using a wiring substrate having a support when a semiconductor chip is mounted on the laminate.

  The light is preferably laser light, and the laser medium and laser wavelength are not limited. By irradiation with laser light, heat energy necessary for decomposing the resin in the adhesive layer can be sufficiently applied, and the adhesive force of the adhesive can be effectively weakened.

  The method for manufacturing a semiconductor device may further include a step of covering the semiconductor chip bonded to the second wiring pattern with a sealing resin. In this case, the semiconductor chip can be protected by the sealing resin, and the detachment of the semiconductor chip from the stacked body can be suppressed.

  The method for manufacturing a semiconductor device may further include a step of removing the adhesive layer from the first stacked body after the step of peeling the support from the first stacked body.

  The method for manufacturing a semiconductor device includes a step of providing an external connection terminal on the first stacked body after the step of peeling the support from the first stacked body, a first stacked body, a glass layer, and a second stacked body. And may be further divided into individual pieces.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device using the wiring board which can form fine wiring, a wiring board, and its manufacturing method can be provided.

The figure explaining the semiconductor device manufactured using the wiring board concerning an embodiment The figure explaining the wiring board concerning an embodiment The figure explaining the manufacturing process of the wiring board which concerns on embodiment The figure explaining the manufacturing process of the wiring board which concerns on embodiment The figure explaining the manufacturing process of the semiconductor device which concerns on embodiment The figure explaining the manufacturing process of the semiconductor device which concerns on embodiment The figure explaining the manufacturing process of the semiconductor device which concerns on an Example The figure explaining the manufacturing process of the semiconductor device which concerns on an Example

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted. In this specification, an example in which two resin layers are formed on both surfaces of a glass layer (glass core) will be described.

  FIG. 1 is a diagram for explaining a semiconductor device manufactured using the wiring board of this embodiment. As shown in FIG. 1, the semiconductor device 1 includes a stacked body 101, a stacked body 102, a glass layer (glass core) 20 having a through via 22, a semiconductor chip 29, an underfill 30, and a mold resin 31. A plurality of external connection terminals 32 and connection terminals 34 are provided. Details of the laminated body 101, the laminated body 102, and the glass layer 20 will be described later.

  The semiconductor chip 29 is an integrated circuit (IC or LSI) having, for example, a transistor or a diode formed on the surface of a semiconductor substrate, and has a substantially rectangular parallelepiped shape. The semiconductor substrate used for the semiconductor chip 29 is, for example, a substrate mainly composed of an inorganic material such as a silicon substrate (Si substrate), a gallium nitride substrate (GaN substrate), or a silicon carbide substrate (SiC substrate). In the present embodiment, a silicon substrate is used as the semiconductor substrate. The coefficient of linear expansion (CTE: Coefficient of Thermal Expansion) of the semiconductor chip 29 formed using the silicon substrate is about 2 to 4 ppm / ° C. (for example, 3 ppm / ° C.). The linear expansion coefficient in the present embodiment has a length that changes in response to a temperature rise within a temperature range of 20 ° C. to 260 ° C., for example.

  The surface 29 a of the semiconductor chip 29 and the wiring pattern exposed on the stacked body 102 are electrically connected via the connection terminal 34. The connection terminal 34 is, for example, a metal such as Au, Ag, Cu, Al or an alloy thereof, a metal composite obtained by applying Cu plating to Cu, or Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn. -Ag-Cu, Sn-Bi, or Au-based solder is used. The connection terminal 34 may be disposed in the entire region of the semiconductor chip 29 or may be disposed in the peripheral region of the semiconductor chip 29. Examples of a method for connecting the semiconductor chip 29 and the wiring board to each other include a wire bonding method and a flip chip method. In the present embodiment, the semiconductor chip 29 and the stacked body 102 are connected to each other by the flip chip method from the viewpoint of reducing the mounting area and improving the work efficiency.

  The underfill 30 is an adhesive used for fixing and sealing the semiconductor chip 29 on the stacked body 102. As the underfill 30, for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used. The underfill 30 may be liquid or film.

  The mold resin 31 is a sealing resin used for covering and protecting the semiconductor chip 29. As the mold resin 31, for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used.

  The external connection terminal 32 is provided on the stacked body 101. The external connection terminal 32 is electrically connected to the semiconductor chip 29 through a wiring pattern provided in the multilayer body 101 and a through via 22 provided in the glass layer 20. The external connection terminal 32 is formed of solder such as Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn—Ag—Cu, or Sn—Bi. When the external connection terminal 32 is formed of solder, before forming the external connection terminal 32, for example, Ni plating, Au plating, or Sn plating is applied to a portion where the wiring pattern on the main surface 101a of the multilayer body 101 is exposed. It may be applied, a pre-solder treatment may be applied, or an organic coating treatment such as OSP (Organic Solderability Preservative) may be applied.

  FIG. 2 is a diagram illustrating the wiring board according to the present embodiment. As shown in FIG. 2, the wiring board 11 includes a support body 12, an adhesive layer 13, a stacked body 101, and a stacked body 102. When the laminated body 101 is composed of, for example, two resin layers, the laminated body 101 includes a first resin layer 14, a second resin layer 19, a connection pad 15, and a wiring pattern 18. For example, when the laminated body 102 includes two resin layers, the third resin layer 21, the fourth resin layer 26, the wiring pattern 25, the connection pad 27, and the semiconductor chip 29 are electrically connected. And a connection terminal 28. The laminated body 101 and the laminated body 102 are electrically connected through a through via 22 provided in the glass layer 20 and filled with a conductor or the like. Note that the number of wirings can be increased by increasing a new resin layer in the stacked body 101 or the stacked body 103.

  The support 12 is a substrate made of a material having a property of transmitting light (transparency), for example. The main surface 12a of the support 12 has, for example, a substantially rectangular shape, a substantially circular shape, or a substantially elliptical shape. The range of the wavelength of light transmitted through the support 12 may be, for example, 100 nm or more and 2000 nm or less, or 300 nm or more and 1100 nm or less. As the support 12, a material that transmits a specific wavelength capable of decomposing the adhesive layer 13 may be used. For example, a glass substrate is used. When using a glass substrate, the component type and component ratio in glass, and its manufacturing method are not ask | required. For example, examples of the glass having different component types and component ratios include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, and any glass may be used. In addition, examples of the manufacturing method include a float method, a downdraw method, a fusion method, an updraw method, and a rollout method, and a glass substrate manufactured by any method may be used. The linear expansion coefficient of the glass substrate is preferably a value close to the linear expansion coefficient of the semiconductor chip 29 described above, for example, −1 ppm / ° C. or more and 10.0 ppm / ° C. or less (or 0.5 ppm / ° C. or more and 5.0 ppm / ° C.). ° C or lower). The maximum height roughness Rz on the main surface 12a of the support 12 based on JIS B 0601: 2013 may be, for example, 0.01 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less. When the maximum height roughness Rz of the main surface 12a of the support 12 is 0.01 μm or more, an increase in cost required for the support 12 can be suppressed. When the maximum height roughness Rz of the main surface 12a of the support 12 is 5 μm or less, disconnection, short circuit, and the like of the wiring pattern 18 due to the unevenness of the main surface 12a can be suppressed. Further, the shape of the support 12 is not limited, and any of a square, a round wafer with an orientation flat, or a round wafer may be used.

  The adhesive layer 13 is a layer for bonding the support 12 and the laminated body 101 to each other. The adhesive layer 13 is provided on the main surface 12a of the support 12 and contains a resin that can be decomposed by light irradiation. In the present embodiment, laser light is used as irradiation light. Therefore, as the resin contained in the adhesive layer 13, a resin that can be thermally decomposed by irradiation with laser light is used. Examples of the resin contained in the adhesive layer 13 include one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a resin in which two or more of these resins are mixed. Used. The thickness of the adhesive layer 13 is, for example, 20 μm to 100 μm.

  The first resin layer 14 is a resin layer provided on the adhesive layer 13 and has an opening 14a. The first resin layer 14 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. Moreover, the 1st resin layer 14 may contain the inorganic filler or the organic filler. The 1st resin layer 14 may also contain the material which the epoxy resin and glass fiber combined, for example. As the first resin layer 14, for example, a solder resist made of an epoxy insulating resin or the like may be used. The thickness of the first resin layer 14 is, for example, 0.5 μm to 30 μm.

  The connection pad 15 is a conductive layer made of a metal such as Au, and is provided in the opening 14 a of the first resin layer 14. The connection pad 15 may be in contact with the adhesive layer 13 in the opening 14a. The thickness of the connection pad 15 is, for example, 0.001 μm to 3 μm. When the connection pad 15 provided from the adhesive layer 13 side is formed by laminating one or more layers, for example, in the case of a single layer, one of Au, Pd, Sn, Cu, and in the case of two layers, Au / Ni, When the Au / Pd laminate is three layers, an Au / Pd / Ni laminate can be applied. Here, the metal layer can be formed by a plating method typified by a wet process or a sputtering method typified by a vacuum process. However, it is desirable to use a plating method in terms of tact, and electroless plating, electrolytic Any method of plating may be used.

  When the connection pad 15 provided from the adhesive layer 13 side is made of an alloy layer, a solder layer containing Sn and other elements, or a solder layer containing Au and other elements can be applied. For example, Sn- Examples thereof include a solder layer made of an alloy of Ag, Sn—Cu, Sn—Bi, Sn—Pb, Sn—Ag—Cu, Au—Si, Au—Sn, and Au—Ge. In addition, the alloy ratio of Sn and another element is not ask | required.

  In the connection pad 15, when the metal layer provided from the adhesive layer 13 side is composed of a metal layer formed by laminating one or more layers and an alloy layer, for example, Au / electroless Ni—P, Au / electroless Ni—B, As Au / electroless Pd—P / electroless Ni—P, a film in which an electroless Ni plating or an alloy film with an inorganic material of electroless Pd plating is laminated can be applied. However, the alloy film with the electroless Ni plating film or the electroless Pd plating film is not limited to an inorganic substance, and may contain a metal such as W (tungsten).

  The wiring pattern 18 is a conductive layer made of a metal such as Au, Cu, or Ni, and is provided on the first resin layer 14 and the connection pad 15. The wiring pattern 18 is electrically connected to the connection pad 15 through the opening 14 a of the first resin layer 14. The thickness of the wiring pattern 18 is, for example, 1 μm to 20 μm. Note that the wiring pattern 18 may contain inorganic impurities such as P and S.

  The second resin layer 19 is a resin layer provided on the first resin layer 14, the connection pad 15, and the wiring pattern 18. The second resin layer 19 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. Further, the second resin layer 19 may contain an inorganic filler or an organic filler. The opening 19 a provided in the second resin layer 19 does not overlap the opening 14 a of the first resin layer 14 and is provided so as to expose a part of the wiring pattern 18. The thickness of the second resin layer 19 is, for example, 0.5 μm to 30 μm.

  The second resin layer 19 may be provided with an opening by laser after the glass layer 20 and the third resin layer 21 are laminated on the second resin layer 19. At this time, vias are collectively formed in the second resin layer 19, the glass layer 2, and the third resin layer 21. Thus, the vias formed in the third resin layer 21, the glass layer 20, and the second resin layer 19 are filled with at least one kind of metal selected from Cu, Ni, Sn, or the like, or a conductive paste. May be. Further, the inside of the via may be made conductive by conformal plating and then filled with an interlayer insulating resin or a solder resist. Note that the laminated body 102 may be sequentially manufactured by pasting the glass provided with the vias in advance and making the vias conductive.

  The glass layer 20 is provided on the second resin layer 19 of the laminate 101. For the glass layer 20, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, photosensitive glass, sapphire glass, or the like can be used. In addition, for example, a glass manufacturing method such as a float method or a downdraw method is not limited. The thickness of the glass layer 20 is 0.05 mm or more and 1 mm or less, for example.

  The third resin layer 21 is a resin layer provided on the glass layer 20. The third resin layer 21 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. Further, the third resin layer 21 may contain an inorganic filler or an organic filler. The thickness of the third resin layer 21 is, for example, 0.5 μm to 30 μm.

  The wiring pattern 25 is a conductive layer made of a metal such as Au, Cu, or Ni, and is provided on the third resin layer 21. The wiring pattern 25 is electrically connected to the wiring pattern 18 through a through via 22 that penetrates the third resin layer 21, the glass layer 20, and the second resin layer 19. The thickness of the wiring pattern 25 is, for example, 1 μm to 20 μm. Note that the wiring pattern 25 may contain inorganic impurities such as P and S.

  The fourth resin layer 26 is a resin layer provided on the glass layer 20 and the wiring pattern 25. The fourth resin layer 26 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. The fourth resin layer 26 may contain an inorganic filler or an organic filler. The thickness of the fourth resin layer 26 is, for example, 0.5 μm to 30 μm.

  It is desirable to perform surface treatment for forming the connection terminals 28 on the connection pads 27 provided on the wiring pattern 25. The connection pad 27 is a conductive layer made of a metal such as Au, and is provided in the opening 26 a of the fourth resin layer 26. The thickness of the connection pad 27 is, for example, 0.001 μm to 3 μm. When the connection pad 27 is formed by laminating one or more layers, for example, in the case of a single layer, any one of Au, Pd, Sn, and Cu, and in the case of two layers, a laminate of Au / Ni and Au / Pd is used. In the case of three layers, a laminate of Au / Pd / Ni can be applied. Here, the formation method of the metal layer includes a plating method typified by a wet process and a sputtering method typified by a vacuum process, but it is desirable to use a plating method in terms of tact, and electroless plating, Any method of electrolytic plating may be used.

  When the connection pad 27 is made of an alloy layer, a solder layer containing Sn and other elements, or a solder layer containing Au and other elements can be applied, for example, Sn—Ag, Sn—Cu, Sn. Examples thereof include a solder layer made of an alloy of -Bi, Sn-Pb, Sn-Ag-Cu, Au-Si, Au-Sn, and Au-Ge. In addition, the alloy ratio of Sn and another element is not ask | required.

  In the connection pad 27, when the metal layer is composed of a metal layer formed by laminating one or more layers and an alloy layer, for example, Au / electroless Ni-P, Au / electroless Ni-B, Au / electroless Pd-P. / Electroless Ni plating, or a film in which an alloy film with an inorganic material of electroless Pd plating is laminated, such as electroless Ni-P. However, the alloy film with the electroless Ni plating film or the electroless Pd plating film is not limited to an inorganic material, and may contain a metal such as W. Further, an organic film treatment such as OSP may be performed on the connection pad 27.

  The connection terminal 28 provided on the connection pad 27 is a terminal provided in the opening 26 a of the fourth resin layer 26, and is provided so as to easily connect the wiring pattern 25 to the connection terminal of the semiconductor chip 29. Yes. The connection terminal 28 is formed of eutectic solder or lead-free solder (Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Bi, or the like), for example.

  The connection pad 27 may be a terminal provided with eutectic solder or lead-free solder on conductive layers made of various metals. Further, the connection pad 27 may be formed by performing plating processing of Ni, Au, Sn, or the like on the opening 26a or organic coating processing such as OSP. Further, the connection pad 27 may be formed by performing gold plating on the wiring pattern 25. In this case, the conductivity of the connection pad 27 is improved, and corrosion of the connection pad 27 is suppressed. The connection terminal 34 of the semiconductor chip 29 is a gold ball connection terminal (for example, a gold connection terminal made of Au, an alloy containing Au, or a metal composite having a surface plated with Au, or a connection terminal formed of Au-based solder. ), The bondability between the connection terminal 28 and the connection terminal 34 plated with gold is improved.

  Next, a method for manufacturing a wiring board according to the present embodiment will be described with reference to FIGS. 3A and 3B. 3A (a) to 3 (k) are diagrams for explaining an example of a method for manufacturing a wiring board, and FIGS. 3B (l) to (p) are diagrams for explaining an example of a method for manufacturing a wiring board. FIG. 3B is a diagram showing a step following FIG. 3A.

  First, as shown in FIG. 3A (a), the adhesive layer 13 is formed on the main surface 12 a of the support 12. The adhesive layer 13 is formed by a known method such as a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. The

  Next, as shown in FIG. 3A (b), after providing the first resin layer 14 on the adhesive layer 13, an opening 14 a is formed in the first resin layer 14. And the connection pad 15 is formed in the said opening part 14a. The first resin layer 14 is formed by a known method such as a printing method, a vacuum pressing method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done. The opening 14 a is formed by removing a part of the first resin layer 14 by, for example, performing laser irradiation or photolithography on the first resin layer 14. The connection pad 15 is provided by plating, for example. The connection pad 15 is not necessarily provided.

  Next, as shown in FIG. 3A (c), a seed layer 16 is provided on the first resin layer 14 and the connection pad 15. The seed layer 16 is connected to the connection pad 15 through the opening 14 a of the first resin layer 14. The seed layer 16 is formed by, for example, an electroless plating method, a sputtering method, a CVD method, or the like. Alternatively, the seed layer 16 may be formed by attaching a conductive foil made of Cu or the like to the first resin layer 14. The seed layer 16 is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, or an Ag / Pd alloy layer. In the present embodiment, a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability.

  Next, as shown in FIG. 3A (d), a resist 17 having an opening 17 a is provided on the seed layer 16. Then, a part of the seed layer 16 exposed by the opening 17a is thickened by, for example, performing a plating process. Here, a relatively thin region in the seed layer 16 is referred to as a first region 16a, and a relatively thick region is referred to as a second region 16b. The first region 16 a is a region existing between the first resin layer 14 and the resist 17. The second region 16b is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, an Ag / Pd alloy layer, or the like. In the present embodiment, a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability. Further, as the resist 17, for example, a negative type or positive type photoresist is used.

  Next, as shown in FIG. 3A (e), the wiring pattern 18 is formed by removing the resist 17 and the first region 16a in the seed layer 16. The resist 17 may be removed from the first resin layer 14 by, for example, lift-off, or may be removed by etching. The first region 16a is removed by wet etching or dry etching, for example. By removing the first region 16 a, the second region 16 b becomes the wiring pattern 18. A part of the second region 16b may be etched simultaneously with the first region 16a. That is, the wiring pattern 18 in the present embodiment is formed by a semi-additive method. In the semi-additive method, a seed layer such as a Cu layer is formed, a resist having a desired pattern is formed on the seed layer, and an exposed portion of the seed layer is thickened by an electrolytic plating method or the like to remove the resist. Thereafter, a thin seed layer is etched to obtain a wiring pattern.

  Further, as shown in FIG. 3A (f), after the wiring pattern 18 is formed, the second resin layer 19 is formed on the first resin layer 14 and the wiring pattern 18. The second resin layer 19 is formed by a known method such as a printing method, a vacuum pressing method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done.

  Next, as shown in FIG. 3A (g), a glass layer 20 is formed on the second resin layer 19. The glass layer 20 is formed by a known method such as a vacuum pressing method, a vacuum laminating method, or a roll laminating method. In order to improve adhesion between the second resin layer and the glass, an adhesive layer or a silane coupling agent layer may be provided on the second resin layer. Further, glass in which an adhesive layer or a resin layer is provided on one side or both sides in advance may be used as the glass layer 20.

  As described above, for the glass layer 20, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, photosensitive glass, sapphire glass, or the like can be used. In addition, for example, a glass manufacturing method such as a float method or a downdraw method is not limited.

  Next, as shown in FIG. 3A (h), a third resin layer 21 is formed on the glass layer 20. The third resin layer 21 is formed by a known method such as a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done.

  Next, as shown in FIG. 3A (i), the third resin layer 21, the glass layer 20, and the second resin layer 19 are opened by laser irradiation to form the through via 22. The through via 22 can be formed using a known laser technique such as a UV-YAG laser, a carbon dioxide laser, or an excimer laser.

  Next, as shown in FIG. 3A (j), a seed layer 23 is provided on the side wall of the through via 22 and the upper surface 21 a of the third resin layer 21. The seed layer 23 is formed by, for example, an electroless plating method, a sputtering method, a CVD method, or the like. The seed layer 23 is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, an Ag / Pd alloy layer, or the like. In the present embodiment, a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability.

  Next, as shown in FIG. 3A (k), the metal layer 24 is formed by conformal plating or via filling plating by electrolytic plating by energizing the inside of the through via 22 using the seed layer 23. To do. Here, when the metal layer 24 is formed on the side wall of the through via 22 and the surface layer 23a of the third resin layer by conformal plating, the hollow portion in the through via 22 is filled with a conductive paste or resin. The conductive paste is not limited in its metal species or resin species, and the mixing ratio is not limited.

  Next, as shown in FIGS. 3B (l) and 3 (m), a resist 17 is formed on the third resin layer 21 in the same manner as when the wiring pattern 18 is formed, and then the wiring pattern 25 is formed. Form.

  Next, as shown in FIG. 3B (n), a fourth resin layer 26 is formed on the third resin layer 21 and the wiring pattern 25. The fourth resin layer 26 is formed by a known method such as a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done. The fourth resin layer 26 may be a solder resist.

  Next, as shown in FIG. 3B (o), the opening 26a is provided in the fourth resin layer 26 by laser irradiation in the same manner as when the opening 14a is provided in the first resin layer 14.

  Finally, as shown in FIGS. 3B (p) and 3 (q), after the surface treatment is performed on the connection pad 27 in the opening 14a by a plating method, for example, a printing method, a ball transfer, a plating method, or the like. Thus, the connection terminal 28 is formed. By the above, the wiring board 11 provided with the support body 12, the adhesive layer 13, the laminated body 101, the laminated body 102, and the glass layer 20 is formed.

  Next, with reference to FIGS. 4A to 4E and FIGS. 5A to 5D, a method for manufacturing a semiconductor device using the wiring substrate according to the present embodiment will be described. 4A to 4E and 5A to 5D are diagrams illustrating an example of a method for manufacturing a semiconductor device.

  First, as shown in FIG. 4A, a wiring board 11 having a support 12, an adhesive layer 13, a laminate 101, a glass layer 20, and a laminate 102 is prepared. The wiring board 11 is equivalent to the wiring board 11 shown by FIG. 2 or FIG. 3B (p).

  Next, as shown in FIG. 4B, a plurality of semiconductor chips 29 are mounted on the wiring board 11. Specifically, the semiconductor chip 29 is mounted on one main surface 101a of the wiring board 11 by a flip chip method. When the semiconductor chip 29 is mounted on the wiring board 11, the connection terminal 34 of the semiconductor chip 29 and the connection terminal 28 (see FIG. 2) of the wiring board 11 are connected to each other. Further, by providing an underfill 30 between the semiconductor chip 29 and the wiring substrate 11, the semiconductor chip 29 and the wiring substrate 11 are fixed and sealed. The underfill 30 may be supplied between the semiconductor chip 29 and the wiring substrate 11 after the semiconductor chip 29 is mounted on the wiring substrate 11. Alternatively, the underfill 30 may be attached to the semiconductor chip 29 or the wiring board 11 in advance, and the sealing with the underfill 30 may be completed simultaneously with mounting the semiconductor chip on the wiring board. For example, the semiconductor chip 29 and the wiring substrate 11 are fixed and sealed with the underfill 30 by applying a curing process to the underfill 30 by heating or light irradiation. The underfill 30 is not necessarily provided.

  Next, as illustrated in FIG. 4C, a mold resin 31 is formed on one main surface 101 a of the wiring substrate 11. At this time, the semiconductor chip 29 is embedded with the mold resin 31. The mold resin 31 is formed by a known method such as a transfer molding method or a potting method. The semiconductor chip 29 may be covered so as to be sealed with the mold resin 31.

  Next, as shown in FIG. 4D, the adhesive layer 13 is irradiated with a laser beam 51 through the support 12. The laser beam 51 may be irradiated over the entire support 12, or the laser beam L may be irradiated to a desired position of the support 12. In the present embodiment, from the viewpoint of reliably decomposing the resin in the adhesive layer 13, the entire support 12 is irradiated with the laser light L while reciprocating linearly. For example, the laser beam L may have a wavelength of 100 nm to 2000 nm, may have a wavelength of 300 nm to 1500 nm, and may have a wavelength of 300 nm to 1100 nm. As an example of a device that emits laser light L, there is a YAG laser device that emits light with a wavelength of 1064 nm, a second harmonic YAG laser device with a wavelength of 532 nm, or a semiconductor laser device that emits light with a wavelength of 780 to 1300 nm. Can be mentioned. The support 12 has transparency and transmits the laser light L. Therefore, the energy of the laser beam 51 that has passed through the support 12 is absorbed by the adhesive layer 13. The absorbed energy of the laser beam L is converted into thermal energy in the adhesive layer 13. By this thermal energy, the resin of the adhesive layer 13 reaches the thermal decomposition temperature and is thermally decomposed. Thereby, the force with which the adhesive layer 13 bonds the support 12 and the laminate 101 is weakened.

  Next, as shown in FIG. 4 (e), the support 12 is peeled from the laminate 101. The method of peeling the support body 12 from the laminated body 101 may be performed manually or using a machine. When the adhesive layer 13 is attached to the laminated body 101, the adhesive layer 13 is removed from the laminated body 101. For example, the adhesive layer 13 remaining on the other main surface 101b is removed from the laminate 101 by peeling after sticking an adhesive tape to the other main surface 101b of the laminate 101. Alternatively, the other main surface 101b may be immersed in a mixed solution of an aqueous potassium permanganate solution and an aqueous sodium hydroxide solution to remove the adhesive layer 13, or the mixed solution may be sprayed on the other main surface 101b. By doing so, the adhesive layer 13 may be removed. Alternatively, the other main surface 101b may be immersed in an organic solvent such as acetone or methyl ethyl ketone to remove the adhesive layer 13, or the organic layer may be sprayed onto the other main surface 101b to form the adhesive layer 13. It may be removed. Further, the adhesive layer 13 may remain on the other main surface 101b, but in this case, it is necessary to form an opening for providing the external connection terminal 32 using a laser beam or the like. In this way, the support 12 and the adhesive layer 13 are removed from the laminate 101 as shown in FIG.

  Next, as shown in FIGS. 5A and 5B, a plurality of external connection terminals 32 are formed on the other main surface 101 b of the multilayer body 101. Specifically, the external connection terminals 31 are formed in portions corresponding to the connection pads 15 (see FIG. 2) of the stacked body 101. For example, the external connection terminals 32 are formed by a solder ball mounting method or solder printing.

  Next, as shown in FIG. 5C, after the dicing tape 33 is attached to the mold resin 31, the laminated body 101, the glass layer 20, the laminated body 102, The mold resin 31 is cut into pieces. For example, the laminated body 101, the glass layer 20, the laminated body 102, and the mold resin 31 are cut using a dicing saw or a laser. As described above, as shown in FIG. 5D, the semiconductor device 1 formed using the wiring substrate 11 is manufactured.

  The wiring board 11 according to the present embodiment described above includes the stacked body 101 that functions as an external connection member for connecting the semiconductor chip 29 in the semiconductor device 1 to an external device. Thereby, since the semiconductor chip 29 and the wiring substrate 11 having the external connection member can be manufactured separately, the manufacturing efficiency of the semiconductor device 1 can be improved. Further, in this wiring board 11, the support 12 has transparency. Thereby, resin can be decomposed | disassembled by irradiating light to the adhesive bond layer 13 through the support body 12, and the adhesive force of the adhesive bond layer 13 can be weakened. Therefore, after bonding the semiconductor chip 29 and the laminate 101 of the wiring substrate 11, the support 12 can be easily peeled from the laminate 101, and the semiconductor device 1 manufactured using the wiring substrate 11 is thin. Can be realized. Further, by manufacturing the semiconductor device 1 using the wiring substrate 11 having the support 12, the wiring substrate 11 can be easily handled.

  Further, the linear expansion coefficient of the support 12 may be −1 ppm / ° C. or more and 10 ppm / ° C. or less. In this case, since the semiconductor chip 29 is manufactured using a substrate mainly composed of an inorganic substance such as a silicon substrate, the linear expansion coefficient of the semiconductor chip 29 and the linear expansion coefficient of the support 12 are close to each other. For this reason, it is possible to suppress misalignment that occurs when the semiconductor chip 29 is mounted on the wiring board 11. Therefore, it becomes possible to prevent the semiconductor chip 29 from being mounted on the wiring substrate 11 and to destroy the portion where the semiconductor chip 29 and the wiring substrate 11 are joined.

  Moreover, when the support body 12 is a glass substrate, while making the support body 12 inexpensive and high intensity | strength, the enlargement of the support body 12 can be made easy. Further, the roughness of the surface of the support 12 can be easily adjusted.

  When the maximum height roughness Rz of the main surface 12a of the support 12 is not less than 0.01 μm and not more than 5 μm, the unevenness of the laminate 101 provided on the support 12 is reduced, so that the wiring pattern 18 is disconnected and short-circuited. Etc. can be suppressed.

  In addition, when the light applied to the adhesive layer 13 is laser light, sufficient heat energy can be applied to decompose the resin in the adhesive layer 13, and the adhesive force of the adhesive layer 13 is effective. Can be weakened. Further, since the laser light is irradiated to the adhesive layer 13 through the support 12, the adhesive force of the adhesive layer 13 can be effectively weakened without damaging the semiconductor chip 29 by the laser light.

  The wiring board, the semiconductor device, and the manufacturing method of the semiconductor device according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, you may combine the said embodiment and modification suitably. Further, a plurality of semiconductor chips 29 stacked on the stacked body 101 may be mounted in a region of the wiring board 11 to be separated. In addition, a member other than the semiconductor chip 29 (for example, a passive component such as a capacitor) may be mounted on the stacked body 101.

  For example, the opening 14a in the first resin layer 14 and the opening 19a in the second resin layer 19 may overlap each other. Furthermore, for example, the connection terminal 28 in the stacked body 102 is not necessarily provided.

  Further, the wiring patterns 18 and 25 on the wiring substrate 11 are not limited to the semi-additive method, and are formed by a known method such as a subtractive method or a full additive method. Here, the subtractive method is a method in which a resist having a desired pattern is formed on a conductor layer such as a Cu layer, an unnecessary conductor layer is etched, and then the resist is removed to obtain a wiring pattern. In the full additive method, an electroless plating catalyst is adsorbed on the resin layer, a resist having a desired pattern is formed on the resin layer, and the catalyst is activated while leaving the resist as an insulating film. In this method, after a conductor such as Cu is deposited in the resist opening by the method, the resist is removed to obtain a desired wiring pattern.

  The glass layer 20 may be provided with a resin layer and a wiring pattern on both sides of the glass layer 20 without forming the through via 22.

  Further, a new resin layer and a wiring pattern may be provided on the second resin layer 19 and / or on the fourth resin layer 26. As a result, multilayer laminates 101 and 102 in which the desired number of wiring patterns and resin layers are laminated can be obtained.

  The present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

(Wiring board)
6A and 6B are diagrams for explaining a method of manufacturing a semiconductor device according to the example.

  First, as shown in FIG. 6A (a), a release layer 41 and a protective layer 42 were formed in order on the main surface 12a of the support 12. As the support 12, glass (OA-10G (manufactured by Nippon Electric Glass Co., Ltd.), 1.1 mm thickness) was used. The linear expansion coefficient of the support 12 was about 4 ppm / ° C. The release layer 41 on the main surface 12a of the support 12 was formed using 3M Light-To-Heat-Conversion (LTHC) Release Coating (manufactured by Sumitomo 3M Limited). The protective layer 42 was formed using 3M UV-Curable Adhesive LC-5200 (manufactured by Sumitomo 3M Limited). The release layer 41 and the protective layer 42 were both formed by spin coating. These release layer 41 and protective layer 42 correspond to the adhesive layer 13 shown in FIG.

  Next, GX-T31 (30 μmt) manufactured by Ajinomoto Fine Techno Co., Ltd. was provided as the first resin layer 14 on the protective layer 42 by a vacuum laminating method, and then an opening 14a having a diameter of 500 μm was formed by laser irradiation. Next, after the connection pad 15 was formed in the opening 14a (FIG. 6A (b)), the wiring pattern 18 was formed by a semi-additive method (FIGS. 6A (c) to (e)). Next, after forming GX-T31 (30 μmt) by the vacuum laminating method as the second resin layer 19 (FIG. 6A (f)), the glass layer 20 (OA-10G (OA-10G, Japan) having a thickness of 100 μm is formed on the second resin layer 19. (FIG. 6A (g)) After forming GX-T31 (30 μmt) as a third resin layer 21 on the glass layer 20 by a vacuum laminating method (FIG. 6A (h) )), A through via 22 having a diameter of 50 μm was formed in the second resin layer 19, the glass layer 20, and the third resin layer 21 by a carbon dioxide laser (FIG. 6A (i)). Then, the inside of the through via 22 was made conductive, and after filling by electrolytic copper plating, a wiring pattern 25 was formed (FIG. 6A (j) to FIG. 6B (m)). GX-T31 (30 μmt) was formed (FIG. 6B (n)) Next, an opening 26a of φ90 μm was provided in the fourth resin layer 26 by a laser (FIG. 6B (o)), and a part of the wiring pattern 25 was formed. Next, electroless Ni / Au plating is applied to the exposed wiring pattern 25 to form a connection pad 27 (FIG. 6B (p)), and Sn-3 wt% Ag-0.5 wt% of φ90 μm is formed. Cu solder (connection terminal 28) was mounted at a peak temperature of 260 ° C. to obtain a wiring board 11A according to this example (FIG. 6B (q)). It was also confirmed that a Cu pattern of L / S = 5/5 μm could be formed for the wiring pattern 25 in the laminate 102.

(Semiconductor device)
Next, the semiconductor chip 29 was mounted on the obtained wiring board 11A. As the semiconductor chip 29, one having a protruding electrode in which a Sn-3.5Ag solder layer was formed at the tip of a Cu post was used. Further, the linear expansion coefficient of the semiconductor chip 29 was about 3 ppm / ° C. An underfill 30 was previously supplied to the wiring board 11. After aligning the protruding electrode of the semiconductor chip 29 with the connection terminal 28 of the wiring board 11A, the semiconductor chip 29 was pressure-bonded to the wiring board 11 and heated. Thereafter, the upper surface of the wiring board 11A including the semiconductor chip 29 was sealed with a mold resin 31 by a transfer molding method. Then, the support 12 was removed from the wiring board 11 by irradiating the entire support with a 1064 nm YAG laser while linearly reciprocating from the support 12 side of the wiring board 11. Furthermore, the adhesive layer 13 was removed from the wiring board 11 by peeling the adhesive tape after affixing the adhesive tape to the laminate 101 and the adhesive layer 13. Next, Sn-3 wt% Ag-0.5 wt% Cu solder balls were mounted on the laminate 101 to form external connection terminals 32. This structure was affixed to a dicing tape and diced to obtain the semiconductor device 1 shown in FIG.

  The present invention can be used for a semiconductor wafer level package and its manufacture.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 11, 11A ... Wiring board 101, 101a ... Laminated body 102, 102a ... Laminated body 12 ... Support body 13 ... Adhesive layer 14 ... 1st resin layer DESCRIPTION OF SYMBOLS 15 ... Connection pad 16 ... Seed layer 17 ... Resist 18 ... Wiring pattern 19 ... 2nd resin layer 20 ... Glass layer 21, 21a ... 3rd resin layer 22 ... Via 23 ... Seed layer 24 ... Plating layer 25 ... Wiring pattern 26, 26a ... Fourth resin layer 27 ... Connection pad 28 ... Connection terminal 29 ... Semiconductor chip 30 .... Underfill 31 ... mold resin 32 ... connecting terminal 33 ... dicing tape 34 ... connecting terminal 51 ... laser light

Claims (15)

  1. A wiring board,
    A transparent support;
    An adhesive layer comprising a resin provided on the support and decomposable by light irradiation;
    A first laminate provided on the adhesive layer, the first laminate having two or more resin layers and one or more first wiring patterns provided between the resin layers;
    A glass layer provided on the first laminate;
    A second laminated body provided on the glass layer, comprising a second laminated body having two or more resin layers and one or more second wiring patterns provided between the resin layers; Wiring board.
  2.   The wiring board according to claim 1, wherein the support has a linear expansion coefficient of −1 ppm / ° C. or more and 10 ppm / ° C. or less.
  3.   The wiring substrate according to claim 1, wherein the support is a glass substrate.
  4.   The wiring board according to claim 1, wherein a maximum height roughness of the main surface of the support is 0.01 μm or more and 5 μm or less.
  5. The glass layer has vias;
    5. The wiring board according to claim 1, wherein the first wiring pattern and the second wiring pattern are electrically connected through the via in the glass layer. 6.
  6.   The wiring board according to claim 1, wherein a semiconductor chip is mounted on the second stacked body.
  7.   The wiring board according to claim 1, wherein the glass layer has a thickness of 0.05 mm or more and 1 mm or less.
  8. The adhesive layer is
    A release layer that is provided on the main surface of the support and contains a resin that can be decomposed by light irradiation;
    The wiring board according to claim 1, further comprising a protective layer provided on the release layer and protecting the first stacked body from the light.
  9. A semiconductor device manufactured using the wiring board according to claim 1,
    The first laminate;
    A glass layer provided on the first laminate;
    The second laminate provided on the glass layer;
    A semiconductor device comprising: a protruding electrode provided on a surface; and a semiconductor chip connected to the second wiring pattern of the second stacked body via the protruding electrode.
  10.   The semiconductor device according to claim 9, wherein the second wiring pattern and the semiconductor chip are connected to each other via a connection terminal including solder.
  11. A method for manufacturing a semiconductor device using the wiring board according to claim 1,
    Mounting a semiconductor chip on the second stacked body of the wiring substrate, and bonding the semiconductor chip to the second wiring pattern;
    And a step of peeling the support from the first stacked body by irradiating the adhesive layer with light through the support.
  12.   The method of manufacturing a semiconductor device according to claim 11, wherein the light is laser light.
  13. The method for manufacturing a semiconductor device according to claim 11, further comprising a step of covering the semiconductor chip bonded to the second wiring pattern with a sealing resin.
  14.   The semiconductor device according to any one of claims 11 to 13, further comprising a step of removing the adhesive layer from the first stacked body after the step of peeling the support from the first stacked body. Production method.
  15. After the step of peeling the support from the first laminate, providing an external connection terminal on the first laminate;
    The method for manufacturing a semiconductor device according to claim 11, further comprising a step of cutting and separating the first stacked body, the glass layer, and the second stacked body.
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FR2042059A5 (en) * 1969-04-02 1971-02-05 Ibm
CN1656612A (en) * 2002-05-23 2005-08-17 肖特股份公司 Glass material for use at high frequencies
JP4072176B2 (en) * 2005-08-29 2008-04-09 新光電気工業株式会社 Manufacturing method of multilayer wiring board
JP2007150171A (en) * 2005-11-30 2007-06-14 Kyocer Slc Technologies Corp Manufacturing method for wiring board
US9420707B2 (en) * 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
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JP2012069734A (en) * 2010-09-24 2012-04-05 Toshiba Corp Manufacturing method of semiconductor device
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JP6081693B2 (en) * 2011-09-12 2017-02-15 新光電気工業株式会社 Wiring board and method of manufacturing wiring board
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