JP4161909B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of an SiP and reducible in cost owing to its high yield and shortening its lead time, and a manufacturing method thereof, and electronic components, semiconductor chips and a package substrate which are used for the semiconductor device. <P>SOLUTION: In the manufacturing method of the semiconductor device on the region of a first conductive substrate 10, 11 having a conductive surface wherefrom a second-conductive-layer forming region is excluded, there is so formed a first resin pattern 12p whose adhesiveness is lower with respect to the surface of an uncured resin sheet than to the surface of the first conductive substrate as to form a master substrate for forming a second conductive layer. By using the first resin pattern as a mask, the second conductive layer 13 is so pattern-formed on the first conductive substrate present in the second-conductive-layer forming region, and the first uncured resin sheet 14 is so stuck on the upper layer of the pattern-formed second conductive layer 13 as to perform exfoliation in the interface between the first uncured resin sheet and the first resin pattern, and in the interface between the second conductive layer and the first conductive substrate. The obtained first uncured resin sheet whereon the second conductive layer is transcribed is so laminated on the first conductive layer of a package substrate as to be changed into a first insulation layer by curing the first uncured resin sheet. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in a form called system-in-package.

  With the miniaturization of semiconductor devices, the minimum processing size of a conductive layer used as a redistribution layer in a SiP (system in package) type semiconductor device (module packaged with an electronic component such as a semiconductor chip) However, there is a demand for further miniaturization.

  As a conventional method of manufacturing a semiconductor device in the form of SiP, for example, a semiconductor chip or other passive component is mounted on a substrate serving as a core, a copper foil is laminated thereon via an insulating resin layer, and laser irradiation is performed. A plating process is performed so that a via hole is opened and buried in the via hole to form a conductive layer, and a copper foil is patterned by etching to form a conductive layer pattern. Further, the conductive layer pattern is laminated on the upper layer by repeating each process such as the lamination of the copper foil through the insulating resin layer, the opening and plating of the via hole, and the pattern processing of the copper foil, thereby forming a rewiring layer.

  However, in the above-described method for manufacturing a semiconductor device in the SiP form, defects are likely to occur frequently in the etching process of a fine wiring pattern after mounting an expensive semiconductor chip or electronic component. In addition to discarding the entire semiconductor chip and the like, there is a disadvantage that the manufacturing cost increases due to low yield.

  On the other hand, as a conventional method for manufacturing a miniaturized mounting substrate, as described in Patent Document 1, for example, a plating resist is formed along a pattern to be formed on a substrate whose surface is conductive. Then, a conductive substrate is patterned by using a plating resist as a mask by an electroplating method in which the substrate is energized, and the obtained conductive layer is bonded to an uncured resin sheet, and the substrate is removed by peeling or etching. Thus, a method for transferring a conductive layer is known.

However, in the above-described mounting substrate manufacturing method, when removing the substrate by etching, as well as in the case of peeling, the plating resist does not inherently withstand repeated use. There is a problem that it is necessary to prepare a substrate having a conductive surface each time and to form a pattern of a plating resist, which increases the manufacturing cost.
Further, since the peeling process itself is very difficult, defects are likely to occur, and the yield is low, it has not been practically a method that can withstand manufacturing.
Further, in the above-described method, it is necessary to prepare a substrate having a conductive surface for each production lot of the substrate and to form a pattern of a plating resist.

As described above, there has been a demand for a method of manufacturing a SiP-type semiconductor device that can be manufactured at a high yield while suppressing the part manufacturing cost, a semiconductor device manufactured thereby, and a semiconductor chip and a package substrate that constitute the semiconductor device.
JP 2000-151078 A JP 2003-13246 A

  The problem to be solved is that the conventional SiP type semiconductor device has a low yield in the manufacturing process and a high manufacturing cost.

  The method for manufacturing a semiconductor device of the present invention includes a step of patterning a first conductive layer on a package substrate, and a region excluding a second conductive layer formation region on the first conductive substrate having at least a surface conductive. Forming a second conductive layer forming master substrate by forming a first resin pattern having lower adhesion to the surface of the uncured resin sheet than the surface of the first conductive substrate; and the first resin Using the pattern as a mask, patterning the second conductive layer on the first conductive substrate in the second conductive layer formation region, and from the second conductive layer side to the master substrate for forming the second conductive layer The step of bonding the first uncured resin sheet, peeling at the interface between the first uncured resin sheet and the first resin pattern, and the interface between the second conductive layer and the first conductive substrate, and the second conductive Layer above 1 a step of transferring onto the uncured resin sheet, a surface of the first uncured resin sheet opposite to the surface to which the second conductive layer is transferred, and the first conductive layer of the package substrate. A step of bonding the surfaces together, and a step of curing the first uncured resin sheet to form a first insulating layer.

In the method of manufacturing a semiconductor device according to the present invention, first, a first conductive layer is patterned on a package substrate.
On the other hand, at least in the region excluding the second conductive layer forming region on the first conductive substrate whose surface is conductive, the first adhesive substrate has lower adhesion to the surface of the uncured resin sheet than the surface of the first conductive substrate. Forming a first resin pattern to form a second conductive layer forming master substrate, and using the first resin pattern as a mask, patterning the second conductive layer on the first conductive substrate in the second conductive layer formation region; The first uncured resin sheet is bonded to the master substrate for forming the second conductive layer from the second conductive layer side, the interface between the uncured resin sheet and the first resin pattern, the second conductive layer, and the first conductive substrate. The second conductive layer is transferred onto the first uncured resin sheet.
Next, the surface of the first uncured resin sheet opposite to the surface on which the second conductive layer is transferred is bonded to the surface of the package substrate on which the first conductive layer is formed, and the first uncured resin sheet is attached. Cured to form the first insulating layer.

  In the method of manufacturing a semiconductor device according to the present invention, when a SiP-type semiconductor device is manufactured, the second conductive layer is formed by a full additive method using a master substrate that can be repeatedly used. Therefore, there is no loss of semiconductors or electronic parts, yield can be increased, and manufacturing cost can be reduced.

  Embodiments of a semiconductor device manufacturing method, a semiconductor device manufactured thereby, and a semiconductor chip and a package substrate used therewith will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a SiP (system in package) semiconductor device according to the present embodiment.
For example, an electronic circuit including an active element 31 such as a transistor or a diode is formed on a silicon semiconductor substrate 30, and an interlayer insulating film 32 such as silicon oxide is formed on the surface thereof.
A passive element 33 such as a capacitance element, an electric resistance element, and an inductance is formed on the upper layer of the interlayer insulating film 32. Further, for example, aluminum is connected so as to connect an electronic circuit such as the active element 31 and the passive element 33. A first conductive layer 34 made of is patterned on the interlayer insulating film 32.
In addition, after the second conductive layer 13 is laminated on the first conductive layer 34 via the first insulating layer 14 ′ as described later, the second conductive layer 13 and the first insulating layer 14 ′ are penetrated. In a region including the formation region of the first through opening V ₁ formed so as to reach the first conductive layer 34, a conductive first conductive layer protective layer 35 that reflects light on the surface of the first conductive layer 34 is provided. Is formed.
As described above, the package substrate of the SiP type semiconductor device according to the present embodiment is configured.

A semiconductor chip 20 provided with an electronic circuit including an active element such as a transistor is mounted on the upper layer of the first conductive layer 34, the active element 31 or the passive element 33 via a die attach film 24.
Here, the semiconductor chip 20 is provided with a pad 22 on the surface of the semiconductor chip body, and the surface of the semiconductor chip body in a region excluding the pad is covered with a protective layer such as silicon oxide.
In addition, a conductive pad protection layer 22 b that reflects light is formed on the outermost surface of the pad 22.

Instead of the semiconductor chip or in addition to the semiconductor chip, another electronic component such as a passive element may be mounted.
The electronic component in this case has a configuration in which a conductive electrode protective layer that reflects light is formed on the outermost surface of the electrode provided on the surface of the electronic component main body, similarly to the semiconductor chip.

The first conductive layer 34 and the semiconductor chip 20 are covered, and a first insulating layer 14 ′ made of an insulating resin is bonded. The second conductive layer 13 is patterned on the upper layer.
Further, a second conductive layer 13 and the first through-opening V ₁ to reach the first conductive layer protective layer 35 is formed through the first insulating layer 14 ', through the first conductive layer protective layer 35 A first through wiring 36 penetrating the first insulating layer 14 ′ is formed so as to connect the first conductive layer 34 and the second conductive layer 13.
Further, a second through-opening V ₂ that penetrates through the second conductive layer 13 and the first insulating layer 14 ′ and reaches the pad protection layer 22 b is formed, and the pad 22 of the semiconductor chip 20 is interposed through the pad protection layer 22 b. A second through wiring (pad through wiring) 37 is formed through the insulating layer 14 ′ so as to connect the first conductive layer 13 and the second conductive layer 13.
When other electronic components such as passive elements are mounted instead of the semiconductor chip or in addition to the semiconductor chip as described above, the through opening penetrates the second conductive layer and the first insulating layer. The through hole wiring for the electronic component electrode is formed through the insulating layer so as to connect the electrode of the electronic component and the second conductive layer through the electrode protective layer. Shall.

Further, the second conductive layer 13 is covered, and the second insulating layer 16 ′ made of an insulating resin is bonded to the upper layer of the first insulating layer 14 ′, and the third conductive layer 15 is patterned on the upper layer. Has been.
A third through-opening V ₃ that penetrates through the third conductive layer 15 and the second insulating layer 16 ′ and reaches the second conductive layer 13 is formed, and connects the second conductive layer 13 and the third conductive layer 15. Thus, a third through wiring 38 penetrating through the second insulating layer 16 ′ is formed.
Furthermore, a fourth through opening V ₄ is formed so as to penetrate the third conductive layer 15, the second insulating layer 16 ′, and the first insulating layer 14 ′ and reach the first conductive layer protective layer 35. A fourth through wiring 39 penetrating through the second insulating layer 16 ′ and the first insulating layer 14 ′ is formed so as to connect the first conductive layer 34 and the third conductive layer 15 via the layer protective layer 35.
A solder resist 40 is formed on the second insulating layer 16 ′ and the third conductive layer 15 that has not been selected, except for the formation region of the third conductive layer 15 selected so as to be exposed.
Bumps (projection electrodes) 41 made of solder balls or the like are formed at necessary portions of the selected and exposed third conductive layer 15.

In the above configuration, the first conductive layer 34, the second conductive layer 13, the third conductive layer 15, the first through wiring 36, the second through wiring 37, the third through wiring 38, and the fourth through wiring 39 are each formed of SiP. The rewiring layer is formed along a pattern according to the design.
Here, the minimum processing dimension of the second conductive layer 13 and the third conductive layer 15 is about 10 μm (line / space = about 10/10 μm), which is a fine pattern. However, a region having a width or diameter of about several tens of μm is formed in the contact portion where the first to fourth through openings are provided, and the first to fourth throughs having a diameter of, for example, about 15 to 30 μm are formed in the contact portion. An opening is formed.

The SiP-type semiconductor device of this embodiment is manufactured by a manufacturing method to be described later, and is a conductive material that reflects the light to the interface between the first through wiring and the first conductive layer to protect the first conductive layer. The first conductive layer protective layer is provided, and a conductive pad protective layer that reflects light to protect the pad is provided at the interface between the pad through-wiring and the pad of the semiconductor chip. Thus, the first conductive layer and the pad are prevented from being damaged when the through opening that reaches the first conductive layer and the pad through the second conductive layer and the first insulating layer is formed. In the case where the second conductive layer is formed and laminated by the full additive method capable of realizing a high-definition pattern as described above and connected to the pad of the semiconductor chip, the yield can be increased and the manufacturing cost can be reduced.
In addition, the first conductive layer is prevented from being damaged even in the through opening that penetrates the third conductive layer, the second insulating layer, and the first insulating layer and reaches the first conductive layer. , Increase yield and reduce manufacturing cost.

Next, a method for manufacturing a SiP-type semiconductor device according to this embodiment will be described.
First, on a glass substrate 10 having a thickness of 3 mm made of heat-resistant glass that transmits light such as ultraviolet rays as shown in FIG. 2A, as shown in FIG. A conductive film 11 such as an ITO (Indium Tin Oxide) film having a film thickness of 5 μm is formed by a method, and a first conductive substrate having at least a surface conductive is formed.
The ITO film is formed, for example, by using ITO pellets (5% by weight) as a deposition source and treating at a substrate temperature of 300 ° C. for 20 minutes.
A substrate provided with a conductive film such as an ITO film in advance may be purchased and used as the conductive substrate.
In the case of an ITO film, it is advantageous when peeling from the second conductive layer in a later process because of its low adhesiveness to other metals, and since it has high light transmission, when uncured resin sheets are laminated and peeled off. Laser light such as an excimer laser to be used can be effectively irradiated. Also, it functions as a common electrode when forming the second conductive layer.

Next, as shown in FIG. 2C, for example, a fine recess 11a is formed on the surface of the conductive film 11 by reverse sputtering, and processed into a surface having a surface roughness of about 1 μm. For example, Ar gas is used under normal reverse sputtering conditions such as RF 50 W and processing time of 5 minutes.
Thereby, adhesiveness with the resin layer for pattern formation formed later improves. Furthermore, the concavo-convex shape is transferred to the second conductive layer formed in a later step on the conductive film, and the adhesion between the second conductive layer and the uncured resin sheet is improved.

Next, as shown in FIG. 2 (d), for example, by spin coating, the conductive film 11 formed on the surface of the conductive substrate has a property of being less adhesive to the surface of the uncured resin sheet. A liquid resin is applied, dried, and pre-baked to form a resin layer 12 with a thickness of 5 μm. As the resin constituting the resin layer 12, a fluorine-based resin (manufactured by Minoru Sangyo Co., Ltd., trade name GT2300 PFA) or the like can be used. Since the fluororesin is excellent in chemical resistance and heat resistance, it is preferable because it improves the durability of the obtained master substrate and can be used repeatedly.
The spin coating conditions are, for example, 800 rpm for 30 seconds, 1200 rpm for 30 seconds, and prebaking conditions are 90 ° C. for 4 minutes and 110 ° C. for 4 minutes.

Next, as shown in FIG. 3A, the resin layer 12 in the second conductive layer formation region is removed by, for example, laser drawing, and the first resin remaining in the region other than the second conductive layer formation region is removed. A pattern 12p is formed, and a master substrate for forming the second conductive layer is formed. For example, the minimum processing dimension of the resin pattern 12p is 10 μm (the line / space width is 10 μm / 10 μm).
The laser drawing condition is a normal condition using a laser drawing apparatus and is performed at a frequency of 25 kHz.
Alternatively, a resist film (not shown) may be patterned, and the resin layer 12 may be patterned by etching to form the first resin pattern 12p as described above.

Next, as shown in FIG. 3B, for example, in the electrolytic plating method in which the first conductive substrate having the conductive film 11 formed on the glass substrate 10 is energized and the conductive film 11 is used as a common electrode, sulfuric acid is used. The conductive film 11 is energized by being immersed in a plating solution such as a copper aqueous solution, and the second conductive layer 13 is patterned on the first conductive substrate in the second conductive layer formation region using the resin pattern 12p as a mask.
As described above, the minimum processing dimension of the resin pattern is formed as 10 μm (line / space width is 10 μm / 10 μm), and the second conductive layer 13 is patterned using this as a mask. It can be formed with a minimum processing dimension of 10 μm (line / space width of 10 μm / 10 μm).
At this time, the film thickness of the second conductive layer 13 is formed to be larger than the film thickness of the resin pattern 12p. For example, if the thickness of the resin pattern 12p is about 5 μm, the thickness of the second conductive layer 13 is set to about 6 μm.

Next, as shown in FIG. 3C, for example, by immersing in a surface roughening agent (trade name NBS2 manufactured by Ebara Densan) for about 5 minutes, fine concave portions 13a are formed on the surface of the second conductive layer 13. And is processed into a surface having a surface roughness of about 1 to 2 μm.
At this time, since the resin pattern 12p has chemical resistance, it is not damaged.

Next, as shown in FIG. 4A, for example, the second conductive layer forming master substrate from the second conductive layer 13 side is impregnated with an uncured aramid resin, also called a prepreg, in a nonwoven fabric. The first uncured resin sheet 14 of B stage having a film thickness of about 20 to several tens of μm (for example, product name CEL-541 manufactured by Shin-Kobe Electric Machinery Co., Ltd.) is bonded together, and the resin at a temperature of 80 ° C. and a pressure of 2 kg is completely cured. Laminate according to semi-curing conditions. As a material for the uncured resin sheet, an epoxy resin or the like can also be used.
At this time, the uncured resin sheet 14 has high adhesiveness with the second conductive layer 13 and is strongly bonded. However, since the surface of the resin pattern 12p is lubricious, the adhesiveness is low and the structure is easily peeled off.
The uncured resin sheet 14 is previously provided with a heat-resistant transparent sheet 14s that facilitates handling.

Next, as shown in FIG. 4B, the interface between the uncured resin sheet 14 and the first resin pattern 12p, and the interface between the second conductive layer 13 and the conductive film 11 formed on the surface of the conductive substrate. And the second conductive layer 13 is transferred onto the first uncured resin sheet 14.
At this time, the entire surface is irradiated with the laser beam LS so as to assist the peeling of the interface between the uncured resin sheet 14 and the resin pattern 12p through the conductive substrate in which the conductive film 11 is provided on the transparent glass substrate 10. . It can be easily peeled off by the impact of the laser beam. As the laser light LS, for example, an excimer laser is used. The output of the excimer laser is, for example, 23 mJ / cm ² and irradiation is performed for several minutes.
Excimer laser light has an effect of giving a shock wave to the absorbed light and facilitating peeling of the bonded portion. Fluorine-based resin is almost white and excimer laser light is transmitted, but copper is a metal and is susceptible to laser.
As described above, since the fine concave portion 11a is formed in the conductive film 11, this shape is transferred to the surface of the second conductive layer 13, and the fine convex portion 13b is formed.

In the above process, the uncured resin sheet 14 and the second conductive layer 13 are strongly bonded, but the resin pattern 12p is more uncured than the conductive film 11 formed on the surface of the conductive substrate. The second conductive layer 13 can be easily peeled off at the interface between the uncured resin sheet 14 and the resin pattern 12p with the second conductive layer 13 adhered to the uncured resin sheet 14 because of its low adhesiveness to the surface of the resin. There is no problem that the resin pattern 12p is peeled off from the conductive substrate or the second conductive layer 13 remains on the conductive substrate.
Accordingly, it is possible to reuse the master substrate for forming the second conductive layer without forming the resin pattern 12p again. For example, the glass substrate 10 constituting the master substrate is made of heat-resistant glass, and the resin pattern 12p is made of fluorine. By using a material with high chemical resistance and heat resistance such as resin, it can be used repeatedly thousands of times, and the conductive layer with the same pattern can be mass-produced, reducing the manufacturing cost. be able to.
Further, the second conductive layer 13 formed as described above is subjected to an appearance inspection such as whether it is accurately formed by a process (not shown), a thickness and a shape, and an electronic inspection as necessary. Can do. In this case, only non-defective products that are accurately formed can be used in the next step, which contributes to an improvement in yield.

On the other hand, as shown in FIG. 5A, a semiconductor chip 20 provided with an electronic circuit including an active element such as a transistor is formed by a normal semiconductor process which is a process different from the above. This is for incorporation in a SiP-type semiconductor device as shown in FIG. 1, and the semiconductor is not particularly limited, such as Si or GaAs.
In the semiconductor chip 20, a pad 22 made of aluminum or the like is provided on the surface of the semiconductor chip body 21 on which the electronic circuit as described above is formed so as to be connected to the electronic circuit, and the semiconductor chip body 21 in a region excluding the pad 22 is provided. The surface is covered with a protective layer 23 such as silicon oxide.
In order to be incorporated in a SiP type semiconductor device, the thickness of the semiconductor chip 20 is reduced to, for example, about 30 μm. Thinning the semiconductor chip 20 is preferable because it leads to thinning of the entire SiP type semiconductor device. Dicing (single piece) may be performed after thin processing in a wafer state, or thin processing may be performed after dicing. When processing thinly to 30 μm in a wafer state, it is necessary to pay sufficient attention to cracking.

Next, as shown in FIG. 5B, a zincate treatment as described in Patent Document 2 is performed on the pad 22 of the semiconductor chip 20 formed as described above, and aluminum constituting the pad 22 is formed. The oxide on the surface of the layer is removed, and a zinc layer 22a is formed on the surface of the pad 22 to a thickness of about 0.3 μm.
Although a nickel layer cannot be directly formed on the aluminum pad 22, it is easy to form a nickel layer on the surface of the zinc layer 22a formed by this zincate treatment by electroless plating.

Next, as shown in FIG. 5C, a pad protection layer 22b made of nickel is formed on the surface of the pad 22 on the zinc layer 22a with a film thickness of about 5 μm by electroless plating.
As will be described later, the pad protective layer 22b reflects a laser beam used to form an opening that reaches the pad 22 through the resin layer laminated on the upper layer, and serves as a stopper for the opening. In such a case, the yield can be increased and the manufacturing cost can be reduced.
Up to the step of forming the pad protection layer 22b may be performed in a wafer state, and in this case, each step of dicing is performed after thinning or after thinning. Alternatively, the zinc layer 22a and the pad protective layer 22b can be formed after dicing, and the thickness can be reduced thereafter.

Here, in the case of mounting other electronic components such as passive elements instead of the semiconductor chip or in addition to the semiconductor chip, on the outermost surface of the electrode of the electronic component, similar to the pad of the semiconductor chip described above, An electrode protective layer made of a nickel layer or the like is formed in advance.
This electrode protective layer reflects the laser beam used to form an opening that reaches the electrode of the electronic component through the resin layer laminated on the upper layer, so that it serves as a stopper for the opening and connects them. Yield can be increased and manufacturing costs can be reduced.

  On the other hand, as shown in FIG. 6A, an electronic circuit including an active element 31 such as a transistor and a diode is provided on a surface of a silicon semiconductor substrate 30 by a normal semiconductor process, which is a process different from the above, on its surface. An interlayer insulating film 32 made of silicon oxide or the like is formed, and a passive element 33 such as a capacitance element, an electric resistance element, and an inductance is formed thereon, and an electronic circuit including the active element 31 and the passive element 33 are formed. The first conductive layer 34 made of aluminum is patterned so as to be connected. This is the package substrate of the SiP-type semiconductor device according to this embodiment. The drawing is a schematic view and shows that the active element 31 and the passive element 33 are formed to be connected to the first conductive layer 34.

Next, as shown in FIG. 6 (b), in a region including a region for forming an opening that penetrates the resin layer laminated on the upper layer of the first conductive layer 34 and reaches the first conductive layer 34, as described later. A conductive first conductive layer protective layer 35 that reflects light, such as a copper layer, is formed on the surface of the first conductive layer 34 to a thickness of about 5 μm. This can be formed as the above-mentioned pattern by, for example, forming a copper layer on the entire surface and removing it by leaving a necessary region by pattern formation and etching of the resist film.
As will be described later, the first conductive layer protective layer 35 reflects the laser beam used to form an opening that reaches the first conductive layer 34 through the resin layer laminated on the upper layer. When it becomes a stopper and these are connected, a yield can be improved and manufacturing cost can be reduced.

  Next, as shown in FIG. 6C, the semiconductor chip 20 having the configuration shown in FIG. 5C is replaced with the first conductive layer 34, the active element 31 or the passive element of the package substrate having the configuration shown in FIG. 6B. Mount on the upper layer of the element 33 or the like via the die attach film 24.

Next, as shown in FIG. 7A, the heat-resistant transparent sheet 14s is peeled off from the uncured resin sheet 14 obtained in the step shown in FIG. The surface of the cured resin sheet 14 opposite to the surface on which the second conductive layer 13 is transferred is bonded to the surface on which the first conductive layer 34 of the package substrate is formed. If this step is performed in a vacuum, bubbles and the like are difficult to enter, which is preferable. At this time, the uncured resin sheet 14 can be covered so as to wrap around in accordance with the shape of the semiconductor chip 20. For example, the unevenness of the semiconductor chip 20 is absorbed and the surface of the uncured resin sheet 14 becomes substantially flat. It is pasted together.
Further, the uncured resin sheet 14 is completely cured to form a first insulating layer 14 'having a film thickness of 20 to several tens of micrometers, for example. The film thickness of the second conductive layer 13 is about 6 μm.
For example, in order to prevent the uncured resin sheet 14 and the thermocompression bonding jig from being bonded, the complete curing described above is performed by sandwiching the upper surface of the uncured resin sheet 14 with a thermocompression bonding jig through a fluororesin film, and 150 Performed by thermocompression treatment at 2 ° C. for 2 hours.

Next, as shown in FIG. 7B, oxidation treatment with sodium hypochlorite, so-called blackening treatment (treating agent: trade name BO499, manufactured by Ebara Densan) is performed, and the surface of the second conductive layer 13 is formed. A black oxide film 13c is formed.
Next, the first conductive layer is formed on the first conductive layer 34 by irradiating the second conductive layer 13 at a predetermined position using laser light, penetrating the second conductive layer 13 and the first insulating layer 14 ′. A first through opening V ₁ reaching the protective layer 35 is formed, and a second through opening V ₂ reaching the pad protective layer 22 b of the pad 22 of the semiconductor chip 20 is formed.
The opening diameters of the first through opening V ₁ and the second through opening V ₂ are, for example, about 15 to 30 μm. As described above, the minimum processing dimension of the second conductive layer 13 is, for example, 10 μm (the line / space width is 10 μm / 10 μm), but the periphery of the first through opening V ₁ and the second through opening V ₂ . In, for example, it is widely formed to have a diameter of several tens of μm.
The conditions for laser light irradiation are, for example, burst processing using an ultraviolet laser for the second conductive layer 13 including the oxide film 13c, the frequency is 25 kHz, and the number of shots is 143. Further, with respect to the first insulating layer 14 ', a cycle process using a CO ₂ laser, one shot pulse width 5 [mu] m, to 1 shot irradiated further by the pulse width 2 [mu] m.

In the opening process of the first through opening V ₁ and the second through opening V ₂ , since the black oxide film 13 c is formed on the surface of the second conductive layer 13, the ultraviolet laser is not reflected. It is fully absorbed and can be opened efficiently. On the other hand, in the opening region of the first through opening V ₁ and the second through opening V _2, a first conductive layer protective layer 35 is formed on the surface of the first conductive layer 34, and on the outermost surface of the pad 22. Since the pad protective layer 22b is formed and these protective layers do not absorb and absorb light such as laser light, the lower layer than the first conductive layer protective layer 35 or the lower layer than the pad protective layer 22b is not removed, The opening stops at the surfaces of the first conductive layer protective layer 35 and the pad protective layer 22b.

Further, after that, a resin residue in the first and second through openings (V ₁ , V ₂ ) is removed and washed by a process called desmear.

Next, as shown in FIG. 7C, for example, the first and second through openings (V ₁ , V ₂ ) are filled with copper paste by screen printing, and cured by heating or the like to form the conductive layer. The first through wiring 36 and the second through wiring 37 are formed.
The copper paste used here is, for example, trade name M-151 (a mixture of copper particles having a diameter of about 5 μm and Sn / Bi solder) manufactured by Tatsuta Electric Wire Co., Ltd., and a solderable material is used.
Next, the oxide film 13c formed on the surface of the second conductive layer 13 is removed by a soft etching process.

FIG. 8 is a schematic diagram showing a step of performing screen printing for forming through wirings such as the first and second through wirings (36, 37). It can also be used to form other through wirings.
A metal mask MS that is opened in the same pattern as the pattern of the opening V is aligned and fixed to the substrate SB to be printed on which the opening V to be embedded with the copper paste is formed, and fixed. A copper paste PS is supplied to the upper surface of the squeegee SQ, and the air pressure P is applied so as to press the squeegee SQ against the metal mask MS. A copper paste PS is embedded in V.
For example, using a vacuum printer (LZ-9957) manufactured by Neurong Co., Ltd., metal mask thickness: 0.05 mm, squeegee hardness: 85, squeegee speed: 3 mm / second, indentation: +0.5 mm, air pressure: 0. 4 MPa, clearance: 0.5 mm, platen temperature: room temperature, screen-printed in vacuum, and the supplied copper paste is cured by, for example, heat treatment at 200 ° C. for 30 minutes.
As described above, in the method of printing the conductive paste by providing the connection openings between the conductive layers, the pattern of the conductive layer can be made thinner compared to the connection method by plating, and as a result, the entire mounting substrate is made thinner. Can do. In addition, since the plating process is unnecessary, the pattern of the conductive layer can be miniaturized, and no plating solution is required, so that the manufacturing cost can be reduced.

Next, description will be made for the configuration up to the configuration shown in FIG. Basically, the second conductive layer is laminated through the first insulating layer as described above, and the same process as the step of forming the first and second through wirings is performed.
First, the third conductive layer forming master substrate is formed in the same manner as the step of forming the second conductive layer forming master substrate shown in FIGS. 2 (a) to 3 (a). For example, the minimum processing dimension of the second resin pattern for forming the third conductive layer is also 10 μm (the line / space width is 10 μm / 10 μm), similarly to the first resin pattern. Here, the second resin pattern for forming the third conductive layer is formed as a pattern corresponding to the design pattern.

Next, in the same manner as the steps shown in FIGS. 3B to 4B, the third conductive layer is masked by electrolytic plating using the second resin pattern as a mask, using the master substrate for forming the third conductive layer. Is formed and transferred to a second uncured resin sheet having a thickness of about 20 to several tens of μm.
The surface of the second uncured resin sheet to which the third conductive layer 15 obtained as described above is transferred is opposite to the surface to which the third conductive layer 15 is transferred, and the second insulating layer 14 ′ has a second surface. The surface on which the conductive layer 13 is formed is bonded, and the second uncured resin sheet is completely cured by a thermocompression treatment to form a second insulating layer 16 ′ having a thickness of about 20 to several tens of μm.

Next, an oxidation treatment with sodium hypochlorite, a so-called blackening treatment, is performed to form a black oxide film (not shown) on the surface of the third conductive layer 15, and the third conductive at a predetermined position using laser light. The third through-opening V ₃ that irradiates the layer 15 and penetrates the third conductive layer 15 and the second insulating layer 16 ′ to reach the second conductive layer 13, and further, the third conductive layer 15 and the second insulating layer. A fourth through-opening V ₄ that penetrates 16 ′ and the first insulating layer 14 ′ and reaches the first conductive layer 34 is formed.
The opening diameters of the third and fourth through openings (V ₃ , V ₄ ) are, for example, about 15 to 30 μm. As described above, the minimum processing size of the second conductive layer 13 and the third conductive layer 15 is, for example, 10 μm (the line / space width is 10 μm / 10 μm). Are widely formed.

In the opening process of the third through opening V ₃ and the fourth through opening V ₄ , since the black oxide film is formed on the surface of the third conductive layer 15, the light is sufficiently absorbed and the efficiency is increased. Can be opened. Here, the opening of the third through opening V ₃ stops at the surface of the second conductive layer 13 made of copper or the like that reflects light, and the opening of the fourth through opening V ₄ similarly emits light. It stops at the surface of the first conductive layer protective layer 35 made of reflective copper or the like.

Next, after removing and cleaning the resin residue in the third and fourth through openings (V ₃ , V ₄ ), the third and fourth through openings (V, for example, by screen printing shown in FIG. 8). ₃ , V ₄ ) is filled with a copper paste and cured by heating or the like to form a conductive layer, and a third through wiring 38 connecting the second conductive layer 13 and the third conductive layer 15 is formed. In addition, a fourth through wiring 39 that connects the first conductive layer 34 and the third conductive layer 15 is formed.
Next, the oxide film formed on the surface of the third conductive layer 15 is removed by a soft etching process.
Thus, the structure shown in FIG. 9A can be obtained.

Next, as shown in FIG. 9B, on the second insulating layer 16 ′ and the non-selected third conductive layer 15 except the formation region of the third conductive layer 15 selected to be exposed. A solder resist 40 is formed.
Further, bumps (projection electrodes) 41 made of solder balls or the like are formed at necessary portions of the exposed third conductive layer 15, and the SiP semiconductor device shown in FIG. 1 can be manufactured as described above. .

In addition, according to the method of manufacturing a SiP type semiconductor device according to the above-described embodiment, the following advantages are obtained.
(1) Since the conductive patterns such as the second and third conductive layers are formed by the electroforming method, the pattern width and shape can be formed with high accuracy. This makes it possible to realize a module with little variation in transmission loss and the like.
(2) Since patterning of a resist (fluorine-based resin) for forming a conductive pattern such as the second and third conductive layers is performed by a laser drawing method, a fine pattern of about line / space = 10 μm / 10 μm It becomes possible to form a module with a small size and high performance.
(3) Since a fluorine-based resin having high heat resistance and chemical resistance is used as a resist for forming a conductive pattern such as the second and third conductive layers, and heat resistant glass is used for the first substrate, Since the master substrate composed of these can be used repeatedly thousands of times, it can be mass-produced at low cost. In addition, since these tools can be used repeatedly, it is not necessary to create them every time of manufacturing, and the lead time of manufacturing can be shortened accordingly.
(4) When the conductive patterns such as the second and third conductive layers are peeled from the glass substrate, the uncured resin sheet and the conductive pattern have high adhesiveness, whereas the uncured resin sheet and the fluororesin have poor adhesion. In addition, since an excimer laser is used in combination, the yield during peeling is good and the productivity is high.
(5) The conductive pattern of each layer such as the second and third conductive layers and the uncured resin sheet to which they are transferred are inspected before lamination, and only good products can be laminated, so there is little yield loss. Cost can be kept low.
(6) Since the conductive paste is embedded through the through openings as the connection wiring between the first to third conductive layers and between these and the electronic components such as the semiconductor chip, each conductive layer is compared with the connection by plating. This pattern can be made thin, which contributes to the thinning of the semiconductor device. Further, since the plating is unnecessary, the pattern can be miniaturized, and further, the plating solution treatment is unnecessary, so that the cost can be reduced.

The present invention is not limited to the above description.
Although a configuration having an electronic circuit on both the package substrate and the semiconductor chip is described, both are not necessarily required. For example, a configuration having an electronic circuit on the package substrate and no semiconductor chip, or a built-in semiconductor chip An electronic circuit is not formed on the package substrate, and the package substrate can be used as a simple substrate. Particularly in the latter case, a metal substrate, an organic substrate, a ceramic substrate, or the like can be used instead of the silicon semiconductor substrate on which the active element is formed.
In the above embodiment, the semiconductor chip is mounted on the first conductive layer of the package substrate. However, the present invention is not limited to this. For example, the semiconductor chip is mounted on the first insulating layer and the second chip is mounted. It is also possible to cover the semiconductor chip with an uncured resin sheet to be an insulating layer. The same applies when mounting electronic components. Furthermore, a plurality of semiconductor chips and electronic components can be mounted on different insulating layers.
With respect to the number of insulating layers made of resin, the number of conductive layers, or the type of through wiring provided, configurations other than those shown in the embodiment can be employed as appropriate.
The material of the resin pattern used for the master substrate is not limited to the fluorine-based resin, and may be any material that has lower adhesion to the uncured resin sheet than the surface of the first conductive substrate.
In addition, various modifications can be made without departing from the scope of the present invention.

The semiconductor device manufacturing method of the present invention can be applied to a method of manufacturing a SiP-type semiconductor device.
The semiconductor device of the present invention can be applied to a SiP type semiconductor device.
The electronic component of the present invention can be applied to an electronic component embedded in a resin layer constituting a SiP-type semiconductor device.
The semiconductor chip of the present invention can be applied to a semiconductor chip embedded in a resin layer constituting a SiP type semiconductor device.
The package substrate of the present invention can be applied to a package substrate constituting a SiP type semiconductor device.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 3A to 3C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 4A and 4B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 5A to 5C are cross-sectional views showing a manufacturing process (semiconductor chip forming process) of a semiconductor device according to the embodiment of the present invention. 6A to 6C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 7A to 7C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. FIG. 8 is a schematic diagram showing a process of performing screen printing for forming the through wiring. FIG. 9A and FIG. 9B are cross-sectional views showing the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Glass substrate, 11 ... Conductive film, 11a ... Concave part, 12 ... Resin layer, 12p ... 1st resin pattern, 13, 15 ... 2nd conductive layer, 13a ... Concave part, 13b ... Convex part, 13c, 15c ... Oxide film , 14 ... 1st uncured resin sheet, 14s ... Heat-resistant transparent sheet, 14 '... 1st insulating layer, 15 ... 3rd conductive layer, 16' ... 2nd insulating layer, 20 ... Semiconductor chip, 21 ... Semiconductor chip main body, DESCRIPTION OF SYMBOLS 22 ... Pad, 22a ... Zinc layer, 22b ... Pad protection layer, 23 ... Protection layer, 30 ... Silicon semiconductor substrate, 31 ... Active element, 32 ... Interlayer insulation film, 33 ... Passive element, 34 ... 1st conductive layer, 35 ... 1st conductive layer protective layer, 36 ... 1st penetration wiring, 37 ... 2nd penetration wiring, 38 ... 3rd penetration wiring, 39 ... 4th penetration wiring, 40 ... Solder resist, 41 ... Bump (projection electrode), LS ... laser light, V ₁ ... first through opening, ₂ ... second through openings, V ₃ ... third through opening, V ₄ ... fourth through openings, SB ... substrate, MS ... metal mask, SQ ... squeegee, PS ... copper paste, P ... air pressure, M … Predetermined direction

Claims (14)

Patterning the first conductive layer on the package substrate;
At least in the region excluding the second conductive layer forming region on the first conductive substrate whose surface is conductive, the first has lower adhesion to the surface of the uncured resin sheet than the surface of the first conductive substrate. Forming a resin pattern to form a second conductive layer forming master substrate;
Patterning a second conductive layer on the first conductive substrate in the second conductive layer formation region using the first resin pattern as a mask;
Bonding the first uncured resin sheet from the second conductive layer side to the master substrate for forming the second conductive layer;
Peeling at the interface between the first uncured resin sheet and the first resin pattern and at the interface between the second conductive layer and the first conductive substrate, and transferring the second conductive layer onto the first uncured resin sheet And a process of
Bonding the surface of the first uncured resin sheet opposite to the surface on which the second conductive layer is transferred to the surface of the package substrate on which the first conductive layer is formed;
Curing the first uncured resin sheet to form a first insulating layer. After the step of curing the first uncured resin sheet to form the first insulating layer,
Forming a first through opening penetrating the second conductive layer and the first insulating layer to reach the first conductive layer;
The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a first through wiring by forming a conductive layer in the first through opening. After the step of patterning the first conductive layer, before the step of bonding the first uncured resin sheet and the package substrate, the surface of the first conductive layer is formed in the formation region of the first through opening. A step of forming a conductive first conductive layer protective layer;
The method of manufacturing a semiconductor device according to claim 2, wherein in the step of forming the first through opening, the first through opening is formed in a region of the first conductive layer protective layer. In the step of forming the first conductive layer protective layer, the first conductive layer protective layer is formed of a light reflective conductive material,
The method for manufacturing a semiconductor device according to claim 3, wherein in the step of forming the first through opening, the first through opening is formed by irradiating light to an opening region of the first through opening. Using a semiconductor substrate provided with an electronic circuit as the package substrate,
The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first conductive layer, the first conductive layer is formed so as to be connected to the electronic circuit. After the step of patterning the first conductive layer, before the step of bonding the first uncured resin sheet and the package substrate, the method further includes a step of mounting an electronic component on the package substrate,
In the step of bonding the first uncured resin sheet and the package substrate, the first uncured resin sheet is bonded to the package substrate so as to cover the electronic component,
After the step of curing the first uncured resin sheet to form the first insulating layer, a second through opening that reaches the electrode of the electronic component through the second conductive layer and the first insulating layer is formed. The method for manufacturing a semiconductor device according to claim 1, further comprising: a step of forming a second through wiring by forming a conductive layer in the second through opening. Before the step of mounting the electronic component, further comprising a step of forming a conductive electrode protective layer on the outermost surface of the electrode of the electronic component,
The method of manufacturing a semiconductor device according to claim 6, wherein in the step of forming the second through opening, the second through opening is formed in a region of the electrode protection layer. In the step of forming the electrode protective layer, the electrode protective layer is formed of a light-reflective conductive material,
The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the second through opening, the second through opening is formed by irradiating light to an opening region of the second through opening. The method of manufacturing a semiconductor device according to claim 6, wherein the electronic component is a semiconductor chip provided with an electronic circuit, and an electrode of the electronic component is a pad of the semiconductor chip. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first resin pattern, the first resin pattern is formed of a fluororesin. In the step of peeling at the interface between the first uncured resin sheet and the first resin pattern and at the interface between the second conductive layer and the first conductive substrate, the first uncured resin sheet passes through the first conductive substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the laser beam is irradiated so as to assist in peeling from the interface between the first resin pattern and the first resin pattern. At least in the region excluding the third conductive layer forming region on the second conductive substrate whose surface is conductive, the second has lower adhesion to the surface of the uncured resin sheet than the surface of the second conductive substrate. Forming a master pattern for forming a third conductive layer by forming a resin pattern;
Patterning a third conductive layer on the second conductive substrate in the third conductive layer formation region using the second resin pattern as a mask;
Bonding a second uncured resin sheet from the third conductive layer side to the master substrate for forming the third conductive layer;
Peeling at the interface between the second uncured resin sheet and the second resin pattern and at the interface between the third conductive layer and the second conductive substrate, and transferring the third conductive layer onto the second uncured resin sheet And a process of
Bonding the surface of the second uncured resin sheet opposite to the surface to which the third conductive layer is transferred, and the surface of the first insulating layer on which the second conductive layer is formed;
The method for manufacturing a semiconductor device according to claim 1, further comprising: curing the second uncured resin sheet to form a second insulating layer. After the step of curing the second uncured resin sheet to form the second insulating layer, a third through opening that reaches the second conductive layer through the third conductive layer and the second insulating layer is formed. The method of manufacturing a semiconductor device according to claim 12, further comprising: a step of forming a conductive layer in the third through-opening portion to form a third through-wiring. After the step of curing the second uncured resin sheet to form the second insulating layer, the second conductive layer reaches the first conductive layer through the third conductive layer, the second insulating layer, and the first insulating layer. The method for manufacturing a semiconductor device according to claim 12, further comprising a step of forming a four through opening and a step of forming a conductive layer in the fourth through opening to form a fourth through wiring.

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