JP2008211254A - Multi-layer circuit board with built-in components - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-layer circuit board with built-in components which has a structure capable of radiating heat generated by a built-in semiconductor chip to the outside efficiently. <P>SOLUTION: A multi-layer circuit board with built-in components comprises a plurality of wiring layers and an isolating layer which are laminated alternatively on a core substrate and further includes at least the semiconductor chip as a circuit component. In this multi-layer circuit board, the semiconductor chip is arranged so that its circuit surface is oriented upward, that is, oriented in a forward direction with respect to the lamination direction. Furthermore, it has a structure in which the following (1) is combined with at least one of (2) and (3): (1) a structure where the back surface of the semiconductor chip is jointed to a layer immediately under it by a heat transmission layer; (2) a structure where a heat transmission via formed on the circuit surface of the semiconductor chip is thermally connected with a heat slinger exposed on the top surface of the circuit substrate; (3) a structure where the heat transmission via formed on the circuit surface of the semiconductor chip is thermally connected with a heat slinger exposed on the side surface of the circuit substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer circuit board with a built-in component that is formed by alternately laminating a plurality of wiring layers and insulating layers and incorporates a semiconductor chip and other circuit components.

  In recent years, various types of multilayer circuit boards incorporating circuit components such as semiconductor chips have been proposed as electronic devices become lighter, thinner, higher performance, and multifunctional (for example, Patent Documents 1 and 2 and Non-Patent Document 1). See).

  In such a structure with a built-in component, a large amount of heat generated from the semiconductor chip is likely to be accumulated in the substrate, which may shorten the product life.

JP 2000-323645 A (Claims) JP 2001-177045 A (Claims) “Electronics Packaging Technology” January 2003 (vol.19, No.1, p12-19)

  It is an object of the present invention to provide a component built-in multilayer circuit board having a structure capable of efficiently radiating heat generated in a built-in semiconductor chip to the outside.

To achieve the above object, according to the present invention, in a multilayer circuit board with a built-in component comprising a plurality of wiring layers and insulating layers alternately stacked on a core substrate and incorporating at least a semiconductor chip as a circuit component. ,
The semiconductor chip is disposed with its circuit surface facing upward in the same direction as the stacking direction, and the following (1) to (3):
(1) A structure in which the back surface of the semiconductor chip is bonded to the core substrate via a heat transfer layer,
(2) A heat transfer via formed on the circuit surface of the semiconductor chip through the insulating layer provided immediately above the semiconductor chip is thermally connected to a heat sink provided on the upper surface of the circuit board. And (3) heat dissipation via which the heat transfer via formed on the circuit surface of the semiconductor chip through the insulating layer provided immediately above the semiconductor chip is exposed on the side surface of the circuit board. Structure thermally connected to the board,
The structure (1) and any one of the structures (2) and (3) are combined, and the semiconductor chip and the heat transfer layer are provided in the same insulating layer. And
(A) In the structure in which the structures (1) and (2) are combined, an external connection terminal is formed on the surface of the core substrate opposite to the semiconductor chip formation surface, and the external connection terminal and the semiconductor chip are Electrically connected through a through hole provided in the core substrate,
(B) In the structure in which the structures (1) and (3) are combined, the heat transfer via and the heat radiating plate are thermally transferred via a heat transfer line provided on the insulating layer in which the heat transfer via is formed. A multilayer circuit board with a built-in component is provided.

  As the heat transfer layer in the structure (1), any one of a conductive paste containing conductive particles, an adhesive film containing metal columns, and a metal layer can be used. The conductive particles and the metal columns are typically made of any one of Ni, Ag, Cu, and Au, respectively. The metal layer is typically formed by combining a metal plating layer formed on the layer immediately below and a metal sputter layer formed on the back surface of the semiconductor chip.

  Furthermore, a metal plate can be used as the heat radiating plate in the structures (2) and (3).

In addition, as a reference technology that does not claim a claim, in a multilayer circuit board with a built-in component comprising a plurality of wiring layers and insulating layers alternately stacked, and at least a semiconductor chip as a circuit component,
The semiconductor chip is arranged with its circuit surface facing downward in the direction opposite to the stacking direction, and the following (1) to (2):
(1) A structure in which a heat transfer via formed directly on the back surface of a semiconductor chip or via a heat transfer layer is thermally connected to a heat sink provided exposed on the upper surface of the circuit board, and 2) At least a structure in which a heat transfer via formed directly on the back surface of the semiconductor chip or via a heat transfer layer is thermally connected to a heat sink provided exposed on the side surface of the circuit board. Also disclosed herein is a multilayer circuit board with a built-in component, characterized by having a single structure.

  Typically, the heat transfer layer is composed of a metal layer formed on the back surface of the semiconductor chip via a barrier layer. Moreover, a metal plate can be used as the heat radiating plate.

Embodiment 1
FIG. 1 shows an example of a component built-in multilayer circuit board according to an embodiment of the first invention in which a semiconductor chip is embedded with the circuit surface facing upward (face up).

This embodiment is the following among the structures (1) to (3) that are features of the present invention:
(1) The structure in which the back surface of the semiconductor chip is joined to the layer immediately below by the heat transfer layer, and (2) the heat transfer via formed on the circuit surface of the semiconductor chip is exposed on the upper surface of the circuit board. Structure that is thermally connected to the heat sink
It is the form provided with two of these.

  The component-embedded multilayer circuit board 10 includes an upper surface wiring layers 102 and 104, a lower surface wiring layer 106, and insulating films 108, 110 between the wiring layers 102/104 on a core substrate 100 made of a glass cloth substrate. Upper and lower surface insulating films 112 and 114 are provided, and a semiconductor chip 116 is embedded in the interlayer insulating film 108 with the circuit surface 116A facing upward (stacking direction). The back surface 116 </ b> B (the lower surface in the drawing) of the semiconductor chip 116 is joined to the wiring layer 102 directly below by the heat transfer layer 118. A heat transfer via 120 extending upward from the circuit surface 116 </ b> A of the semiconductor chip 116 through the interlayer insulating film 110 is joined to the heat transfer layer 104 </ b> A on the same layer as the wiring layer 104 on the interlayer insulating film 110. The heat transfer layer 104A is thermally connected to a heat radiating plate 128 bonded thereto with a conductive paste 126 via a connection pad 123 formed of two metal plating layers 122 and 124 on the upper surface. The conductive paste layer 126 also functions as an adhesive layer.

  The connection via 130 penetrating only the interlayer insulating film 110 electrically connects an electrode pad (not shown) on the circuit surface 116A of the semiconductor chip 116 and the wiring layer 104, and penetrates the interlayer insulating films 108 and 110. The connecting via 132 electrically connects the wiring layer 104 on the upper floor and the wiring layer 102 on the lower floor. Through the through holes 134 penetrating the core substrate 100, the wiring layers 104 and 106 on the upper and lower surfaces of the substrate are electrically connected. The through hole 134 has a cylindrical shape made of a conductive layer that covers the inner wall of the raw hole penetrating the core substrate, and the inside of the cylindrical through hole 134 is filled with a resin 137. An external connection terminal 136 is formed on the wiring layer 106 on the lower surface side of the substrate via two metal plating layers 135A and 135B. The entire lower surface of the substrate except the portion is covered with the surface insulating film 114.

  1, the back surface 116B side of the semiconductor chip 116 is radiated to the core substrate 100 via the heat transfer layer 118, and the circuit surface 116A side is transferred to the heat transfer layer 104A / via the heat transfer via 120. Heat is dissipated through the heat transfer path of the connection pad 123 / conductive paste 126 / heat sink 128. Thereby, the internal accumulation of heat generated in the semiconductor chip 116 is significantly reduced, and the product life is remarkably improved.

  An example of a procedure for manufacturing the component built-in multilayer circuit board 10 of FIG. 1 will be described.

  First, a procedure for manufacturing the built-in semiconductor chip 116 will be described.

  As shown in FIG. 2, a semiconductor wafer (silicon wafer) 116 'on which a large number of semiconductor elements are formed is prepared. In the drawing, an upper surface 116'A is a semiconductor element formation surface, and 116'B is a wafer back surface.

  As shown in FIG. 3, the surface protection tape 140 is attached to the upper surface 116'A. This is done by roll pressing at room temperature with a laminator.

  As shown in FIG. 4, the wafer thickness is reduced to 20 to 100 μm by grinding the back surface 116 ′ B. This is performed using a back grinder at a rotational speed of 4000 rpm and a grinding speed of 1 μm / sec, and the back surface 116 ′ B is finished to a roughness (Ra) of 0.01 μm.

As shown in FIG. 5, a heat transfer layer 118A made of a metal such as Au is formed on the back surface 116′B by sputtering. This is performed at a power of 500 W and a substrate temperature of 70 ° C. under a reduced pressure of 10 ⁻⁴ Pa. The thickness of the Au heat transfer layer 118A is about 0.1 to 0.3 μm.

  As shown in FIG. 6, a dicing tape 142 is affixed from above the Au heat transfer layer 118. This is done by roll pressing at room temperature with a laminator.

  As shown in FIG. 7, the surface protection tape 140 is peeled off. This is done in a peel manner with a tape remover. As a result, the upper surface (element formation surface) 116'A of the wafer 116 'is exposed again.

  As shown in FIG. 8, the wafer 116 'is diced along a dicing line D and divided into individual semiconductor chips. This is performed using a dicer at a dicing blade rotation speed of 40000 rpm and a cutting speed of 50 mm / sec.

  As shown in FIG. 9, individual semiconductor chips 116 are obtained by the dicing described above. Each semiconductor chip 116 includes a heat transfer layer 118A of Au on the back surface 116B.

  Next, an example of a procedure for manufacturing the component built-in multilayer circuit board 10 in which the semiconductor chip 116 is embedded will be described.

  As shown in FIG. 10, a core substrate 100 made of a glass cloth substrate (thickness 500 μm) or the like is prepared.

  As shown in FIG. 11, through-hole holes 134 ′ having a diameter of 150 to 300 μm are opened at predetermined locations on the core substrate 100 by a drill.

  As shown in FIG. 12, a Cu plating layer 103 is formed on the upper and lower surfaces of the core substrate 100 and the inner wall of the through hole through electroless plating and electrolytic plating.

  As shown in FIG. 13, the inside of the through hole hole 134 ′ is filled with an epoxy resin 137. The Cu plating layer 103 constitutes the upper and lower wiring layers 102 and 106 and the through hole 134 shown in FIG.

  As shown in FIG. 14, an epoxy-based photosensitive resist layer 108 'is formed on the entire top surface. This is performed by attaching a photosensitive epoxy resin film using a vacuum laminator at a substrate temperature of 100 to 150 ° C. and a pressure of 1 MPa. The thickness of the resist layer 108 ′ is equal to the thickness of the built-in semiconductor chip 116.

  As shown in FIG. 15, a built-in semiconductor chip accommodation opening 144 is opened in the resist layer 108 ′ by normal exposure / development processing. Thereafter, the resist layer 108 ′ is completely cured by heat treatment at 150 to 170 ° C. for 2 hours to form the interlayer insulating film 108 (FIG. 1).

  As shown in FIG. 16, an Au heat transfer layer 118B is formed on the wiring layer 102 exposed in the chip housing port 144 by electroless plating. This is performed by using a cyan Au plating solution and treating at a solution temperature of 80 ° C. for 40 minutes. The Au heat transfer layer 118B has a thickness of 0.3 μm.

  As shown in FIG. 17, the semiconductor chip 116 manufactured as described above is inserted into the chip accommodation port 144. At that time, the circuit surface 116A of the semiconductor chip 116 is faced up (face up), and the Au heat transfer surface 118A formed on the back surface 116B is faced down.

  As shown in FIG. 18, the Au heat transfer layer 118B on the core substrate 100 side and the Au heat transfer layer 118A on the semiconductor chip 116 side are joined by die bonding using ultrasonic waves. This is performed at an ultrasonic amplitude of 3 μm, a frequency of 50 Hz, a load of 10 N, a time of 10 seconds, and a temperature of 100 ° C. As a result, the two Au heat transfer layers 118A and 118B are combined to form an integrated Au heat transfer layer 118, and a heat dissipation path from the back surface 116B of the semiconductor chip 116 to the core substrate 100 side is secured.

  As shown in FIG. 19, an interlayer insulating film 110 covering the upper surface is formed. This is done by attaching a thermosetting epoxy resin film (non-photosensitive, thickness 30-50 μm) with a vacuum laminator at a temperature of 100-150 ° C. and a pressure of 1 MPa, and then in an oven at 170 ° C. for 2 hours. This is done by curing.

  As shown in FIG. 20A, the heat transfer via hole 120 ′ and the connection via hole 130 ′ reaching the circuit surface 116A of the semiconductor chip 116 through the interlayer insulating film 110 and the interlayer insulating films 110 and 108 are penetrated. Then, a connection via hole 132 ′ reaching the upper surface side wiring layer 102 is opened. This is simultaneously opened by laser processing using a YAG laser (wavelength 355 nm). The via hole has a top diameter of 60 μm and a bottom diameter of 50 μm. 20 (2), the heat transfer via hole 120 'is formed at the center portion of the circuit surface 116A, and the connection via hole 130' is formed at the peripheral portion of the circuit surface 116A.

  As shown in FIG. 21, an electroless Cu plating layer 146 is formed on the entire top surface. That is, after performing a pretreatment of immersing in a palladium colloid solution having a catalytic action, a plating treatment is performed in a copper sulfate plating solution at 45 ° C. for 30 minutes.

  As shown in FIG. 22 (1), a resist pattern 148 is formed on the electroless Cu plating layer 146. This is performed by applying a dry film resist having a thickness of 20 μm, followed by exposure and development. As shown in FIG. 22 (2), when viewed from above, the resist pattern 148 has a peripheral portion corresponding to a region including the connection via holes 130 ′ and 132 ′. Is a peripheral portion pattern 148P composed of a plurality of openings that are spaced apart from each other, and the central portion is a central portion pattern 148C as a single opening that exposes all of the plurality of heat transfer via holes 120 ′.

  As shown in FIG. 23 (1), each opening of the resist pattern 148 is filled with Cu by electrolytic Cu plating using the electroless Cu plating layer 146 as a power feeding layer, and the heat transfer via 120 and the connection vias 130 and 132 are filled. Then, the wiring layer 104 and the heat transfer layer 104A are formed. The wiring layer 104 and the heat transfer layer 104A are both 15 μm thick and formed on the same layered floor. As shown in FIG. 23 (2), when viewed from above, the wiring layer 104 is formed in the region defined by the resist peripheral portion pattern 148P shown in FIG. 22 (2). The connection via 132 and the inner connection via 130 are electrically connected. In the figure, 104 (132) and 104 (130) are connection pads between the wiring 104, the connection via 132, and the connection via 130. In FIG. 23 (2), the heat transfer layer 104A formed in the center is integrally formed in the opening of the resist center pattern 148C shown in FIG. All of 120 are joined together.

  As shown in FIG. 24, after removing and removing the resist layer 148, the electroless Cu plating layer 146 exposed thereunder is removed. Thereby, the wiring layer 104 and the heat transfer layer 104A are separated from each other and completed.

  As shown in FIG. 25, a solder resist layer 112 that covers the entire top surface excluding the heat transfer layer 104A is formed. This is done by applying a thermosetting epoxy resin film (non-photosensitive, 30-50 μm thick) with a vacuum laminator at a temperature of 100-150 ° C. and a pressure of 1 MPa, and curing in an oven at 170 ° C. for 2 hours. After that, only the portion of the heat transfer layer 104A is opened by laser processing using a YAG laser (wavelength 355 nm). Further, by the same method, the solder resist layer 114 is formed on the entire surface except the pad formation scheduled portion 136 ′ for the external connection terminals on the lower surface.

  As shown in FIG. 26, connection pads 123 and 135 are formed on the heat transfer layer 104A exposed in the opening on the upper surface and the pad formation planned portion 136 'on the lower surface, respectively. This is performed by sequentially forming Ni plating layers 122 and 135A and Au plating layers 124 and 135B at the respective locations by electroless plating. That is, the connection pad 123 on the heat transfer layer 104A has a two-layer structure including the base Ni plating layer 122 and the Au plating layer 124. Similarly, the connection pad 135 for the external connection terminal on the lower surface is the base Ni plating layer 135A. And an Au plating layer 135B.

  As shown in FIG. 27, an Ag paste layer 126 is formed as a conductive paste on the entire top surface.

  As shown in FIG. 28, an Al plate 128 having a thickness of 0.3 to 0.7 mm is bonded to the entire surface of the Ag paste layer 126 as a heat sink. This is performed by placing the Al plate 128 on the Ag paste layer 126 and curing the Ag paste layer 126 by heat treatment at 150 to 170 ° C. for 2 hours. As a result, the circuit surface 116A of the semiconductor chip 116 is thermally connected to the outermost Al heat sink 128 via the heat transfer via 120, the heat transfer layer 104A, the connection pad 123, and the Ag paste layer 126. A heat dissipation path from the top to the top of the substrate is secured.

  Finally, as shown in FIG. 1, when the external connection terminals 136 made of solder balls are joined to the connection pads 135 on the lower surface, the component built-in multilayer circuit board 10 is completed.

[Embodiment 2]
FIG. 29 shows an example of a component built-in multilayer circuit board according to another embodiment of the present invention embedded with the circuit surface of a semiconductor chip facing upward (face up).

This embodiment is the following among the structures (1) to (3) that are features of the present invention:
(1) A structure in which the back surface of the semiconductor chip is bonded to a layer immediately below by a heat transfer layer, and (3) a heat transfer via formed on the circuit surface of the semiconductor chip is exposed on the side surface of the circuit board. Structure that is thermally connected to the heat sink
It is the form provided with two of these.

  In this manner, the heat sink on the side surface of the circuit board can be provided with a heat sink on the upper surface of the circuit board as in the case where a component such as a semiconductor chip is mounted on the upper surface of the circuit board by flip chip. Especially useful in difficult cases. However, it is not necessary to limit only to that case, and the form which provides a heat sink on both the upper surface and the side surface is within the scope of the present invention.

  As shown in FIG. 29 (1), the multilayer circuit board 20 with a built-in component is provided on the core substrate 100 made of a glass cloth substrate, the wiring layers 102 and 104 on the upper surface side, the wiring layer 106 on the lower surface side, and the wiring layers 102 and 104. Insulating films 108 and 110, and upper and lower surface insulating films 112 and 114, and a semiconductor chip 116 is embedded in the interlayer insulating film 108 with the circuit surface 116A facing upward (stacking direction) (face-up). .

  The back surface 116 </ b> B (the lower surface in the drawing) of the semiconductor chip 116 is joined to the wiring layer 102 directly below by the heat transfer layer 118. A heat transfer via 120 extending upward from the circuit surface 116 </ b> A of the semiconductor chip 116 through the interlayer insulating film 110 is bonded to the heat transfer layer 104 </ b> B on the same layer as the wiring layer 104 on the interlayer insulating film 110.

  As shown in FIG. 29 (2), the conductive paste layer 150 on the side surface of the circuit board 20 is positioned such that the heat transfer line 104BL extending in four directions from the heat transfer layer 104B does not intersect the wiring layer 104 in a plane. The conductive paste layer 150 is thermally connected to the heat sink 152 bonded to the side surface of the substrate. The conductive paste layer 150 also functions as an adhesive layer. Note that FIG. 29 (2) shows the uppermost layer (surface insulating film 112 and connection pads 154 for external connection terminals (shown below) shown in FIG. 29 (1) in order to clearly show the relative positional relationship of each part. Explanation))) is peeled off.

  Here, as shown in FIG. 29 (1), the upper and lower wiring layers 102 and 106 directly formed on both surfaces of the core substrate 100 are provided with end portions (both left and right in the figure) close to the side surface of the substrate. It is shorter than that in the case of Form 1 (FIG. 1) and is spaced from the conductive paste layer 150 so as not to be short-circuited by contact with the conductive paste layer 150.

  The connection via 130 penetrating only the interlayer insulating film 110 electrically connects an electrode pad (not shown) on the circuit surface 116A of the semiconductor chip 116 and the wiring layer 104, and penetrates the interlayer insulating films 108 and 110. The connecting via 132 electrically connects the wiring layer 104 on the upper floor and the wiring layer 102 on the lower floor. Through the through holes 134 penetrating the core substrate 100, the wiring layers 104 and 106 on the upper and lower surfaces of the substrate are electrically connected.

  On the upper wiring layer 104 on the upper surface side of the substrate, external connection terminal connection pads 154 including two metal plating layers 154A and 154B are formed on the upper surface of the portion corresponding to the connection via 132.

  A connection pad 135 for an external connection terminal composed of two metal plating layers 135A and 135B is formed at a predetermined position of the wiring layer 106 on the lower surface side of the substrate. As in the case of the first embodiment shown in FIG. 1, the external connection terminal 136 can be formed on the connection pad 135. The lower surface of the substrate is entirely covered with the surface insulating film 114 except for the connection pads 35.

  29, the back surface 116B side of the semiconductor chip 116 is radiated to the core substrate 100 via the heat transfer layer 118, and the circuit surface 116A side is transferred via the heat transfer via 120 to the heat transfer layer 104B /. Heat is dissipated through the heat transfer path of the heat transfer line 104BL / conductive paste 150 / heat sink 152. Thereby, the internal accumulation of heat generated in the semiconductor chip 116 is significantly reduced, and the product life is remarkably improved.

  Next, an example of a procedure for manufacturing the component built-in multilayer circuit board 20 will be described.

  Since the manufacturing process according to the present embodiment has much in common with the manufacturing process according to the first embodiment, only the differences are illustrated.

  The steps shown in FIGS. 10 to 21 described in the first embodiment are performed. However, the wiring layers 102 and 106 provided on both the upper and lower surfaces of the core substrate 100 are formed by shortening the end portions closer to the core substrate side surface in order to avoid contact with the conductive paste layer 150 on the side surface of the core substrate as described above.

  Therefore, in the step of forming the Cu plating layer 103 described with reference to FIGS. 12 to 13 in Embodiment 1, in this embodiment, a dry film resist layer 156 is provided on the side edge of the core substrate 100 as shown in FIG. When the plating of the lever portion is prevented and the plating is completed, the resist layer 156 is removed with an alkaline resist stripping solution as shown in FIG. Thereafter, as in the first embodiment, the inside of the through hole 134 ′ is filled with an epoxy resin 137. Through the above processing, the upper and lower wiring layers 102 and 106 each composed of the plating layer 103 and the through hole 134 are obtained, and the wiring layers 102 and 106 have a form in which the end portion X near the side surface of the core substrate is lost. Occurrence of a short circuit due to contact with the conductive paste layer 150 is avoided.

  Thereafter, the same process as that shown in FIGS. 14 to 21 of the first embodiment is performed.

  Next, in each of the subsequent steps, a structure partially different from that of the first embodiment is obtained depending on the processing content corresponding to the first embodiment.

  As shown in FIG. 32, a resist pattern 148 is formed on the electroless Cu plating layer 146 by the same process as described in the process of FIG. This is performed by applying a dry film resist having a thickness of 20 μm, followed by exposure and development. As shown in FIG. 32 (2), when viewed from above, the resist pattern 148 has a peripheral portion corresponding to a region including the connection via holes 130 ′ and 132 ′. The peripheral portion pattern 148P is formed of a plurality of openings that are spaced apart from each other, and the central portion is an opening that exposes a connecting portion that connects the opening 148CV that exposes each heat transfer via hole 120 ′ and the heat transfer via hole 120. 148CL is a central portion pattern 148C. A pattern 148BL extending in the four directions from the central pattern 148C and reaching the outer edge is a pattern that defines the heat transfer line 104BL shown in FIG.

  As shown in FIG. 33 (1), each opening of the resist pattern 148 is filled with Cu by electrolytic Cu plating using the electroless Cu plating layer 146 as a power feeding layer, and the heat transfer via 120 and the connection vias 130 and 132 are filled. Then, the wiring layer 104 and the heat transfer layer 104B are formed. The wiring layer 104 and the heat transfer layer 104B are both 15 μm thick and are formed on the same layered floor. As shown in FIG. 33 (2), when viewed from above, the wiring layer 104 is formed in a region defined by the resist peripheral portion pattern 148P shown in FIG. 32 (2). The connection via 132 and the inner connection via 130 are electrically connected. In the figure, 104 (132) and 104 (130) are connection pads between the wiring 104, the connection via 132, and the connection via 130. In FIG. 33 (2), the heat transfer layer 104B formed in the center is formed between the heat transfer layer 104B and the heat transfer via 120 in the opening 148CV constituting the resist center pattern 148C shown in FIG. Connection pads are formed, and the connection pads are connected by the heat transfer layer 104B itself. Eventually, the heat transfer layer 104B is connected to all of the heat transfer vias 120 thereunder as a whole.

  Furthermore, as a characteristic structure of the present embodiment, a heat transfer line 104BL extends from the heat transfer layer 104B in the central portion in all directions, and the tip thereof reaches the side surface of the substrate. Thereby, the heat transfer path to the heat sink 152 (FIG. 29) finally provided on the side surface of the substrate is secured.

  As shown in FIG. 34, after removing and removing the resist layer 148, the electroless Cu plating layer 146 exposed thereunder is removed. Thereby, the wiring layer 104 and the heat transfer layer 104B (including the heat transfer line 104BL) are separated from each other and completed.

  As shown in FIG. 35, a solder resist layer 112 is formed to cover the entire upper surface excluding the connection pad formation scheduled portion 154 'for the external connection terminals. This is done by applying a thermosetting epoxy resin film (non-photosensitive, 30-50 μm thick) with a vacuum laminator at a temperature of 100-150 ° C. and a pressure of 1 MPa, and curing in an oven at 170 ° C. for 2 hours. After that, only a portion of the connection pad formation scheduled portion 154 ′ is opened by laser processing using a YAG laser (wavelength 355 nm). Further, by the same method, the solder resist layer 114 is formed on the entire surface excluding the connection pad formation scheduled portion 136 ′ for the external connection terminals on the lower surface.

  As shown in FIG. 36, connection pads 154 and 135 are formed on the upper and lower connection pad formation scheduled portions 154 'and 136', respectively. This is performed by sequentially forming Ni plating layers 154A, 135A and Au plating layers 154B, 135B at the respective locations by electroless plating. That is, the connection pad 154 on the upper surface has a two-layer structure composed of the base Ni plating layer 154A and the Au plating layer 154B. Similarly, the connection pad 135 for the external connection terminal on the lower surface has the base Ni plating layer 135A and the Au plating layer 135B. A two-layer structure consisting of

  As shown in FIG. 37, an Ag paste layer 150 is formed as a conductive paste on the entire side surface. Thereby, the tip of the heat transfer line 104BL extending in four directions from the heat transfer layer 104B in the center of the substrate is connected to the Ag paste layer 150.

  Finally, as shown in FIG. 29, an Al plate 152 having a thickness of 0.3 to 0.7 mm is joined to the entire outer periphery of the Ag paste layer 150 as a heat sink. This is performed by holding the Al plate 152 on the outer periphery of the Ag paste layer 150 and curing the Ag paste layer 150 by heat treatment at 150 to 170 ° C. for 2 hours. As a result, the circuit surface 116A of the semiconductor chip 116 is thermally connected to the outermost Al heat sink 152 via the heat transfer via 120, the heat transfer layer 104B, the heat transfer line 104BL, and the Ag paste layer 150. A heat dissipation path from 116 to the side of the substrate is secured.

  As shown in FIG. 1 of the first embodiment, external connection terminals 136 made of solder balls can be bonded to the connection pads 135 on the lower surface.

[Reference form]
FIG. 38 shows an example of a multilayer circuit board with built-in components according to a reference technique embedded with the circuit surface of a semiconductor chip facing downward.

This form is the following among the structures (1) to (2) of the reference technology:
(1) A structure in which a heat transfer via formed directly or through a heat transfer layer on the back surface of a semiconductor chip is thermally connected to a heat sink provided exposed on the upper surface of the circuit board is provided. It is a form.

  The component-embedded multilayer circuit board 30 is formed on a core substrate 100 made of a glass cloth substrate, upper wiring layers 102 and 104, a lower wiring layer 106, and insulating films 108, 110 between the wiring layers 102/104, The upper surface insulating film 112 is provided, and the semiconductor chip 117 is embedded in the opening 108A of the interlayer insulating film 108 with the circuit surface 117A facing downward (opposite to the stacking direction). The Au electrode bump 117E provided on the circuit surface 117A of the semiconductor chip 117 and the Au plating layer 102F formed on the wiring layer 102 on the upper surface side of the core substrate 100 are flip-chip bonded. The gap in the opening 108A is filled with an underfill 109. From the chip heat transfer layer 118 formed on the back surface 117B (upper surface in the drawing) of the semiconductor chip 117, the heat transfer via 120 extends upward through the interlayer insulating film 110, and the wiring layer 104 on the interlayer insulating film 110 and It is joined to the heat transfer layer 104A on the same laminated floor. The heat transfer layer 104A is thermally connected to a heat sink 128 joined by a conductive adhesive layer 126 made of a conductive film or a conductive paste.

  The connection via 132 penetrating through the interlayer insulating films 108 and 110 electrically connects the upper wiring layer 104 and the lower wiring layer 102. Through the through holes 134 that penetrate the core substrate 100, the wiring layers 102 and 106 on the upper and lower surfaces of the substrate are electrically connected. The through hole 134 has a cylindrical shape made of a conductive layer that covers the inner wall of the raw hole penetrating the core substrate, and the inside of the cylindrical through hole 134 is filled with a resin 137. As in the case of the first embodiment shown in FIG. 1, the external connection terminal 136 is formed on the wiring layer 106 on the lower surface side of the substrate via the two metal plating layers 135A and 135B, and the portion on the lower surface of the substrate is formed. The entire surface may be covered with the surface insulating film 114.

  38 includes a heat transfer layer 104A / conductive paste (or conductive film) 126 / heat radiating plate 128 from the chip heat transfer layer 118 on the back surface 117B of the semiconductor chip 117 through the heat transfer via 120. Heat is dissipated through the heat transfer path. Thereby, the internal accumulation of heat generated in the semiconductor chip 117 is greatly reduced, and the product life is remarkably improved.

  An example of a procedure for manufacturing the component built-in multilayer circuit board 30 of FIG. 38 will be described.

  First, a procedure for manufacturing the built-in semiconductor chip 117 will be described.

  As shown in FIG. 39, a semiconductor wafer (silicon wafer) 117 'on which a large number of semiconductor elements are formed is prepared. In the drawing, an upper surface 117'A is a semiconductor element formation surface, and 117'B is a wafer back surface. An Au electrode bump 117E of each semiconductor element is provided on the upper surface 117'A.

  As shown in FIG. 40, the surface protection tape 140 is attached to the upper surface 117'A. This is done by roll pressing at room temperature with a laminator.

  As shown in FIG. 41, the wafer thickness is reduced to 20 to 100 μm by grinding the back surface 117 ′ B. This is performed using a back grinder at a rotational speed of 4000 rpm and a grinding speed of 1 μm / sec, and the back surface 117 ′ B is finished to a roughness (Ra) of 0.01 μm.

As shown in FIG. 42, a heat transfer layer 118 composed of a TaN layer 118B and a Cu layer 118A is formed on the back surface 117′B by sputtering. This is performed under a reduced pressure of 10 ⁻⁴ Pa at an output of 500 W and a substrate temperature of 70 ° C. First, a 0.05 μm thick TaN layer 118B is formed on the back surface 117′B, and a 0.5 μm thick layer is formed thereon. A Cu layer 118A is formed. The main body of the heat transfer layer 118 is a Cu layer 118A, and the TaN layer 118B is a barrier layer for preventing Cu from diffusing to the silicon wafer 117 ′ side.

  As shown in FIG. 43, the dicing tape 142 is affixed on the Cu / TaN heat transfer layer 118. This is done by roll pressing at room temperature with a laminator.

  As shown in FIG. 44, the surface protection tape 140 is peeled off. This is done in a peel manner with a tape remover. As a result, the upper surface (element formation surface) 117'A and the electrode bumps 117E of the wafer 117 'are exposed again.

  As shown in FIG. 45, the wafer 117 'is diced along a dicing line D and divided into individual semiconductor chips. This is performed using a dicer at a dicing blade rotation speed of 40000 rpm and a cutting speed of 50 mm / sec.

  As shown in FIG. 46, individual semiconductor chips 117 are obtained by the dicing described above. Each semiconductor chip 117 includes a heat transfer layer 118 including a TaN layer 118B and a Cu layer 118A on the back surface 117B.

  Next, an example of a procedure for manufacturing the component built-in multilayer circuit board 30 in which the semiconductor chip 117 is embedded will be described.

  First, as shown in FIG. 10 referred to in the description of the first embodiment, a core substrate 100 made of a glass cloth substrate (thickness: 500 μm) or the like is prepared, and as shown in FIG. A through-hole element 134 ′ having a diameter of 150 to 300 μm is opened by a drill.

  Next, in the present embodiment, as shown in FIG. 47, resist patterns 160 and 162 are respectively formed on a portion of the upper surface of the core substrate 100 where the semiconductor chip 117 is mounted and a lower surface portion corresponding thereto. This is performed by applying a dry film resist having a thickness of 40 μm, followed by exposure and development.

  As shown in FIG. 48, a Cu plating layer 103 is formed on the upper and lower surfaces of the core substrate 100 other than the resist pattern and on the inner wall of the through-hole element 134 by electroless plating and electrolytic plating. That is, an electroless Cu plating layer is first formed to a thickness of 0.1 to 0.3 μm, and then an electrolytic Cu plating layer is formed to a thickness of 15 to 25 μm using this as a power feeding layer.

  As shown in FIG. 49, after the resist patterns 160 and 162 are stripped with an alkaline stripping solution, the electroless Cu plating layer exposed from the bottom is removed with a dilute solution of sulfuric acid + hydrogen peroxide solution.

  As shown in FIG. 50, the inside of the through hole element hole 134 ′ is filled with an epoxy resin 137. The Cu plating layer 103 constitutes a wiring layer 102 on the upper surface of the core substrate 100, a wiring layer 106 on the lower surface, and a through hole 134.

  As shown in FIG. 51, an epoxy photosensitive resist layer 108 'is formed on the entire top surface. This is performed by attaching a photosensitive epoxy resin film using a vacuum laminator at a substrate temperature of 100 to 150 ° C. and a pressure of 1 MPa. The thickness of the resist layer 108 'is equal to the thickness of the built-in semiconductor chip 117 (FIG. 46).

  As shown in FIG. 52, a built-in semiconductor chip accommodation opening 108A is opened in the resist layer 108 'by normal exposure / development processing. Thereafter, the resist layer 108 ′ is completely cured by heat treatment at 150 to 170 ° C. for 2 hours to form the interlayer insulating film 108 (FIG. 38).

  As shown in FIG. 53, an electroless Au plating layer 102F is formed on the wiring layer 102 exposed in the chip accommodation opening 108A. This is performed by using a cyan Au plating solution and treating at a solution temperature of 80 ° C. for 40 minutes. The Au plating layer 102F has a thickness of 0.3 to 0.5 μm.

  As shown in FIG. 54, the semiconductor chip 117 manufactured as described above is inserted into the chip accommodating port 108A with the circuit surface 117A facing down (face down) (the chip heat transfer layer 118 facing up), The electrode bump 117E of the semiconductor chip 117 and the Au plating layer 102F of the wiring layer 102 are bonded by sonic flip chip bonding. This is performed at an ultrasonic amplitude of 3 μm, a frequency of 50 Hz, a load of 10 N, a time of 10 seconds, and a temperature of 100 ° C. As a result, the semiconductor chip 117 is mounted while being electrically connected to the wiring layer 102.

  As shown in FIG. 55, the side gap and the lower gap of the semiconductor chip 117 are filled with an epoxy resin-based underfill. This is performed by tracing the four sides of the semiconductor chip 117 with a dispenser.

  As shown in FIG. 56, an interlayer insulating film 110 covering the upper surface is formed. This is done by attaching a thermosetting epoxy resin film (non-photosensitive, thickness 30-50 μm) with a vacuum laminator at a temperature of 100-150 ° C. and a pressure of 1 MPa, and then in an oven at 170 ° C. for 2 hours. This is done by curing.

  As shown in FIG. 57, the heat transfer via hole 120 ′ that reaches the heat transfer layer 118 (Cu layer 118A) on the back surface 117B of the semiconductor chip 117 through the interlayer insulating film 110, and the interlayer insulating films 110 and 108 pass through. Then, a connection via hole 132 ′ reaching the upper surface side wiring layer 102 is opened. This is simultaneously opened by laser processing using a YAG laser (wavelength 355 nm). The via hole has a top diameter of 60 μm and a bottom diameter of 50 μm.

  As shown in FIG. 58, an electroless Cu plating layer 146 is formed on the entire top surface. That is, after performing a pretreatment of immersing in a palladium colloid solution having a catalytic action, a plating treatment is performed in a copper sulfate plating solution at 45 ° C. for 30 minutes.

  As shown in FIG. 59, after forming a resist pattern 148 of a dry film resist on the electroless Cu plating layer 146 (see FIG. 22 in Embodiment 1), the electroless Cu plating is performed using the electroless Cu plating layer 146 as a power feeding layer. Layer 104 is formed. The electrolytic Cu plating layer 104 forms a heat transfer via 120, a connection via 132, a heat transfer layer 104 </ b> A, and a wiring layer 104.

  As shown in FIG. 60, after removing and removing the resist layer 148, the electroless Cu plating layer 146 exposed thereunder is removed. Thereby, the wiring layer 104 and the heat transfer layer 104A are separated from each other and completed. The upper wiring layer 104 is electrically connected to the lower wiring layer 102 by the connection via 132, and the heat transfer layer 104 A is thermally connected to the chip heat transfer layer 118 on the back surface of the semiconductor chip 117 by the heat transfer via 120.

  As shown in FIG. 61, a resist layer 112 covering the entire top surface excluding the heat transfer layer 104A is formed. This is performed by applying, exposing, developing, and curing a photosensitive epoxy resin. As a result, the upper surface of the heat transfer layer 118A is exposed in the opening of the resist layer 112 covering the upper surface.

  As shown in FIG. 62, a conductive adhesive layer 126 is formed on the upper surface. This is performed by supplying an epoxy resin film or a conductive paste containing conductive particles such as Ag or Ni to the upper heat dissipating plate arrangement region.

  Finally, as shown in FIG. 38, an Al plate 128 having a pressure of 0.3 to 0.7 mm is bonded on the conductive adhesive layer 126 as a heat sink. This is performed by placing the Al plate 128 on the Ag paste layer 126 and curing the Ag paste layer 126 by heat treatment at 150 to 170 ° C. for 2 hours. Thereby, the back surface 117B of the semiconductor chip 117 is thermally connected to the outermost Al heat sink 128 via the chip heat transfer layer 118, the heat transfer via 120, the heat transfer layer 104A, and the conductive adhesive layer 126. A heat dissipation path from the chip 116 to the upper side of the substrate is secured.

  According to the present invention, there is provided a component built-in multilayer circuit board having a structure capable of efficiently dissipating heat generated in a built-in semiconductor chip to the outside. Thereby, the internal accumulation of heat generated in the semiconductor chip is greatly reduced, and the life of the device is remarkably improved.

FIG. 1 is a cross-sectional view showing a component built-in multilayer circuit board according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing a first step in the manufacturing process of the semiconductor chip incorporated in the component built-in multilayer circuit board of FIG. FIG. 3 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 4 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 5 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 6 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 7 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 8 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 9 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 10 is a cross-sectional view showing a first step of manufacturing the component built-in multilayer circuit board of FIG. FIG. 11 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 12 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 13 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 14 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 15 is a cross-sectional view showing a step subsequent to the step of FIG. 16 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 17 is a cross-sectional view showing the next process of the process of FIG. 18 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 19 is a cross-sectional view showing the next process of the process of FIG. 20 is a (1) cross-sectional view and (2) plan view showing the next process of the process of FIG. FIG. 21 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 22 is a (1) cross-sectional view and (2) plan view showing the next process of the process of FIG. FIG. 23 is a cross-sectional view (1) and a plan view (2) showing the next step of the step of FIG. FIG. 24 is a cross-sectional view showing the next process of the process of FIG. FIG. 25 is a cross-sectional view showing the next process of the process of FIG. FIG. 26 is a cross-sectional view showing the next process of the process of FIG. FIG. 27 is a cross-sectional view showing the next process of the process of FIG. FIG. 28 is a cross-sectional view showing the next process of the process of FIG. 29 is a (1) cross-sectional view and (2) plan view showing a component built-in multilayer circuit board according to Embodiment 2 of the present invention. 30 is a cross-sectional view showing a first step of manufacturing the component built-in multilayer circuit board of FIG. FIG. 31 is a cross-sectional view showing a step subsequent to the step of FIG. FIG. 32 is a (1) cross-sectional view and (2) plan view showing the next process of the process of FIG. FIG. 33 is a (1) cross-sectional view and (2) plan view showing the next process of the process of FIG. 32. FIG. 34 is a (1) cross-sectional view and (2) plan view showing the next process of the process of FIG. FIG. 35 is a cross-sectional view showing the next process of the process of FIG. FIG. 36 is a cross-sectional view showing the next process of the process of FIG. FIG. 37 is a (1) cross-sectional view and (2) plan view showing the next process of the process of FIG. 36. FIG. 38 is a sectional view showing a component built-in multilayer circuit board according to a reference technique. FIG. 39 is a cross-sectional view showing a first step in the manufacturing process of the semiconductor chip incorporated in the component built-in multilayer circuit board of FIG. FIG. 40 is a cross-sectional view showing the next process of the process of FIG. FIG. 41 is a cross-sectional view showing the next process of the process of FIG. FIG. 42 is a cross-sectional view showing the next process of the process of FIG. FIG. 43 is a cross-sectional view showing the next process of the process of FIG. FIG. 44 is a cross-sectional view showing the next process of the process of FIG. FIG. 45 is a cross-sectional view showing the next process of the process of FIG. FIG. 46 is a cross-sectional view showing the next process of the process of FIG. 47 is a cross-sectional view showing an initial stage process for manufacturing the component built-in multilayer circuit board of FIG. FIG. 48 is a cross-sectional view showing the next process of the process of FIG. FIG. 49 is a cross-sectional view showing the next process of the process of FIG. FIG. 50 is a cross-sectional view showing the next process of the process of FIG. FIG. 51 is a cross-sectional view showing the next process of the process of FIG. FIG. 52 is a cross-sectional view showing the next process of the process of FIG. FIG. 53 is a cross-sectional view showing the next process of the process of FIG. FIG. 54 is a cross-sectional view showing the next process of the process of FIG. FIG. 55 is a cross-sectional view showing the next process of the process of FIG. FIG. 56 is a cross-sectional view showing the next process of the process of FIG. FIG. 57 is a cross-sectional view showing the next process of the process of FIG. 58 is a cross-sectional view showing the next process of the process of FIG. FIG. 59 is a cross-sectional view showing the next process of the process of FIG. FIG. 60 is a cross-sectional view showing the next process of the process of FIG. FIG. 61 is a cross-sectional view showing the next process of the process of FIG. FIG. 62 is a cross-sectional view showing the next process of the process of FIG.

Explanation of symbols

10, 20, 30 Component built-in multilayer circuit board 100 Core substrate 102, 104 Upper side wiring layer 104A, 104B Heat transfer layer 104BL Heat transfer line 106 Lower side wiring layer 108, 110 Wiring interlayer insulating film 108A, 144 Chip receiving port 112 Surface insulating film on upper surface 114 Surface insulating film on lower surface 116, 117 Semiconductor chip 116A, 117A Circuit surface of semiconductor chip 116B, 117B Back surface of semiconductor chip 118 Heat transfer layer 118A Chip side heat transfer layer 118B Substrate side heat transfer layer 120 Thermal via 122, 124 Metal plating layer 126, 150 Conductive adhesive layer 128, 152 Heat sink 130, 132 Connection via 134 Through hole 135, 154 Connection pad 136 External connection terminal 137 Raw hole filling resin

Claims (7)

In a multilayer circuit board with a built-in component, which is formed by alternately laminating a plurality of wiring layers and insulating layers on a core substrate, and includes at least a semiconductor chip as a circuit component,
The semiconductor chip is disposed with its circuit surface facing upward in the same direction as the stacking direction, and the following (1) to (3):
(1) A structure in which the back surface of the semiconductor chip is bonded to the core substrate via a heat transfer layer,
(2) A heat transfer via formed on the circuit surface of the semiconductor chip through the insulating layer provided immediately above the semiconductor chip is thermally connected to a heat sink provided on the upper surface of the circuit board. And (3) heat dissipation via which the heat transfer via formed on the circuit surface of the semiconductor chip through the insulating layer provided immediately above the semiconductor chip is exposed on the side surface of the circuit board. Structure thermally connected to the board,
The structure (1) and any one of the structures (2) and (3) are combined, and the semiconductor chip and the heat transfer layer are provided in the same insulating layer. And
(A) In the structure in which the structures (1) and (2) are combined, an external connection terminal is formed on the surface of the core substrate opposite to the semiconductor chip formation surface, and the external connection terminal and the semiconductor chip are Electrically connected through a through hole provided in the core substrate,
(B) In the structure in which the structures (1) and (3) are combined, the heat transfer via and the heat radiating plate are thermally transferred via a heat transfer line provided on the insulating layer in which the heat transfer via is formed. A multilayer circuit board with a built-in component, characterized by being connected to   2. The circuit board according to claim 1, wherein the heat transfer layer in the structure (1) is any one of a conductive paste containing conductive particles, an adhesive film containing conductive particles, and a metal layer. Multi-layer circuit board with built-in components.   3. The component built-in multilayer circuit board according to claim 2, wherein each of the conductive particles and the metal column is made of any one of Ni, Ag, Cu, and Au.   3. The circuit board according to claim 2, wherein the metal layer is formed by bonding a metal plating layer formed on the layer immediately below and a metal sputter layer formed on the back surface of the semiconductor chip. The component built-in multilayer circuit board.   The circuit board according to claim 1, wherein the heat dissipation plate in the structures (2) and (3) is a metal plate.   2. The circuit board according to claim 1, wherein in the case of having the structure of (A), the semiconductor chip and the external connection terminal include a first insulating layer surrounding the semiconductor chip, the semiconductor chip, and the first A multilayer circuit board with a built-in component, which is electrically connected through a via penetrating a second insulating layer provided immediately above the insulating layer.   The circuit board according to claim 6, wherein the heat radiating plate covers one surface side of the second insulating layer.

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