JP6433662B2 - 多軸角速度センサ - Google Patents
多軸角速度センサ Download PDFInfo
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- JP6433662B2 JP6433662B2 JP2014016124A JP2014016124A JP6433662B2 JP 6433662 B2 JP6433662 B2 JP 6433662B2 JP 2014016124 A JP2014016124 A JP 2014016124A JP 2014016124 A JP2014016124 A JP 2014016124A JP 6433662 B2 JP6433662 B2 JP 6433662B2
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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Description
(角速度センサの概略構成)
図1は、本発明の実施形態に係る角速度センサ51の構成を示す分解斜視図である。図2(a)は、角速度センサ51の一部(蓋体59)を取り外して角速度センサ51の内部を示す平面図である。図2(b)は、図2(a)のIIb−IIb線における角速度センサ51の断面図である。
図3(a)は、センサ素子1を示す斜視図である。なお、図3(a)においては、X軸センサ素子1XとY軸センサ素子1Yとの相違部分については省略し、両者の共通部分のみを図示している。
図1、図2(a)及び図2(b)に示すように、X軸センサ素子1X及びY軸センサ素子1Yは、互いに重ね合わされて実装面57aに支持(固定)されている。すなわち、これら2つのセンサ素子1は、個別には、実装基体57の実装面57aに支持されない。従って、実装面57aの平面視において、2つのセンサ素子1全体としての面積は、重ね合わされた面積分で小さくされており、従来と比較して小型化することができる。具体的には、以下のとおりである。
図5(a)、図5(b)及び図6は、第2の実施形態に係る角速度センサ251の要部を示す図である。具体的には、図5(a)は、角速度センサ251のX軸センサ素子201X及びY軸センサ素子201Y(以下、単に「センサ素子201」ということがある。)を示す分解斜視図である。図5(b)は、2つのセンサ素子201を固定した状態で示す斜視図である。図6は、角速度センサ251の断面図(第1の実施形態の図2(b)に相当)である。
図7及び図8は、第3の実施形態に係る角速度センサ351の要部を示す図である。具体的には、図7は、角速度センサ351におけるパッド及び配線の一例を示す模式的な斜視図(第1の実施形態の図4に相当)である。図8は、角速度センサ351の断面図(第1の実施形態の図2(b)に相当)である。
Claims (3)
- 第1基部、及び所定の並び方向に並べられ、この並び方向に交差する延在方向の同一側へ前記第1基部から延びる複数の第1腕を有する第1圧電体を含み、所定の第1軸回りの角速度に応じた電気信号を出力可能な圧電振動式の第1センサ素子と、
第2基部、及び所定の並び方向に並べられ、この並び方向に交差する延在方向の同一側へ前記第2基部から延びる複数の第2腕を有する第2圧電体を含み、所定の第2軸回りの角速度に応じた電気信号を出力可能な圧電振動式の第2センサ素子と、
実装面を有する実装基体と、
を有し、
前記第1基部及び前記第2基部は、前記第1軸と前記第2軸とが互いに異なる方向となり、前記第1基部の、前記複数の第1腕の延在方向及び並び方向に沿う面と、前記第2基部の、前記複数の第2腕の延在方向及び並び方向に沿う面とが互いに対向し、かつ前記第1腕の延在方向と前記第2腕の延在方向とが互いに異なる方向となる位置関係で互いに固定されており、
前記第1基部は、前記第2基部側の面において、前記第1腕側の第1非重複領域に対して前記第1腕とは反対側の第1重複領域が低くされることにより、前記第1重複領域における厚みが前記第1非重複領域における厚みよりも薄くされており、
前記第2基部は、前記第1基部側の面において、前記第2腕側の第2非重複領域に対して前記第2腕とは反対側の第2重複領域が低くされることにより、前記第2重複領域における厚みが前記第2非重複領域における厚みよりも薄くされており、
前記第1重複領域と前記第2重複領域とが重ねられ、前記第1非重複領域と前記第2非重複領域とは重ねられておらず、
前記第1重複領域は、前記複数の第1腕の並び方向において前記複数の第1腕全体の両側外側の面間に亘る幅を有しており、
前記第2重複領域は、前記複数の第2腕の並び方向において前記複数の第2腕全体の両側外側の面間に亘る幅を有しており、
前記第1基部の、前記第2基部に対向する面とは反対側の面は、前記実装面に対向するとともに、平面透視において前記第1重複領域と重複する範囲において当該反対側の面と前記実装面との間に介在するバンプによって、前記実装面に固定されている
多軸角速度センサ。 - 前記実装面のうち前記第1腕と前記第2腕とに挟まれた領域に少なくとも一部が位置する集積回路素子を更に有する
請求項1に記載の多軸角速度センサ。 - 前記第1圧電体は、前記第1基部のうち前記第1腕が延びる側にのみ、前記第1腕を含む全ての腕を有し、
前記第2圧電体は、前記第2基部のうち前記第2腕が延びる側にのみ、前記第2腕を含む全ての腕を有している
請求項1又は2に記載の多軸角速度センサ。
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JP6433662B2 true JP6433662B2 (ja) | 2018-12-05 |
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CN113169265A (zh) * | 2018-11-30 | 2021-07-23 | 京瓷株式会社 | 多轴角速度传感器 |
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JPH06294654A (ja) * | 1993-04-08 | 1994-10-21 | Towa Electron Kk | 振動ジャイロ |
JP2009128351A (ja) * | 2007-11-19 | 2009-06-11 | Microstone Corp | ジャイロセンサ振動体 |
JP4678427B2 (ja) * | 2008-06-23 | 2011-04-27 | 株式会社村田製作所 | 振動ジャイロ |
JP5181938B2 (ja) * | 2008-09-03 | 2013-04-10 | 株式会社大真空 | 音叉型水晶振動子 |
JP2010101727A (ja) * | 2008-10-23 | 2010-05-06 | Citizen Holdings Co Ltd | 振動体パッケージ及びそれを用いた振動ジャイロセンサ |
JP2011133246A (ja) * | 2009-12-22 | 2011-07-07 | Sony Corp | 角速度センサ及び電子機器 |
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