JP6430971B2 - Ｎ相システムのための電圧モードドライバ回路 - Google Patents

Ｎ相システムのための電圧モードドライバ回路 Download PDF

Info

Publication number
JP6430971B2
JP6430971B2 JP2015561730A JP2015561730A JP6430971B2 JP 6430971 B2 JP6430971 B2 JP 6430971B2 JP 2015561730 A JP2015561730 A JP 2015561730A JP 2015561730 A JP2015561730 A JP 2015561730A JP 6430971 B2 JP6430971 B2 JP 6430971B2
Authority
JP
Japan
Prior art keywords
transistor
phase
signals
voltage level
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2015561730A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016511608A5 (cg-RX-API-DMAC7.html
JP2016511608A (ja
Inventor
チュルキュ・リー
ジョージ・アラン・ウィリー
祥一郎 仙石
祥一郎 仙石
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016511608A publication Critical patent/JP2016511608A/ja
Publication of JP2016511608A5 publication Critical patent/JP2016511608A5/ja
Application granted granted Critical
Publication of JP6430971B2 publication Critical patent/JP6430971B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/06—Control of transmission; Equalising by the transmitted signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
JP2015561730A 2013-03-07 2014-03-07 Ｎ相システムのための電圧モードドライバ回路 Expired - Fee Related JP6430971B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361774425P 2013-03-07 2013-03-07
US61/774,425 2013-03-07
US14/199,064 2014-03-06
US14/199,064 US9172426B2 (en) 2013-03-07 2014-03-06 Voltage mode driver circuit for N-phase systems
PCT/US2014/021994 WO2014138646A1 (en) 2013-03-07 2014-03-07 Voltage mode driver circuit for n-phase systems

Publications (3)

Publication Number Publication Date
JP2016511608A JP2016511608A (ja) 2016-04-14
JP2016511608A5 JP2016511608A5 (cg-RX-API-DMAC7.html) 2017-03-30
JP6430971B2 true JP6430971B2 (ja) 2018-11-28

Family

ID=51487798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015561730A Expired - Fee Related JP6430971B2 (ja) 2013-03-07 2014-03-07 Ｎ相システムのための電圧モードドライバ回路

Country Status (8)

Country Link
US (1) US9172426B2 (cg-RX-API-DMAC7.html)
EP (1) EP2965216B1 (cg-RX-API-DMAC7.html)
JP (1) JP6430971B2 (cg-RX-API-DMAC7.html)
KR (1) KR20150126906A (cg-RX-API-DMAC7.html)
CN (1) CN105164659B (cg-RX-API-DMAC7.html)
ES (1) ES2632283T3 (cg-RX-API-DMAC7.html)
HU (1) HUE033607T2 (cg-RX-API-DMAC7.html)
WO (1) WO2014138646A1 (cg-RX-API-DMAC7.html)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9215063B2 (en) * 2013-10-09 2015-12-15 Qualcomm Incorporated Specifying a 3-phase or N-phase eye pattern
TWI859712B (zh) 2014-03-25 2024-10-21 日商新力股份有限公司 發送裝置及通訊系統
US9166584B1 (en) * 2014-06-09 2015-10-20 Xilinx, Inc. Current-encoded signaling
US9112550B1 (en) 2014-06-25 2015-08-18 Kandou Labs, SA Multilevel driver for high speed chip-to-chip communications
US20160179739A1 (en) * 2014-12-17 2016-06-23 Intel Corporation Symmetrically coupled differential channel
US9998154B2 (en) 2015-06-22 2018-06-12 Qualcomm Incorporated Low power physical layer driver topologies
US10419252B2 (en) 2015-06-22 2019-09-17 Qualcomm Incorporated Low power physical layer driver topologies
US9553635B1 (en) 2015-07-24 2017-01-24 Qualcomm Incorporated Time based equalization for a C-PHY 3-phase transmitter
US9520988B1 (en) 2015-08-04 2016-12-13 Qualcomm Incorporated Adaptation to 3-phase signal swap within a trio
JP6665441B2 (ja) 2015-08-10 2020-03-13 ソニー株式会社 送信装置、受信装置、および通信システム
WO2017190102A1 (en) * 2016-04-28 2017-11-02 Kandou Labs, S.A. Low power multilevel driver
EP3529956B1 (en) * 2016-10-24 2021-07-21 Qualcomm Incorporated Reducing transmitter encoding jitter in a c-phy interface using multiple clock phases to launch symbols
TW201830940A (zh) * 2017-02-08 2018-08-16 陳淑玲 三線式傳輸的穿戴裝置
TW201843945A (zh) * 2017-03-03 2018-12-16 日商索尼半導體解決方案公司 傳送裝置及通信系統
US10496583B2 (en) 2017-09-07 2019-12-03 Kandou Labs, S.A. Low power multilevel driver for generating wire signals according to summations of a plurality of weighted analog signal components having wire-specific sub-channel weights
KR101959139B1 (ko) 2017-10-13 2019-03-15 한양대학교 산학협력단 동시 스위칭 잡음 및 간섭을 제거하는 고속 데이터 송수신 시스템 및 방법
CN108073539A (zh) * 2017-12-27 2018-05-25 上海集成电路研发中心有限公司 一种mipi接口的d-phy电路
KR102286729B1 (ko) * 2018-01-03 2021-08-05 한양대학교 산학협력단 동시 스위칭 잡음이 없고 높은 신호선 효율을 가지는 송신기 및 이에 있어서 데이터 전송 방법
KR102034368B1 (ko) * 2018-01-03 2019-10-18 한양대학교 산학협력단 동시 스위칭 잡음이 없고 높은 신호선 효율을 가지는 송신기 및 이에 있어서 데이터 전송 방법
KR102034369B1 (ko) * 2018-01-05 2019-10-18 한양대학교 산학협력단 동시 스위칭 잡음을 제거하면서 클록 및 데이터를 전송할 수 있는 송신기 및 이의 동작 방법
US10855254B2 (en) * 2019-01-31 2020-12-01 Marvell Asia Pte, Ltd. Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver
US10873323B2 (en) * 2019-01-31 2020-12-22 Marvell Asia Pte, Ltd. Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver
WO2023287437A1 (en) * 2021-07-16 2023-01-19 Lattice Semiconductor Corporation Communication systems and methods
US12063034B2 (en) 2022-08-30 2024-08-13 Kandou Labs SA Line driver impedance calibration for multi-wire data bus

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH572687A5 (cg-RX-API-DMAC7.html) * 1972-04-11 1976-02-13 Europ Teletransmission
JPS59108430A (ja) * 1982-12-13 1984-06-22 Matsushita Electric Ind Co Ltd ２値−３値変換回路
JPH0691459B2 (ja) * 1986-05-21 1994-11-14 松下電器産業株式会社 ３値出力回路
JPH02174445A (ja) * 1988-12-27 1990-07-05 Toshiba Corp 複線式データ伝送装置
JPH0442616A (ja) * 1990-06-08 1992-02-13 Rohm Co Ltd ３値出力回路
US6051990A (en) * 1997-11-13 2000-04-18 Quantum Corporation Asymmetric current mode driver for differential transmission lines
ATE400097T1 (de) 2001-08-13 2008-07-15 Motorola Inc Drahtlose kommunikation mit sendediversität
US7170949B2 (en) * 2002-03-14 2007-01-30 Intel Corporation Methods and apparatus for signaling on a differential link
JPWO2005074219A1 (ja) 2004-01-28 2007-11-15 松下電器産業株式会社 データ送信装置、データ受信装置、伝送路符号化方法および復号方法
KR100782305B1 (ko) 2006-01-09 2007-12-06 삼성전자주식회사 3개의 전송선의 차동신호화에 의한 데이터 신호 송수신장치 및 송수신 방법
US8064535B2 (en) * 2007-03-02 2011-11-22 Qualcomm Incorporated Three phase and polarity encoded serial interface
US7936180B2 (en) * 2008-02-01 2011-05-03 Mediatek Inc. Serial link transmitter

Also Published As

Publication number Publication date
US9172426B2 (en) 2015-10-27
CN105164659A (zh) 2015-12-16
US20140254712A1 (en) 2014-09-11
KR20150126906A (ko) 2015-11-13
WO2014138646A1 (en) 2014-09-12
JP2016511608A (ja) 2016-04-14
CN105164659B (zh) 2018-02-06
HUE033607T2 (en) 2017-12-28
EP2965216A1 (en) 2016-01-13
ES2632283T3 (es) 2017-09-12
EP2965216B1 (en) 2017-04-19

Similar Documents

Publication Publication Date Title
JP6430971B2 (ja) Ｎ相システムのための電圧モードドライバ回路
JP6325537B2 (ja) Ｎ相極性出力ピンモードマルチプレクサ
US10134272B2 (en) N-phase polarity data transfer
JP6832874B2 (ja) 低電力物理層ドライバトポロジー
US20140112401A1 (en) 3dynamic configuration of an n-phase polarity data communications link
WO2015021262A1 (en) Run-length detection and correction
EP3831023A1 (en) Low power physical layer driver topologies

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170221

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170221

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180223

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180604

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20181005

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20181101

R150 Certificate of patent or registration of utility model

Ref document number: 6430971

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees