JP6384175B2

JP6384175B2 - Semiconductor light emitting device

Info

Publication number: JP6384175B2
Application number: JP2014151309A
Authority: JP
Inventors: 恵滋榎村
Original assignee: Nichia Corp
Current assignee: Nichia Corp
Priority date: 2014-07-25
Filing date: 2014-07-25
Publication date: 2018-09-05
Anticipated expiration: 2034-07-25
Also published as: JP2016025341A

Description

半導体発光素子に関する。 The present invention relates to a semiconductor light emitting device.

従来、複数の発光ダイオード（半導体ユニット）を等マトリックス方式で基材上に作製し、金属蒸着の方式により接続リードライン（配線）を蒸着し、マトリックス発光ダイオード単体（半導体発光素子）を形成する発明が提案された（特許文献１参照）。 Conventionally, an invention in which a plurality of light emitting diodes (semiconductor units) are produced on a substrate by an equal matrix method, and a connection lead line (wiring) is deposited by a metal vapor deposition method to form a single matrix light emitting diode (semiconductor light emitting element). Has been proposed (see Patent Document 1).

実用新案登録第３１１７２８１号公報Utility Model Registration No. 3117281

しかしながら、上記従来の半導体発光素子では、複数の半導体ユニット間で輝度に偏りが生じるというという問題があった。 However, the conventional semiconductor light emitting device has a problem in that the luminance is uneven among a plurality of semiconductor units.

上記の課題は、次の手段により解決される。 The above problem is solved by the following means.

同一の基板上で一方向に配列して形成された同一構造からなる３つ以上の半導体ユニットと、前記３つ以上の半導体ユニットのうち一端の半導体ユニットに形成された第１端子と、前記３つ以上の半導体ユニットのうち他端の半導体ユニットに形成された第２端子と、前記第１端子が形成された半導体ユニットと他の半導体ユニットとが接続されるよう前記３つ以上の半導体ユニットにまたがって形成された第１配線と、前記第２端子が形成された半導体ユニットと他の半導体ユニットとが接続されるよう前記３つ以上の半導体ユニットにまたがって形成された第２配線と、を備え、前記第１配線の半導体ユニット間における各抵抗値は、前記第１端子から離れるに従って大きくなり、前記第２配線の半導体ユニット間における各抵抗値は、前記第２端子から離れるに従って大きくなる、ことを特徴とする半導体発光素子。 Three or more semiconductor units having the same structure formed in one direction on the same substrate, a first terminal formed on one of the three or more semiconductor units, and the 3 The second terminal formed on the semiconductor unit at the other end of the two or more semiconductor units, the semiconductor unit on which the first terminal is formed, and the other semiconductor units are connected to the three or more semiconductor units. A first wiring formed across the semiconductor unit, and a second wiring formed across the three or more semiconductor units so that the semiconductor unit on which the second terminal is formed and another semiconductor unit are connected to each other. Each resistance value between the semiconductor units of the first wiring increases as the distance from the first terminal increases, and each resistance value between the semiconductor units of the second wiring is Serial increases as the distance from the second terminal a semiconductor light emitting device characterized by.

上記の半導体発光素子によれば、複数の半導体ユニット間における輝度の偏りを軽減することができる。 According to the semiconductor light emitting device described above, it is possible to reduce the unevenness of luminance among the plurality of semiconductor units.

実施形態１に係る半導体発光素子の模式的平面図である。1 is a schematic plan view of a semiconductor light emitting element according to Embodiment 1. FIG. 図１Ａ中のＡ−Ａ断面図である。It is AA sectional drawing in FIG. 1A. 図１Ａ中のＢ−Ｂ断面図である。It is BB sectional drawing in FIG. 1A. 図１Ａ中のＣ−Ｃ断面図である。It is CC sectional drawing in FIG. 1A. 実施形態１に係る半導体発光素子の等価回路図である。2 is an equivalent circuit diagram of the semiconductor light emitting device according to Embodiment 1. FIG. 実施形態２に係る半導体発光素子の模式的平面図である。5 is a schematic plan view of a semiconductor light emitting element according to Embodiment 2. FIG. 図２Ａ中のＡ−Ａ断面図である。It is AA sectional drawing in FIG. 2A. 図２Ａ中のＢ−Ｂ断面図である。It is BB sectional drawing in FIG. 2A. 図２Ａ中のＤ−Ｄ断面図である。It is DD sectional drawing in FIG. 2A. 実施形態２に係る半導体発光素子の等価回路図である。5 is an equivalent circuit diagram of a semiconductor light emitting element according to Embodiment 2. FIG. 実施形態３に係る半導体発光素子の模式的平面図である。6 is a schematic plan view of a semiconductor light emitting element according to Embodiment 3. FIG. 図３Ａ中のＡ−Ａ断面図である。It is AA sectional drawing in FIG. 3A. 図３Ａ中のＢ−Ｂ断面図である。It is BB sectional drawing in FIG. 3A. 図３Ａ中のＥ−Ｅ断面図である。It is EE sectional drawing in FIG. 3A. 実施形態３に係る半導体発光素子の等価回路図である。6 is an equivalent circuit diagram of a semiconductor light emitting element according to Embodiment 3. FIG. 実施形態４に係る半導体発光素子の模式的平面図である。6 is a schematic plan view of a semiconductor light emitting element according to Embodiment 4. FIG. 図４Ａ中のＡ−Ａ断面図である。It is AA sectional drawing in FIG. 4A. 図４Ａ中のＢ−Ｂ断面図である。It is BB sectional drawing in FIG. 4A. 図４Ａ中のＦ−Ｆ断面図である。It is FF sectional drawing in FIG. 4A. 実施形態４に係る半導体発光素子の等価回路図である。6 is an equivalent circuit diagram of a semiconductor light emitting element according to Embodiment 4. FIG.

［実施形態１に係る半導体発光素子］
図１Ａは実施形態１に係る半導体発光素子の模式的平面図であり、図１Ｂは図１Ａ中のＡ−Ａ断面図であり、図１Ｃは図１Ａ中のＢ−Ｂ断面図であり、図１Ｄは図１Ａ中のＣ−Ｃ断面図であり、図１Ｅは実施形態１に係る半導体発光素子の等価回路図である。以下、図１Ａ〜１Ｅを参照しつつ、実施形態１に係る半導体発光素子１について説明する。 [Semiconductor Light Emitting Element According to Embodiment 1]
1A is a schematic plan view of a semiconductor light emitting device according to Embodiment 1, FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB in FIG. 1D is a cross-sectional view taken along the line CC in FIG. 1A, and FIG. 1E is an equivalent circuit diagram of the semiconductor light emitting device according to the first embodiment. Hereinafter, the semiconductor light emitting element 1 according to Embodiment 1 will be described with reference to FIGS.

実施形態１に係る半導体発光素子１は、同一の基板１０上で一方向に配列して形成された同一構造からなる３つ以上の半導体ユニット２１、２２、２３と、３つ以上の半導体ユニット２１、２２、２３のうち一端の半導体ユニット２１に形成された第１端子３１と、３つ以上の半導体ユニット２１、２２、２３のうち他端の半導体ユニット２３に形成された第２端子３２と、第１端子３１が形成された半導体ユニット２１と他の半導体ユニット２２、２３とが接続されるよう３つ以上の半導体ユニット２１、２２、２３にまたがって形成された第１配線４１と、第２端子３２が形成された半導体ユニット２３と他の半導体ユニット２１、２２とが接続されるよう３つ以上の半導体ユニット２１、２２、２３にまたがって形成された第２配線４２と、を備え、第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２は、第１端子３１から離れるに従って大きくなり、第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２は、第２端子３２から離れるに従って大きくなる半導体発光素子である。以下、順に説明する。 The semiconductor light emitting device 1 according to Embodiment 1 includes three or more semiconductor units 21, 22, and 23 having the same structure and arranged in one direction on the same substrate 10, and three or more semiconductor units 21. , 22 and 23, a first terminal 31 formed on the semiconductor unit 21 at one end, a second terminal 32 formed on the semiconductor unit 23 at the other end of the three or more semiconductor units 21, 22, and 23, A first wiring 41 formed across three or more semiconductor units 21, 22, 23 so that the semiconductor unit 21 in which the first terminal 31 is formed and the other semiconductor units 22, 23 are connected; Second wiring 4 formed across three or more semiconductor units 21, 22, 23 so that the semiconductor unit 23 in which the terminal 32 is formed and the other semiconductor units 21, 22 are connected. The resistance values R11 and R12 between the semiconductor units of the first wiring 41 increase as the distance from the first terminal 31 increases, and the resistance values R21 and R22 between the semiconductor units of the second wiring 42 This is a semiconductor light emitting device that becomes larger as the distance from the two terminals 32 increases. Hereinafter, it demonstrates in order.

（３つ以上の半導体ユニット２１、２２、２３）
３つ以上の半導体ユニット２１、２２、２３は、同一の基板１０上で一方向に配列して形成されている。３つ以上の半導体ユニット２１、２２、２３は同一構造からなる。各半導体ユニット２１、２２、２３は、例えば図１に示すように、基板１０上に設けられた第１半導体層Ｌ１と、第１半導体層Ｌ１上に第１半導体層Ｌ１の一部が露出するよう設けられた第２半導体層Ｌ２と、を有している。ここで、基板１０には、例えば、サファイアやスピネル（ＭｇＡｌ_２Ｏ_４）などの絶縁性基板１０を用いることができる。また、第１半導体層Ｌ１及び第２半導体層Ｌ２には、半導体発光素子に適した材料を用いることが好ましく、例えば、Ｉｎ_ＸＡｌ_ＹＧａ_{１−Ｘ−Ｙ}Ｎ（０≦Ｘ、０≦Ｙ、Ｘ＋Ｙ＜１）等の半導体を用いることが好ましい。第１半導体層Ｌ１と第２半導体層Ｌ２との間には活性層ＡＬ（発光層）が含まれていてもよく、この場合、活性層ＡＬ（発光層）には量子効果が生ずる薄膜を積層した単一量子井戸や多重量子井戸構造などを用いることができる。第２半導体層Ｌ２上には透光性電極６０などの電極を設けることができる。なお、本実施形態では、半導体発光素子１が３つの半導体ユニットを備える場合について説明するが、半導体発光素子１は４つ以上の半導体ユニットを備えることもできる。 (Three or more semiconductor units 21, 22, 23)
Three or more semiconductor units 21, 22, and 23 are formed in one direction on the same substrate 10. Three or more semiconductor units 21, 22, and 23 have the same structure. In each of the semiconductor units 21, 22, and 23, for example, as shown in FIG. 1, a first semiconductor layer L1 provided on the substrate 10 and a part of the first semiconductor layer L1 are exposed on the first semiconductor layer L1. The second semiconductor layer L2 is provided. Here, for the substrate 10, for example, an insulating substrate 10 such as sapphire or spinel (MgAl ₂ O ₄ ) can be used. For the first semiconductor layer L1 and the second semiconductor layer L2, it is preferable to use a material suitable for a semiconductor light emitting element. For example, In _X Al _Y Ga _1-XY N (0 ≦ X, 0 ≦ Y , X + Y <1) or the like is preferably used. An active layer AL (light emitting layer) may be included between the first semiconductor layer L1 and the second semiconductor layer L2, and in this case, a thin film that produces a quantum effect is laminated on the active layer AL (light emitting layer). A single quantum well or a multiple quantum well structure can be used. An electrode such as the translucent electrode 60 can be provided on the second semiconductor layer L2. In addition, although this embodiment demonstrates the case where the semiconductor light-emitting device 1 is provided with three semiconductor units, the semiconductor light-emitting device 1 can also be provided with four or more semiconductor units.

（第１端子３１、第２端子３２）
第１端子３１は３つ以上の半導体ユニット２１、２２、２３のうち一端の半導体ユニット２１に形成され、第２端子３２は３つ以上の半導体ユニット２１、２２、２３のうち他端の半導体ユニット２３に形成される。第１端子３１と第２端子３２は対角位置に形成される。 (First terminal 31, second terminal 32)
The first terminal 31 is formed on one semiconductor unit 21 of the three or more semiconductor units 21, 22, 23, and the second terminal 32 is the other semiconductor unit of the three or more semiconductor units 21, 22, 23. 23. The first terminal 31 and the second terminal 32 are formed at diagonal positions.

第１端子３１や第２端子３２には、例えば、Ａｇ、Ａｌ、Ｎｉ、Ｒｈ、Ａｕ、Ｃｕ、Ｔｉ、Ｐｔ、Ｐｄ、Ｍｏ、Ｃｒ、Ｗなどの単体金属又はこれらの金属を主成分とする合金などを用いることができ、さらに、これらの金属材料を単層で、又は積層したものを利用することができる。なお、合金を用いる場合は、例えば、ＡｌＳｉＣｕ合金のように、組成元素としてＳｉなどの非金属元素を含有するものであってもよい。また、第１端子３１や第２端子３２はスパッタ法や電解メッキなどの方法により形成することができ、エッチングによるパターン形成法やリフトオフによるパターン形成法などの当該分野で公知の方法によって形状を整形することができる。 For the first terminal 31 and the second terminal 32, for example, a single metal such as Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, or these metals is a main component. An alloy or the like can be used, and further, a single layer or a laminate of these metal materials can be used. In addition, when using an alloy, you may contain nonmetallic elements, such as Si, as a composition element like an AlSiCu alloy, for example. The first terminal 31 and the second terminal 32 can be formed by a method such as sputtering or electrolytic plating, and the shape is shaped by a method known in the art such as a pattern formation method by etching or a pattern formation method by lift-off. can do.

第１端子３１や第２端子３２を第２半導体層Ｌ２上において設けることにより、第１端子３１が設けられる半導体ユニット２１や第２端子３２が設けられる半導体ユニット２３において第２半導体層Ｌ２を除去して第１半導体層Ｌ１を露出させ、この上に第１端子３１や第２端子３２を設ける場合とは異なり、第１端子３１及び第２端子３２が設けられる半導体ユニット２１、２３の第２半導体層Ｌ２の形状と、第１端子３１及び第２端子３２が設けられない半導体ユニット２２の第２半導体層Ｌ２の形状と、を同一にして、３つ以上の半導体ユニット２１、２２、２３における各発光面積を同一にすることが可能となる。なお、第１端子３１及び第２端子３２は、例えば絶縁層７０を用いることにより第２半導体層Ｌ２から絶縁することができる。 By providing the first terminal 31 and the second terminal 32 on the second semiconductor layer L2, the second semiconductor layer L2 is removed from the semiconductor unit 21 provided with the first terminal 31 and the semiconductor unit 23 provided with the second terminal 32. Unlike the case where the first semiconductor layer L1 is exposed and the first terminal 31 and the second terminal 32 are provided thereon, the second of the semiconductor units 21 and 23 in which the first terminal 31 and the second terminal 32 are provided. The shape of the semiconductor layer L2 is the same as the shape of the second semiconductor layer L2 of the semiconductor unit 22 in which the first terminal 31 and the second terminal 32 are not provided. In the three or more semiconductor units 21, 22, and 23, Each light emitting area can be made the same. In addition, the 1st terminal 31 and the 2nd terminal 32 can be insulated from the 2nd semiconductor layer L2 by using the insulating layer 70, for example.

（第１配線４１、第２配線４２）
第１配線４１は第１端子３１が形成された半導体ユニット２１と他の半導体ユニット２２、２３とが接続されるよう３つ以上の半導体ユニット２１、２２、２３にまたがって形成される。第２配線４２は第２端子３２が形成された半導体ユニット２３と他の半導体ユニット２１、２２とが接続されるよう３つ以上の半導体ユニット２１、２２、２３にまたがって形成される。第１配線４１や第２配線４２は、例えば、第１端子３１や第２配線４２と同じ材料により構成することができる。なお、第１配線４１及び第２配線４２の上には、例えば、保護膜８０が形成される。 (First wiring 41, second wiring 42)
The first wiring 41 is formed across three or more semiconductor units 21, 22, 23 so that the semiconductor unit 21 in which the first terminal 31 is formed and the other semiconductor units 22, 23 are connected. The second wiring 42 is formed across three or more semiconductor units 21, 22, 23 so that the semiconductor unit 23 in which the second terminal 32 is formed and the other semiconductor units 21, 22 are connected. The first wiring 41 and the second wiring 42 can be made of the same material as the first terminal 31 and the second wiring 42, for example. For example, a protective film 80 is formed on the first wiring 41 and the second wiring 42.

第１配線４１は、３つ以上の半導体ユニット２１、２２、２３の各第２半導体層Ｌ２上において該各第２半導体層Ｌ２から絶縁されるよう形成された共通部分４１ａと、共通部分４１ａから延伸して各第２半導体層Ｌ２にそれぞれ導通するよう形成された複数の個別部分４１ｂと、を有することが好ましい。また、第２配線４２は、３つ以上の半導体ユニット２１、２２、２３の各第２半導体層Ｌ２上において各第２半導体層Ｌ２から絶縁されるよう形成された共通部分４２ａと、共通部分４２ａから延伸して各第２半導体層Ｌ２から露出する各第１半導体層Ｌ１にそれぞれ導通するよう形成された複数の個別部分４２ｂと、を有することが好ましい。このようにすれば、各半導体ユニット２１、２２、２３に同じ形状の個別部分４１ｂ、４２ｂを最小限の面積で配置することができるため、第１配線４１及び第２配線４２の各抵抗値Ｒ１１、Ｒ１２、Ｒ２１、Ｒ２２を共通部分４１ａ、４２ａの抵抗値にほぼ等しいとみなして、共通部分４１ａ、４２ａの形状や面積などの違いにより設定することが可能になる。 The first wiring 41 includes a common portion 41a formed on each second semiconductor layer L2 of the three or more semiconductor units 21, 22, and 23 so as to be insulated from the second semiconductor layer L2, and a common portion 41a. It is preferable to have a plurality of individual portions 41b formed so as to extend and to be electrically connected to the respective second semiconductor layers L2. The second wiring 42 includes a common portion 42a formed on each second semiconductor layer L2 of the three or more semiconductor units 21, 22, and 23 so as to be insulated from each second semiconductor layer L2, and a common portion 42a. And a plurality of individual portions 42b formed so as to be electrically connected to the first semiconductor layers L1 exposed from the second semiconductor layers L2. In this way, the individual parts 41b and 42b having the same shape can be disposed in the semiconductor units 21, 22 and 23 with a minimum area, so that the resistance values R11 of the first wiring 41 and the second wiring 42 can be obtained. , R12, R21, and R22 are considered to be substantially equal to the resistance values of the common portions 41a and 42a, and can be set according to differences in the shapes and areas of the common portions 41a and 42a.

（抵抗値）
第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２は、第１端子３１から離れるに従って大きくなり、第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２は、第２端子３２から離れるに従って大きくなる。このようにすれば、各半導体ユニット２１、２２、２３を流れる電流が均一になるよう、第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２と第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２とを設定することが可能となる。なお、本実施形態では、Ｒ１１：Ｒ２１＝１：２、Ｒ１２：Ｒ２２＝２：１となるよう、第１配線４１と第２配線４２との半導体ユニット間における各抵抗値（共通部分４１ａ、４２ａと個別部分４１ｂ、４２ｂを形成する場合は共通部分４１ａ、４２ａの半導体ユニット間における各抵抗値）が設定されるものとする。 (Resistance value)
The resistance values R11 and R12 between the semiconductor units of the first wiring 41 increase as the distance from the first terminal 31 increases, and the resistance values R21 and R22 between the semiconductor units of the second wiring 42 move away from the second terminal 32. Grows according to. In this way, the resistance values R11, R12 between the semiconductor units of the first wiring 41 and the resistances between the semiconductor units of the second wiring 42 so that the currents flowing through the semiconductor units 21, 22, 23 are uniform. The values R21 and R22 can be set. In the present embodiment, the resistance values (common portions 41a, 42a) between the semiconductor units of the first wiring 41 and the second wiring 42 are set so that R11: R21 = 1: 2, R12: R22 = 2: 1. When the individual portions 41b and 42b are formed, each resistance value between the semiconductor units of the common portions 41a and 42a is set.

第１配線４１の幅及び／又は厚みは、第１端子３１から離れるに従って小さくなることが好ましい。このようにすれば、簡単に、第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２を第１端子３１から離れるに従って大きくすることができる（本実施形態ではＲ１１＜Ｒ１２）。また、大きな電流が流れやすい第１端子３１に近い側において第１配線４１の幅や厚みが大きくなるため、第１配線４１の焼損を抑制するという効果を得ることもできる。なお、本実施形態では、図１Ａに示すように、半導体ユニット２１と半導体ユニット２２とにまたがって形成される第１配線４１（具体的には第１配線４１の共通部分４１ａ）の幅が半導体ユニット２２と半導体ユニット２３とにまたがって形成される第１配線４１（具体的には第１配線４１の共通部分４１ａ）の幅よりも大きくなるよう第１配線４１（具体的には第１配線４１の共通部分４１ａ）の幅を段階的に形成し、これにより、第１配線４１の幅が第１端子３１から離れるに従って小さくなるようにし、もって、第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２が第１端子３１から離れるに従って大きくなる（すなわちＲ１１＜Ｒ１２になる）ようにする。ただし、これは一例であり、本実施形態においては、半導体ユニット２１と半導体ユニット２２とにまたがって形成される第１配線４１（具体的には第１配線４１の共通部分４１ａ）の厚み（あるいは幅と厚みの双方）が半導体ユニット２２と半導体ユニット２３とにまたがって形成される第１配線４１（具体的には第１配線４１の共通部分４１ａ）の厚み（あるいは幅と厚みの双方）よりも大きくなるよう第１配線４１（具体的には第１配線４１の共通部分４１ａ）の厚み（あるいは幅と厚みの双方）を段階的に形成し、これにより、第１配線４１の厚み（あるいは幅と厚みの双方）が第１端子３１から離れるに従って小さくなるようにし、もって、第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２が第１端子３１から離れるに従って大きくなる（すなわちＲ１１＜Ｒ１２になる）ようにしてもよい。 It is preferable that the width and / or thickness of the first wiring 41 decreases as the distance from the first terminal 31 increases. In this way, the resistance values R11 and R12 between the semiconductor units of the first wiring 41 can be easily increased as the distance from the first terminal 31 increases (R11 <R12 in the present embodiment). In addition, since the width and thickness of the first wiring 41 are increased on the side close to the first terminal 31 where a large current easily flows, an effect of suppressing the burning of the first wiring 41 can be obtained. In the present embodiment, as shown in FIG. 1A, the width of the first wiring 41 (specifically, the common portion 41a of the first wiring 41) formed across the semiconductor unit 21 and the semiconductor unit 22 is a semiconductor. The first wiring 41 (specifically, the first wiring) is larger than the width of the first wiring 41 (specifically, the common portion 41a of the first wiring 41) formed across the unit 22 and the semiconductor unit 23. 41 is formed stepwise so that the width of the first wiring 41 decreases as the distance from the first terminal 31 increases, so that each resistance between the semiconductor units of the first wiring 41 can be reduced. The values R11 and R12 are increased as the distance from the first terminal 31 increases (that is, R11 <R12). However, this is only an example, and in the present embodiment, the thickness of the first wiring 41 (specifically, the common portion 41a of the first wiring 41) formed across the semiconductor unit 21 and the semiconductor unit 22 (or, specifically, the first wiring 41). The width (thickness and thickness) of the first wiring 41 (specifically, the common portion 41a of the first wiring 41) formed across the semiconductor unit 22 and the semiconductor unit 23 (specifically, both the width and thickness). The thickness (or both width and thickness) of the first wiring 41 (specifically, the common portion 41a of the first wiring 41) is formed stepwise so as to increase the thickness of the first wiring 41 (or Both the width and the thickness) are reduced as the distance from the first terminal 31 increases, so that the resistance values R11 and R12 between the semiconductor units of the first wiring 41 are separated from the first terminal 31. Runishitagatte increases may be (i.e. R11 <becomes R12) as.

同様に、第２配線４２の幅及び／又は厚みは、第２端子３２から離れるに従って小さくなることが好ましい。このようにすれば、簡単に、第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２を第２端子３２から離れるに従って大きくすることができる（本実施形態ではＲ２１＞Ｒ２２）。また、大きな電流が流れやすい第２端子３２に近い側において第２配線４２の幅や厚みが大きくなるため、第２配線４２の焼損を抑制するという効果を得ることもできる。なお、本実施形態では、図１Ａに示すように、半導体ユニット２３と半導体ユニット２２とにまたがって形成される第２配線４２（具体的には第２配線４２の共通部分４２ａ）の幅が半導体ユニット２２と半導体ユニット２１とにまたがって形成される第２配線４２（具体的には第２配線４２の共通部分４２ａ）の幅よりも大きくなるよう第２配線４２（具体的には第２配線４２の共通部分４２ａ）の幅を段階的に形成し、これにより、第２配線４２の幅が第２端子３２から離れるに従って小さくなるようにし、もって、第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２が第２端子３１から離れるに従って大きくなる（すなわちＲ２１＞Ｒ２２になる）ようにする。ただし、これは一例であり、本実施形態においては、半導体ユニット２３と半導体ユニット２２とにまたがって形成される第２配線４２（具体的には第２配線４２の共通部分４２ａ）の厚み（あるいは幅と厚みの双方）が半導体ユニット２２と半導体ユニット２１とにまたがって形成される第２配線４２（具体的には第２配線４２の共通部分４２ａ）の厚み（あるいは幅と厚みの双方）よりも大きくなるよう第２配線４２（具体的には第２配線４２の共通部分４２ａ）の厚み（あるいは幅と厚みの双方）を段階的に形成し、これにより、第２配線４２の厚み（あるいは幅と厚みの双方）が第２端子３２から離れるに従って小さくなるようにし、もって、第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２が第２端子３１から離れるに従って大きくなる（すなわちＲ２１＞Ｒ２２になる）ようにしてもよい。 Similarly, the width and / or thickness of the second wiring 42 is preferably reduced as the distance from the second terminal 32 increases. In this way, each resistance value R21, R22 between the semiconductor units of the second wiring 42 can be easily increased as the distance from the second terminal 32 increases (R21> R22 in this embodiment). Further, since the width and thickness of the second wiring 42 are increased on the side close to the second terminal 32 where a large current easily flows, an effect of suppressing the burning of the second wiring 42 can be obtained. In the present embodiment, as shown in FIG. 1A, the width of the second wiring 42 (specifically, the common portion 42a of the second wiring 42) formed across the semiconductor unit 23 and the semiconductor unit 22 is a semiconductor. The second wiring 42 (specifically, the second wiring) is larger than the width of the second wiring 42 (specifically, the common part 42a of the second wiring 42) formed across the unit 22 and the semiconductor unit 21. 42, the width of the common portion 42a) is formed stepwise, whereby the width of the second wiring 42 decreases as the distance from the second terminal 32 increases, so that each resistance between the semiconductor units of the second wiring 42 is reduced. The values R21 and R22 are increased as the distance from the second terminal 31 increases (that is, R21> R22). However, this is an example, and in the present embodiment, the thickness of the second wiring 42 (specifically, the common portion 42a of the second wiring 42) formed over the semiconductor unit 23 and the semiconductor unit 22 (or the common portion 42a). The width (thickness and thickness) of the second wiring 42 (specifically, the common portion 42 a of the second wiring 42) formed across the semiconductor unit 22 and the semiconductor unit 21 (or both the width and thickness). The thickness (or both width and thickness) of the second wiring 42 (specifically, the common portion 42a of the second wiring 42) is formed stepwise so as to increase the thickness of the second wiring 42 (or Both the width and the thickness) are reduced as the distance from the second terminal 32 increases, so that the resistance values R21 and R22 between the semiconductor units of the second wiring 42 are separated from the second terminal 31. Runishitagatte increases (i.e. R21> becomes R22) it may be.

なお、第１配線４１及び第２配線４２の幅及び／又は厚みについて、「離れるに従って大きく（又は小さく）なる」とは、図１Ａのような段階的に大きく（又は小さく）なることに限られず、連続的に大きく（又は小さく）なることを含む。 In addition, regarding the width and / or thickness of the first wiring 41 and the second wiring 42, “increasing (or decreasing) with increasing distance” is not limited to increasing in steps (or decreasing) as illustrated in FIG. 1A. , Including continuously increasing (or decreasing).

以上説明したように、実施形態１に係る半導体発光素子１では、第１配線４１の半導体ユニット間における各抵抗値Ｒ１１、Ｒ１２を第１端子３１から離れるに従って大きくするとともに、第２配線４２の半導体ユニット間における各抵抗値Ｒ２１、Ｒ２２を第２端子３２から離れるに従って大きくしたので、同じ大きさの電流を流した場合に同じ輝度で発光する同一構造の半導体ユニット２１、２２、２３の各々に対して、同じ大きさの電流を流すことができる。したがって、実施形態１に係る半導体発光素子１によれば、複数の半導体ユニット２１、２２、２３間における輝度の偏りを軽減される。 As described above, in the semiconductor light emitting device 1 according to the first embodiment, the resistance values R11 and R12 between the semiconductor units of the first wiring 41 are increased as the distance from the first terminal 31 increases, and the semiconductor of the second wiring 42 is increased. Since the resistance values R21 and R22 between the units are increased with increasing distance from the second terminal 32, each of the semiconductor units 21, 22, and 23 having the same structure that emit light with the same luminance when the same magnitude of current is passed. Current of the same magnitude can be applied. Therefore, according to the semiconductor light emitting element 1 according to the first embodiment, the unevenness of luminance among the plurality of semiconductor units 21, 22, 23 is reduced.

［実施形態２に係る半導体発光素子］
図２Ａは実施形態２に係る半導体発光素子の模式的平面図であり、図２Ｂは図２Ａ中のＡ−Ａ断面図であり、図２Ｃは図２Ａ中のＢ−Ｂ断面図であり、図２Ｄは図２Ａ中のＤ−Ｄ断面図であり、図２Ｅは実施形態２に係る半導体発光素子の等価回路図である。以下、図２Ａ〜２Ｄを参照しつつ、実施形態２に係る半導体発光素子について説明する。 [Semiconductor Light Emitting Element According to Embodiment 2]
2A is a schematic plan view of the semiconductor light emitting device according to Embodiment 2, FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A, and FIG. 2C is a cross-sectional view taken along line BB in FIG. 2D is a sectional view taken along the line DD in FIG. 2A, and FIG. 2E is an equivalent circuit diagram of the semiconductor light emitting device according to the second embodiment. Hereinafter, the semiconductor light emitting device according to the second embodiment will be described with reference to FIGS.

実施形態２に係る半導体発光素子では、３つ以上の半導体ユニット２１、２２、２３が、基板１０上に設けられた第１半導体層Ｌ１と第１半導体層Ｌ１上に第１半導体層Ｌ１の一部が露出するよう設けられた第２半導体層Ｌ２とを有する複数の半導体積層体５０を有する。複数の半導体積層体５０は、第１半導体層Ｌ１と第２半導体層Ｌ２とを接続する第３配線４３により３つ以上の半導体ユニット２１、２２、２３の各々において直列接続されている。また、第１端子３１は、第３配線４３により直列接続された複数の半導体積層体５０のうちの一端となる半導体積層体５０が有する第２半導体層Ｌ２上において第２半導体層Ｌ２から絶縁されるよう形成されている。第２端子３２は、第３配線４３により直列接続された複数の半導体積層体５０のうちの他端となる半導体積層体５０が有する第２半導体層Ｌ２上において第２半導体層Ｌ２から絶縁されるよう形成されている。さらに、第１配線４１は、第３配線４３により直列接続された複数の半導体積層体５０のうちの一端となる各半導体積層体５０が有する各第２半導体層Ｌ２上において各第２半導体層Ｌ２から絶縁されるよう形成された共通部分４１ａと、共通部分４１ａから延伸して各第２半導体層Ｌ２にそれぞれ導通するよう形成された複数の個別部分４１ｂと、を有する。第２配線４２は、第３配線４３により直列接続された複数の半導体積層体５０のうちの他端となる各半導体積層体５０が有する各第２半導体層Ｌ２上において各第２半導体層Ｌ２から絶縁されるよう形成された共通部分４２ａと、共通部分４２ａから延伸して該各第２半導体層Ｌ２から露出する各第１半導体層Ｌ１にそれぞれ導通するよう形成された複数の個別部分４２ｂと、を有する。第１端子３１と第２端子３２は対角位置に形成される。実施形態２に係る半導体発光素子によれば、１つの半導体ユニットに対してまとめて電流が流れるのではなく、１つの半導体ユニットよりも狭い領域である個々の半導体積層体５０に電流がそれぞれ流れるようになるため、より一層、第１配線４１及び第２配線４２の個別部分４１ｂ、４２ｂから均一に電流が広がるようになり、複数の半導体ユニット間における輝度の偏りが軽減される。なお、第３配線４３には、例えば、第１端子３１、第２端子３２、第１配線４１、第２配線４２と同じ材料を用いることができる。 In the semiconductor light emitting device according to the second embodiment, three or more semiconductor units 21, 22, and 23 are provided on the first semiconductor layer L1 provided on the substrate 10 and on the first semiconductor layer L1. A plurality of semiconductor stacked bodies 50 having a second semiconductor layer L2 provided so that the portion is exposed. The plurality of semiconductor stacked bodies 50 are connected in series in each of the three or more semiconductor units 21, 22, and 23 by a third wiring 43 that connects the first semiconductor layer L <b> 1 and the second semiconductor layer L <b> 2. The first terminal 31 is insulated from the second semiconductor layer L2 on the second semiconductor layer L2 included in the semiconductor stacked body 50 that is one end of the plurality of semiconductor stacked bodies 50 connected in series by the third wiring 43. It is formed so that. The second terminal 32 is insulated from the second semiconductor layer L2 on the second semiconductor layer L2 of the semiconductor stacked body 50 that is the other end of the plurality of semiconductor stacked bodies 50 connected in series by the third wiring 43. It is formed as follows. Further, the first wiring 41 is formed on each second semiconductor layer L2 on each second semiconductor layer L2 included in each semiconductor stacked body 50 serving as one end of the plurality of semiconductor stacked bodies 50 connected in series by the third wiring 43. Common portion 41a formed so as to be insulated from each other, and a plurality of individual portions 41b formed so as to extend from common portion 41a and to be electrically connected to each second semiconductor layer L2. The second wiring 42 extends from each second semiconductor layer L2 on each second semiconductor layer L2 of each semiconductor stacked body 50 that is the other end of the plurality of semiconductor stacked bodies 50 connected in series by the third wiring 43. A common portion 42a formed to be insulated, and a plurality of individual portions 42b formed to be electrically connected to the first semiconductor layers L1 extending from the common portion 42a and exposed from the second semiconductor layers L2. Have The first terminal 31 and the second terminal 32 are formed at diagonal positions. According to the semiconductor light emitting device according to the second embodiment, currents do not flow collectively to one semiconductor unit, but currents flow to the individual semiconductor stacked bodies 50 that are narrower than one semiconductor unit. As a result, the current spreads uniformly from the individual portions 41b and 42b of the first wiring 41 and the second wiring 42, and the unevenness of luminance among the plurality of semiconductor units is reduced. For example, the same material as the first terminal 31, the second terminal 32, the first wiring 41, and the second wiring 42 can be used for the third wiring 43.

［実施形態３、４に係る半導体発光素子］
図３Ａは実施形態３に係る半導体発光素子の模式的平面図であり、図３Ｂは図３Ａ中のＡ−Ａ断面図であり、図３Ｃは図３Ａ中のＢ−Ｂ断面図であり、図３Ｄは図３Ａ中のＥ−Ｅ断面図であり、図３Ｅは実施形態３に係る半導体発光素子の等価回路図である。また、図４Ａは実施形態４に係る半導体発光素子の模式的平面図であり、図４Ｂは図４Ａ中のＡ−Ａ断面図であり、図４Ｃは図４Ａ中のＢ−Ｂ断面図であり、図４Ｄは図４Ａ中のＦ−Ｆ断面図であり、図４Ｅは実施形態４に係る半導体発光素子の等価回路図である。以下、図３Ａ〜３Ｅ及び図４Ａ〜４Ｅを参照しつつ、実施形態３、４に係る半導体発光素子について説明する。 [Semiconductor Light Emitting Element According to Embodiments 3 and 4]
3A is a schematic plan view of the semiconductor light emitting device according to Embodiment 3, FIG. 3B is a cross-sectional view taken along line AA in FIG. 3A, and FIG. 3C is a cross-sectional view taken along line BB in FIG. 3D is a cross-sectional view taken along line EE in FIG. 3A, and FIG. 3E is an equivalent circuit diagram of the semiconductor light emitting device according to the third embodiment. 4A is a schematic plan view of the semiconductor light emitting device according to Embodiment 4, FIG. 4B is a cross-sectional view taken along line AA in FIG. 4A, and FIG. 4C is a cross-sectional view taken along line BB in FIG. 4A. 4D is a cross-sectional view taken along line FF in FIG. 4A, and FIG. 4E is an equivalent circuit diagram of the semiconductor light emitting device according to the fourth embodiment. Hereinafter, the semiconductor light emitting element according to Embodiments 3 and 4 will be described with reference to FIGS. 3A to 3E and FIGS. 4A to 4E.

実施形態３、４に係る半導体発光素子は、第３配線４３上に第３端子３３を備えている点で、第３端子３３を備えていない実施形態１、２に係る半導体発光素子と相違する。また、実施形態３、４に係る半導体発光素子は、第１端子３１と第３端子３３が対角位置に形成され、第２端子３２と第３端子３３が対角位置に形成される点で、第１端子３１と第２端子３２が対角位置に形成される実施形態１、２に係る半導体発光素子と相違する。実施形態３、４に係る半導体発光素子によっても、実施形態１、２に係る半導体発光素子と同様に、複数の半導体ユニット間における輝度の偏りが軽減される。 The semiconductor light emitting devices according to the third and fourth embodiments are different from the semiconductor light emitting devices according to the first and second embodiments that do not include the third terminal 33 in that the third terminal 33 is provided on the third wiring 43. . In the semiconductor light emitting devices according to the third and fourth embodiments, the first terminal 31 and the third terminal 33 are formed at diagonal positions, and the second terminal 32 and the third terminal 33 are formed at diagonal positions. The first terminal 31 and the second terminal 32 are different from the semiconductor light emitting device according to the first and second embodiments in which the first terminal 31 and the second terminal 32 are formed at diagonal positions. Also by the semiconductor light emitting elements according to the third and fourth embodiments, the luminance unevenness among the plurality of semiconductor units is reduced, similarly to the semiconductor light emitting elements according to the first and second embodiments.

以上、実施形態について説明したが、これらの説明は一例に関するものであり、特許請求の範囲に記載された構成を何ら限定するものではない。 While the embodiments have been described above, these descriptions are only examples, and do not limit the configurations described in the claims.

１半導体発光素子
１０基板
２１半導体ユニット
２２半導体ユニット
２３半導体ユニット
３１第１端子
３２第２端子
３３第３端子
４１第１配線
４１ａ共通部分
４１ｂ個別部分
４２第２配線
４２ａ共通部分
４２ｂ個別部分
４３第３配線
Ｒ１１、Ｒ１２第１配線の半導体ユニット間における各抵抗値
Ｒ２１、Ｒ２２第２配線の半導体ユニット間における各抵抗値
５０半導体積層体
６０透光性電極
７０絶縁層
８０保護膜
Ｌ１第１半導体層
Ｌ２第２半導体層
ＡＬ活性層 DESCRIPTION OF SYMBOLS 1 Semiconductor light-emitting device 10 Board | substrate 21 Semiconductor unit 22 Semiconductor unit 23 Semiconductor unit 31 1st terminal 32 2nd terminal 33 3rd terminal 41 1st wiring 41a Common part 41b Individual part 42 2nd wiring 42a Common part 42b Individual part 43 3rd Wiring R11, R12 Each resistance value R21, R22 between the semiconductor units of the first wiring 50 Each resistance value 50 between the semiconductor units of the second wiring 50 Semiconductor laminated body 60 Translucent electrode 70 Insulating layer 80 Protective film L1 First semiconductor layer L2 Second semiconductor layer AL active layer

Claims

A first semiconductor layer formed on the same substrate and arranged in one direction on the same substrate, and a part of the first semiconductor layer exposed on the first semiconductor layer. Three or more semiconductor units having a second semiconductor layer provided
A first terminal formed so as to be insulated from the second semiconductor layer on the second semiconductor layer included in the semiconductor unit at one end of the three or more semiconductor units;
A second terminal formed so as to be insulated from the second semiconductor layer on the second semiconductor layer included in the semiconductor unit at the other end of the three or more semiconductor units;
A common portion connected to the first terminal formed across the three or more semiconductor units so as to be insulated from the second semiconductor layers on the second semiconductor layers of the three or more semiconductor units ; A first wiring having a plurality of individual portions extending from the common portion and formed to be electrically connected to the second semiconductor layers, respectively .
A common portion connected to the second terminal formed across the three or more semiconductor units so as to be insulated from the second semiconductor layers on the second semiconductor layers of the three or more semiconductor units ; A second wiring having a plurality of individual portions formed to extend from the common portion and to be electrically connected to the first semiconductor layers exposed from the second semiconductor layers ,
With
Each resistance value between the semiconductor units of the first wiring increases as the distance from the first terminal increases.
Each resistance value between the semiconductor units of the second wiring increases as the distance from the second terminal increases.
A semiconductor light emitting element characterized by the above.

Same Ri Do the same structure formed by arranging in one direction on the substrate, a portion of the first semiconductor layer is exposed to the first semiconductor layer and the first semiconductor layer provided on the substrate A plurality of semiconductor stacks each having a second semiconductor layer provided in such a manner that each of the plurality of semiconductor stacks is connected by a third wiring that connects the first semiconductor layer and the second semiconductor layer. Three or more semiconductor units connected in series ;
On the second semiconductor layer of the semiconductor stacked body serving as one end of the plurality of semiconductor stacked bodies connected in series by the third wiring included in the semiconductor unit at one end of the three or more semiconductor units, the second semiconductor layer A first terminal formed to be insulated from the semiconductor layer ;
On the second semiconductor layer of the semiconductor stacked body which is the other end of the plurality of semiconductor stacked bodies connected in series by the third wiring included in the semiconductor unit at the other end of the three or more semiconductor units , A second terminal formed to be insulated from the second semiconductor layer ;
The three or more semiconductors are insulated from each second semiconductor layer on each second semiconductor layer included in each semiconductor stacked body that is one end of the plurality of semiconductor stacked bodies connected in series by the third wiring. A first portion having a common portion connected to the first terminal formed across the unit, and a plurality of individual portions extending from the common portion and formed to be electrically connected to the second semiconductor layers . Wiring and
The three or more semiconductor layers that are the other ends of the plurality of semiconductor stacks connected in series by the third wirings are insulated from the second semiconductor layers on the second semiconductor layers of the second semiconductor layers . A common portion connected to the second terminal formed across the semiconductor unit, and a plurality of portions formed to be electrically connected to the first semiconductor layers extending from the common portion and exposed from the second semiconductor layers. A second wiring having :
With
Each resistance value between the semiconductor units of the first wiring increases as the distance from the first terminal increases.
Each resistance value between the semiconductor units of the second wiring increases as the distance from the second terminal increases.
A semiconductor light emitting element characterized by the above.

The semiconductor light emitting device according to claim 1, wherein the first terminal and the second terminal are formed at diagonal positions.

A first semiconductor layer formed on the same substrate and arranged in one direction on the same substrate, and a part of the first semiconductor layer exposed on the first semiconductor layer. Three or more semiconductor units having a second semiconductor layer provided
A first terminal and a second terminal formed on the second semiconductor layer included in the semiconductor unit at one end of the three or more semiconductor units so as to be insulated from the second semiconductor layer;
A common portion connected to the first terminal formed across the three or more semiconductor units so as to be insulated from the second semiconductor layers on the second semiconductor layers of the three or more semiconductor units; A first wiring having a plurality of individual portions extending from the common portion and formed to be electrically connected to the second semiconductor layers, respectively.
A common portion connected to the second terminal formed across the three or more semiconductor units so as to be insulated from the second semiconductor layers on the second semiconductor layers of the three or more semiconductor units; A second wiring having a plurality of individual portions extending from the common portion and formed to be electrically connected to the second semiconductor layers, respectively.
A third terminal formed on the semiconductor unit at the other end of the three or more semiconductor units;
A common portion connected to the third terminal formed across the three or more semiconductor units, and a first portion extending from the common portion and exposed from each second semiconductor layer of the three or more semiconductor units. A third wiring having a plurality of individual portions formed to be electrically connected to one semiconductor layer,
With
Each resistance value between the semiconductor units of the first wiring increases as the distance from the first terminal increases.
Each resistance value between the semiconductor units of the second wiring increases as the distance from the second terminal increases.
A semiconductor light emitting element characterized by the above.

A first semiconductor layer formed on the same substrate and arranged in one direction on the same substrate, and a part of the first semiconductor layer exposed on the first semiconductor layer. Three or more semiconductor units having a second semiconductor layer provided
A first terminal and a second terminal formed on the second semiconductor layer included in the semiconductor unit at the other end of the three or more semiconductor units so as to be insulated from the second semiconductor layer;
A common portion connected to the first terminal formed across the three or more semiconductor units so as to be insulated from the second semiconductor layers on the second semiconductor layers of the three or more semiconductor units; A first wiring having a plurality of individual portions formed to extend from the common portion and to be electrically connected to the first semiconductor layers exposed from the second semiconductor layers,
A common portion connected to the second terminal formed across the three or more semiconductor units so as to be insulated from the second semiconductor layers on the second semiconductor layers of the three or more semiconductor units; A second wiring having a plurality of individual portions formed to extend from the common portion and to be electrically connected to the first semiconductor layers exposed from the second semiconductor layers,
A third terminal formed on one of the three or more semiconductor units;
A common portion connected to the third terminal formed across the three or more semiconductor units, and extending from the common portion to be electrically connected to each second semiconductor layer of the three or more semiconductor units. A third wiring having a plurality of individual portions formed;
With
Each resistance value between the semiconductor units of the first wiring increases as the distance from the first terminal increases.
Each resistance value between the semiconductor units of the second wiring increases as the distance from the second terminal increases.
A semiconductor light emitting element characterized by the above.

6. The light emitting device according to claim 4, wherein a distance between the first terminal and the third terminal and a distance between the second terminal and the third terminal are substantially equal in a top view. element.

Wherein the respective resistance value between the semiconductor unit of the second wiring and the resistance value between the semiconductor unit of the first wiring, claim 1, wherein the current through each semiconductor unit is a value that is uniform The semiconductor light-emitting device according to any one of 6 .

8. The semiconductor light emitting element according to claim 1, wherein the width and / or thickness of the first wiring decreases with increasing distance from the first terminal. 9.

9. The semiconductor light emitting element according to claim 1, wherein the width and / or thickness of the second wiring decreases as the distance from the second terminal increases.