KR102519080B1 - Light emitting diode having plurality of light emitting cells - Google Patents

Abstract

A light emitting diode having a plurality of light emitting cells is provided. The light emitting diode includes first to fourth light emitting cells disposed on a substrate; a first electrode pad; and a second electrode pad, wherein each light emitting cell includes a lower semiconductor layer, an active layer, and an upper semiconductor layer, and the lower semiconductor layer includes a first lower semiconductor layer and a second lower semiconductor layer spaced apart from each other. In addition, the first light-emitting cell and the second light-emitting cell share the first lower semiconductor layer, the third light-emitting cell and the fourth light-emitting cell share the second lower semiconductor layer, and the first light-emitting cell is connected to the third light-emitting cell. are connected in series, and the second light emitting cell is connected in series to the fourth light emitting cell. Furthermore, the first electrode pad is electrically connected to the upper semiconductor layer of the first light emitting cell and the second light emitting cell, and the second electrode pad is electrically connected to the lower semiconductor layer of the third light emitting cell and the fourth light emitting cell. . Accordingly, a highly efficient light emitting diode can be provided.

Description

Light emitting diode having a plurality of light emitting cells {LIGHT EMITTING DIODE HAVING PLURALITY OF LIGHT EMITTING CELLS}

The present invention relates to a light emitting diode, and more particularly, to a light emitting diode having a plurality of light emitting cells.

A light emitting diode (LED) is a solid state light emitting device that converts electrical energy into light. Light emitting diodes are widely used as light sources in backlight units, lighting devices, signals, large displays, and the like. As the lighting LED market expands and its application range expands to high current density and high power fields, there is a need to improve the characteristics of light emitting diodes for stable driving during high current driving.

In general, when the current density applied to the light emitting diode is increased, the amount of light emitted from the light emitting diode is increased. However, a droop phenomenon in which the external quantum efficiency decreases as the current density increases occurs. The droop phenomenon means that the rate at which light is lost increases as the current density increases, and is an obstacle to increasing the luminous efficiency expressed in lm/W.

An object to be solved by the present invention is to provide a light emitting diode suitable for providing a high efficiency light emitting device.

Another problem to be solved by the present invention is to provide a light emitting diode with improved droop phenomenon.

According to one embodiment of the present invention, a substrate; first to fourth light emitting cells disposed on the substrate; a first electrode pad; and a second electrode pad, wherein each light emitting cell includes a lower semiconductor layer, an upper semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, wherein the lower semiconductor layer is spaced apart from the first lower semiconductor layer. and a second lower semiconductor layer, wherein the first light emitting cell and the second light emitting cell share a first lower semiconductor layer, and the third light emitting cell and the fourth light emitting cell share a second lower semiconductor layer. The first light emitting cell is connected in series to the third light emitting cell, the second light emitting cell is connected in series to the fourth light emitting cell, and the first electrode pad is connected to the first light emitting cell and the second light emitting cell. A light emitting diode electrically connected to the upper semiconductor layer of the cell, and the second electrode pad electrically connected to the lower semiconductor layer of the third light emitting cell and the fourth light emitting cell.

By connecting the light emitting cells in series, it is possible to reduce the driving current of the light emitting diode, thereby reducing the current density and improving light emitting efficiency. Furthermore, by connecting the light emitting cells in parallel, the current input to the light emitting cells can be evenly distributed to the light emitting cells, thereby reducing the droop phenomenon.

1 is a plan view for explaining a light emitting diode according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view taken along the line AA of Fig. 1;
FIG. 3 is a cross-sectional view taken along the cut line BB in FIG. 1;
FIG. 4 is a cross-sectional view taken along the line CC of FIG. 1 .
FIG. 5 is an enlarged plan view of the first electrode pad of FIG. 1 .
FIG. 6 is an enlarged plan view of the second electrode pad of FIG. 1 .
7 is a photograph showing a light emitting pattern of a light emitting diode according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention may be embodied in other forms without being limited to the embodiments described below. And, in the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Also, when an element is described as being “on top of” or “on” another element, each part is “immediately on” or “directly on” the other element, as well as each element and other elements. It also includes the case where another component is interposed in between. Like reference numbers indicate like elements throughout the specification.

A light emitting diode according to an embodiment of the present invention includes a substrate; first to fourth light emitting cells disposed on the substrate; a first electrode pad; and a second electrode pad. Here, each light emitting cell includes a lower semiconductor layer, an upper semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, and the lower semiconductor layer includes a first lower semiconductor layer and a second lower semiconductor layer spaced apart from each other. wherein the first light emitting cell and the second light emitting cell share a first lower semiconductor layer, the third light emitting cell and the fourth light emitting cell share a second lower semiconductor layer, and the first light emitting cell is connected in series to the third light emitting cell, the second light emitting cell is connected in series to the fourth light emitting cell, and the first electrode pad is electrically connected to the upper semiconductor layer of the first light emitting cell and the second light emitting cell. , and the second electrode pad is electrically connected to the lower semiconductor layer of the third light emitting cell and the fourth light emitting cell. Accordingly, a light emitting diode having light emitting cells connected in series and parallel is provided, and thus, current density for driving can be reduced and current can be evenly distributed among the light emitting cells, thereby improving light emitting efficiency.

Moreover, since the first and second light emitting cells and the third and fourth light emitting cells share the first lower semiconductor layer and the second lower semiconductor layer, the manufacturing process is simple and the decrease in light emitting area due to separation of the light emitting cells is minimized. can do.

Specifically, the first lower semiconductor layer and the second lower semiconductor layer may be separated by a separation groove exposing an upper surface of the substrate, the first light emitting cell, the second light emitting cell, and the third light emitting cell. The cell and the fourth light emitting cell may be separated by a mesa separation groove exposing the first lower semiconductor layer and the second lower semiconductor layer, respectively.

In some embodiments, the light emitting diode may further include a transparent electrode layer disposed on the upper semiconductor layer of each light emitting cell.

Also, the first electrode pad may be disposed on the mesa separation groove, and furthermore, may be disposed across the first light emitting cell and the second light emitting cell. In this case, the transparent electrode layers may be disposed between the first and second light emitting cells and the first electrode pad, respectively.

In addition, the light emitting diode may further include a current blocking layer disposed below the first electrode pad. The current blocking layer may have an area larger than that of the first electrode pad so that the first electrode pad is limitedly disposed on the current blocking layer, and a portion of the current blocking layer is formed on the first light emitting cell and the second light emitting cell. It may be disposed between the cell and the transparent electrode layer.

Each of the transparent electrode layers on the first light emitting cell and the second light emitting cell may have an opening exposing the current blocking layer, and the first electrode pad may contact the current blocking layer through the opening.

The light emitting diode may include upper extension parts disposed on the transparent electrode layer on each light emitting cell and electrically connected to the transparent electrode layer; and current blocking layers disposed between the transparent electrode layers and the light emitting cells under the upper extension portions. A width of the current blocking layers may be less than three times a width of the upper extension portions. The current blocking layer helps the current to be evenly distributed in the light emitting cell area. In addition, by controlling the width of the current blocking layer, light loss due to the current blocking layer can be reduced.

The light emitting diode may further include lower extension parts connected to the lower semiconductor layer of each light emitting cell. Each lower extension may include a straight line area extending in the same direction, the straight line area of the lower extension of the first light emitting cell is parallel to the straight area of the lower extension of the third light emitting cell, and the second light emitting cell A straight area of the lower extension of may be parallel to a straight area of the lower extension of the fourth light emitting cell.

Upper extensions disposed on the transparent electrode layers of the first light emitting cell and the second light emitting cell are electrically connected to the first electrode pad and connected to the lower semiconductor layers of the third light emitting cell and the fourth light emitting cell. The lower extension parts are electrically connected to the second electrode pad. Accordingly, the light emitting cells are connected in series and parallel between the first electrode pad and the second electrode pad.

Furthermore, each upper extension may include a main upper extension having a shape surrounding a portion of the corresponding lower extension and a secondary upper extension protruding from the main upper extension.

The auxiliary extensions on the first light emitting cell and the second light emitting cell may be disposed to connect the main upper extension to the first electrode pad, and the auxiliary extensions on the third light emitting cell and the fourth light emitting cell may connect the main upper extension to the first electrode pad. The main upper extensions of the light emitting cell and the fourth light emitting cell may be connected to the lower extensions of the first light emitting cell and the second light emitting cell, respectively.

The auxiliary upper extensions on the first light emitting cell and the second light emitting cell may be connected to the main upper extension closer to the mesa separation groove than the corresponding lower extension. Accordingly, the length of the auxiliary upper extension portion can be reduced.

The light emitting diode may further include connection parts connecting the lower extension parts of the first and second light emitting cells and the auxiliary upper extension parts of the third and fourth light emitting cells, respectively. Furthermore, the light emitting diode may further include an insulating layer insulating the connecting parts from the second lower semiconductor layer of the third light emitting cell and the fourth light emitting cell.

Further, the lower extensions of the third light emitting cell and the fourth light emitting cell may further include lower extensions of a curved area connecting the lower extensions of the straight area to the second electrode pad. Furthermore, the second electrode pad may be disposed on the second lower semiconductor layer exposed by the mesa separation groove.

The light emitting diode may further include an insulating layer covering side surfaces of the upper semiconductor layer and the active layer around the second electrode pad. This insulating layer can prevent a short circuit from being generated by the bonding material in the ball bonding process.

An insulating layer covering side surfaces of the upper semiconductor layer and the active layer may be spaced apart from the transparent electrode layer.

In some embodiments, the first electrode pad and the second electrode pad may be disposed to face each other, the first electrode pad is disposed near one edge of the substrate, and the second electrode pad is disposed near the edge of the substrate. It may be disposed near one edge of the substrate opposite the other edge.

Meanwhile, the main upper extensions on the third light emitting cell and the fourth light emitting cell have an inner end disposed between the lower extension of the third light emitting cell and the lower extension of the fourth light emitting cell, and an outer side of the lower extension, respectively. It may have an outer end disposed thereon, and an outer end of the lower extension may be disposed closer to the other edge than the inner end.

In addition, the light emitting diode may have a symmetrical structure with respect to a line passing through the first electrode pad and the second electrode pad.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view for explaining a light emitting diode according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1, FIG. 3 is a cross-sectional view taken along the line B-B in FIG. 1, and FIG. is a cross-sectional view taken along the cut line C-C in FIG. 5 and 6 are enlarged plan views of the first and second electrode pads of FIG. 1 , respectively.

First, referring to FIG. 1 , a light emitting diode according to this embodiment includes a first light emitting cell C1, a second light emitting cell C2, a third light emitting cell D1 and a fourth light emitting cell C1 disposed on a substrate 21. A light emitting cell D2 is included. In addition, the light emitting diode includes a first electrode pad 37 and a second electrode pad 35, upper extension parts 37a, 37b, 37c, 37d and lower extension parts 35a, 35b, connection parts ( 35c), current blocking layers 31a, a first insulating layer 31b, a second insulating layer 31c, and a transparent electrode layer 33. In addition, each of the light emitting cells C1, C2, D1, and D2 includes a lower semiconductor layer 23a or 23b, an active layer 25, and an upper semiconductor layer 27, as shown in FIGS. 2 to 4 .

The substrate 21 is not particularly limited as long as it is a substrate suitable for growing a gallium nitride-based semiconductor layer. For example, it may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, an aluminum nitride substrate, or a silicon substrate. In particular, in this embodiment, the substrate 21 may be a patterned sapphire substrate (PSS).

The lower semiconductor layers 23a and 23b, the active layer 25 and the upper semiconductor layer 27 may be III-V series, particularly gallium nitride-based compound semiconductor layers. These semiconductor layers may include, for example, a nitride-based semiconductor such as (Al, Ga, In)N. The lower semiconductor layers 23a and 23b may include n-type impurities (eg, Si), and the upper semiconductor layer 27 may include p-type impurities (eg, Mg), but vice versa. It could be. The active layer 25 may have a multi-quantum well structure (MQW), and its composition ratio may be adjusted to emit light having a desired peak wavelength. The first to fourth light-emitting cells C1, C2, D1, and D2 may be formed by sequentially growing a lower semiconductor layer, an active layer, and an upper semiconductor layer on the substrate 21 and then patterning the semiconductor layers. . The semiconductor layers may be grown using, for example, metal organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor deposition.

Meanwhile, the first light emitting cell C1 and the second light emitting cell C2 are separated from the third light emitting cell D1 and the fourth light emitting cell D2 by the separation groove 30a, and also the first light emitting cell. (C1) and the third light emitting cell D1 are separated from the second light emitting cell C2 and the fourth light emitting cell D2 by the mesa separation groove 27a, respectively. That is, the first and second light emitting cells C1 and C2 are separated from each other by an isolation process of forming the separation groove 30a exposing the substrate 21 . In contrast, the first light emitting cell C1, the second light emitting cell C2, the third light emitting cell D1 and the fourth light emitting cell D2 have mesa separation grooves exposing the lower semiconductor layers 23a and 23b. It is formed by the mesa etching process forming (27a). Therefore, the first light emitting cell C1 and the second light emitting cell C2 share the first lower semiconductor layer 23a, and the third light emitting cell D1 and the fourth light emitting cell D2 share the second lower semiconductor layer 23a. Layer 23b is shared. In addition, the first lower semiconductor layer 23a and the second lower semiconductor layer 23b are spaced apart from each other by the separation groove 30a.

As can be seen with reference to FIG. 3 , other electrode parts other than the first electrode pad 37 and the second electrode pad 35 are not disposed in the mesa separation groove 27a, and the lower semiconductor layers 23a and 23b ) can be exposed.

The first light emitting cell C1 and the second light emitting cell C2 may have the same shape, and the third light emitting cell D1 and the fourth light emitting cell D2 may also have the same shape. However, as the second electrode pad 35 is disposed, the first light emitting cell C1 and the second light emitting cell C2 have slightly different shapes from the third light emitting cell D1 and the fourth light emitting cell D2. can be different. These light emitting cells (C1, C2, D1, D2) may have a generally elongated rectangular shape.

Meanwhile, the first electrode pad 37 is disposed near one edge 21a of the substrate 21, and the second electrode pad 35 is disposed near the other edge 21b opposite to the one edge. As shown in FIG. 1 , the first electrode pad 37 and the second electrode pad 35 may be disposed to face each other. The first electrode pad 37 and the second electrode pad 35 are disposed on the mesa separation groove 27a. Furthermore, the first electrode pad 37 may be formed over the first light emitting cell C1 and the second light emitting cell C2. The first electrode pad 37 and the second electrode pad 35 will be described later with reference to FIGS. 5 and 6 .

A transparent electrode layer 33 is disposed on each light emitting cell. The transparent electrode layer 33 is connected to the upper semiconductor layer 27 . The transparent electrode layer 33 is formed of a material having light transmission and electrical conductivity, and may be formed of, for example, a conductive oxide such as ITO, ZnO, or IZO or a light transmission metal layer such as Ni/Au. Since the transparent electrode layer 33 has a lower sheet resistance than the upper semiconductor layer 27, current is distributed over a wide area. In addition, the transparent electrode layer 33 makes an ohmic contact with the upper semiconductor layer 27 to input current to the upper semiconductor layer 27 .

The lower semiconductor layer 23a or 23b is exposed through the upper semiconductor layer 27 and the active layer 25 of each light emitting cell, and lower extension portions 35a or 35b are formed on the exposed lower semiconductor layer 23a or 23b. are placed The lower extension portions 35a and 35b are electrically connected to the lower semiconductor layers 23a and 23b.

The lower extension portion 35a is connected to the second electrode pad 35 and includes a straight area and a curved area. A curved area connects the straight area and the second electrode pad 35 . Lower extensions of the linear regions on the third light emitting cell D1 and the fourth light emitting cell D4 may be parallel to each other. Also, the lower extension part 35a may pass through the center of each of the light emitting cells D1 and D2.

Meanwhile, the lower extensions 35b disposed on the first light emitting cell C1 and the second light emitting cell C2 may include a straight area and be parallel to each other. Further, as best shown in FIGS. 1 and 4 , the lower extension 35b may be parallel to the straight region of the lower extension 35a.

Meanwhile, upper extension portions 37a, 37b, 37c, and 37d are disposed on the transparent electrode layer 33. The auxiliary upper extension part 37a and the main upper extension part 37a are disposed on the first and second light emitting cells C1 and C2, and the auxiliary upper extension part 37a is disposed on the third and fourth light emitting cells D1 and D2. An upper extension 37c and a main upper extension 37d are disposed.

The main upper extension 37b is arranged to surround the end and part of the side of the lower extension 35b. Accordingly, a portion of the main upper extension 37b is disposed outside the lower extension 35b, another portion is located inside the lower extension 35b, and another portion is disposed outside the lower extension 35b. It is disposed between the end of the substrate 21 and one edge 21a of the substrate 21 . Further, the main upper extension 37b has two ends and these ends are located inside and outside the lower extension 35b, respectively. Here, the inner side of the lower extension part 35b means the side of the mesa separation groove 27a with respect to the lower extension part 35b and an imaginary straight line extending therefrom, and the outer side means the side facing the inner side. The main upper extension 37b may have a symmetrical structure with respect to a straight line passing through the lower extension 35b.

The main upper extension portion 37b extends from one edge 21a side of the substrate 21 where the first electrode pad 37 is disposed to the other edge 21b side where the second electrode pad 35 is disposed. As shown in FIG. 1 , the distance between the main upper extension 37b and the lower extension 35b may not be constant, but may become closer and further along the direction of extension of the main upper extension 37b. The distance from the lower extension 35b to the main upper extension 37b is generally longer than the distance from the main upper extension 37b to the edge of the first conductivity type semiconductor layer 23 or to the mesa separation groove 27a. can However, the distance from the inner or outer end to the lower extension portion 35b is the distance from the outer end to the edge of the first conductive semiconductor layer 23 or the distance from the inner end to the mesa separation groove 27a. can be shorter Accordingly, the current can be evenly distributed while alleviating the concentration of the current at the corners of the first light emitting cell or the second light emitting cell.

Meanwhile, the auxiliary upper extension portion 37a connects the first electrode pad 37 and the main upper extension portion 37b. The auxiliary upper extension portion 37a may have a straight shape, and one end is connected to the first electrode pad 37 and the other end is connected to the main upper extension portion 37b. A connection point of one end of the auxiliary upper extension part 37a may be further away from the edge 21a of one side of the substrate 21 than the center of the first electrode pad 37 . Also, the connection point of the other end may be located inside the lower extension part 35b, and may be closer to one edge 21a of the substrate 21 than the end of the lower extension part 35b.

The main upper extension 37d is arranged to surround the end and part of the side of the lower extension 35a. Accordingly, a part of the main upper extension 37d is disposed outside the lower extension 35a, another part is located inside the lower extension 35a, and another part is disposed outside the lower extension 35a. It is disposed between the end of the separation groove (30a). Also, the main upper extension 37d has two ends, an inner end and an outer end, and these ends are located inside and outside the lower extension 35a, respectively. Here, the inner side of the lower extension part 35a means the side of the mesa separation groove 27a with respect to the lower extension part 35a and an imaginary straight line extending therefrom, and the outer side means the side facing the inner side.

The main upper extension portion 37d extends from the side of the separation groove 30a to the side of the other edge 21b of the substrate 21 on which the second electrode pad 35 is disposed. As shown in Fig. 1, the distance between the main upper extension 37d and the lower extension 35b may not be constant, but may be distant and approaching along the direction of extension of the main upper extension 37d.

The main upper extension 37d may have a substantially symmetrical structure with respect to the straight region of the lower extension 35b, but the outer end of the lower extension 35a is closer to the other edge 21b of the substrate 21 than the inner end. located closer to That is, as shown in FIG. 1, the area of the main upper extension 37d located outside the lower extension 35a is longer than the area located on the inside, and the curved area of the lower extension 35a can be bent along

Meanwhile, the auxiliary upper extension 37c may extend from the main upper extension 37d toward the lower extension 35b on the first light emitting cell C1. The auxiliary upper extension portion 37c may have a straight shape and may be parallel to the lower extension portion 35b. One end of the auxiliary upper extension 37c is connected to the main upper extension 37c, and the other end is connected to the connecting portion 35c.

Referring to FIGS. 1 and 4 , the connecting portion 35c connects the auxiliary upper extension portion 37c and the lower extension portion 35b. That is, the lower extension part 35b on the first light emitting cell C1 is connected to the auxiliary upper extension part 37c on the third light emitting cell D1 through the connection part 35c, and the upper part 37c on the second light emitting cell C2. The lower extension part 35b may be connected to the auxiliary upper extension part 37c on the fourth light emitting cell D2 through another connection part 35c. Accordingly, the first light emitting cell C1 may be connected in series to the third light emitting cell D1, and the second light emitting cell C2 may be connected to the fourth light emitting cell D2 in series. Meanwhile, the first and third light emitting cells C1 and D1 are connected in parallel to the second and fourth light emitting cells C2 and D2. Meanwhile, the connection part 35c is spaced apart from the third and fourth light emitting cells D1 and D2 by the insulating layer 31b.

The first electrode pad 37, the second electrode pad 35, the upper extension portions 37a, 37b, 37c, and 37d, the lower extension portions 35a, 35b, and the connection portion 35c are made of the same material and are the same. It may be formed together in a process, and may be formed in a multilayer structure of, for example, Cr/Al/Cr/Ni/Au. However, the present invention is not limited thereto, and each element may be formed in another process using different materials.

Meanwhile, the upper extension portions 37a, 37b, 37c, and 37d, the lower extension portions 35a, 35b, and the connection portion 35c are formed on an imaginary line passing through the first electrode pad 37 and the second electrode pad 35. may have a symmetrical structure. Furthermore, the light emitting diode according to the present embodiment may have a symmetrical structure with respect to an imaginary line passing through the first electrode pad 37 and the second electrode pad 35 . Accordingly, the current can be evenly distributed.

Referring back to FIGS. 1 to 4 , a current blocking layer 31a may be disposed below the upper extension portions 37a, 37b, 37c, and 37d. In addition, the current blocking layer 31a may be disposed below the first electrode pad 37 . The current blocking layer 31a is disposed between the transparent electrode layer 33 and the upper semiconductor layer 27 of the light emitting cells C1, C2, D1, and D4. Furthermore, the current blocking layer 31a may be connected to the insulating layer 31b positioned below the connection portion 35c.

The current blocking layer 31a is made of an insulating material and may be formed as a single layer or multiple layers. For example, the current blocking layer 130 may include SiOx or SiNx, and may include a distributed Bragg reflector in which insulating material layers having different refractive indices are stacked. The current blocking layer 31a prevents current from flowing directly from the upper extension portions 37a, 37b, 37c, and 37d to the light emitting cells C1, C2, D1, and D4, thereby preventing the light emitting cells C1 and C2 from flowing. , D1, D4) to spread the current over a wide area. The line width of the current blocking layer 31a may be larger than that of the upper extension portions 37a, 37b, 37c, and 37d. If the line width is too large, light emitted from the light emitting cells may be absorbed and light loss may occur. Accordingly, the line width of the current blocking layer 31a is preferably less than three times the line width of the upper extension portions 37a, 37b, 37c, and 37d.

In addition, the current blocking layer 31a positioned under the first electrode pad 37 insulates the first electrode pad 37 from the first lower semiconductor layer 23a. Furthermore, the current blocking layer 31a may also be interposed between the first electrode pad 37 and the first and second light emitting cells C1 and C2. In this case, the current blocking layer 31a is interposed between the transparent electrode layer 33 and the upper semiconductor layer 27 .

FIG. 5 is an enlarged plan view of a portion of the first electrode pad 37 of FIG. 1 .

Referring to FIG. 5 , a current blocking layer 31a having an area larger than that of the first electrode pad 37 is disposed under the first electrode pad 37 . The first electrode pad 37 is limitedly positioned on the current blocking layer 31a. The first electrode pad 37 is positioned on the mesa separation groove 27a and is disposed over the first light emitting cell C1 and the second light emitting cell C2. Accordingly, the current blocking layer 31a insulates the first electrode pad 37 and the first lower semiconductor layer 23a on the mesa separation groove 27a, and furthermore, the first and second light emitting cells C1, C2) is interposed between the transparent electrode layer 33 and the upper semiconductor layer 27. Meanwhile, a portion of the transparent electrode layer 33 is located below the first electrode pad 37 and has an opening 33a exposing the current blocking layer 31a. The transparent electrode layers 33 on the first light emitting cell C1 and the second light emitting cell C2 each have an opening 33a, and the openings 33a are symmetrical to each other with the mesa separation groove 27a interposed therebetween. can be formed as

The opening 33a may have a shape like a part of a donut. That is, the opening 33a may include a concave sidewall and a convex sidewall, and may include a flat sidewall connecting the concave sidewall and the convex sidewall. By forming the opening 33a in the transparent electrode layer 33, the adhesive force of the first electrode pad 37 is increased. In this embodiment, the formation of the opening 33a in the transparent electrode layer 33 is described, but the opening 31a may be formed in the current blocking layer 31a to expose the upper semiconductor layer 27 .

FIG. 6 is an enlarged plan view of the second electrode pad 35 of FIG. 1 .

Referring to FIG. 6 , the second electrode pad 35 is disposed in the mesa separation groove 27a and electrically connected to the second lower semiconductor layer 23b as described above. Meanwhile, the third light emitting cell D1 and the fourth light emitting cell D2 are positioned adjacent to the second electrode pad 35 .

The insulating layer 31c covers the side surfaces of the third light emitting cell D1 and the fourth light emitting cell D2. As shown, the insulating layer 31c may cover side surfaces of the third and fourth light emitting cells D1 and D2 except for portions where the lower extension 35a passes. When the wire is ball-bonded on the second electrode pad 35, the bonding material contacts the upper semiconductor layer 27 of the third light emitting cell D1 or the fourth light emitting cell D2. prevent short circuits from occurring.

The insulating layer 31c may be spaced apart from the transparent electrode layer 33, and thus, the area of the insulating layer 31c may be relatively small. Accordingly, light loss due to the insulating layer 31c can be reduced.

A light emitting diode according to an embodiment of the present invention may operate at a relatively high voltage by using light emitting cells connected in series. Accordingly, the overall driving current can be reduced. Furthermore, the light emitting cells may be connected in parallel and the current may be evenly distributed using the lower extension part and the upper extension part. In addition, the light emitting diode may be packaged through a conventional conventional process, and a wavelength conversion layer containing a phosphor may be disposed on the light emitting diode. Accordingly, a light emitting device emitting white light may be provided.

7 is a photograph showing a light emitting pattern of a light emitting diode according to an embodiment of the present invention. This light emitting pattern was photographed in a state in which the wire was bonded to the light emitting diode and packaged.

Referring to FIG. 7 , it can be seen that light is uniformly emitted over the entire area of the light emitting cells. In general, in a light emitting diode composed of a single light emitting cell, since it is difficult to evenly distribute current at the corner, less light is generated at the corner. However, in the light emitting diode according to the present embodiment, light is evenly emitted even to the corners of each light emitting cell.

Meanwhile, a package was fabricated using a light emitting diode having a chip size of 1430 μm × 760 μm, and the luminous efficiency of the package was measured. The luminous efficiency exceeded 210 lm/W.

Claims (20)

Board;
first to fourth light emitting cells disposed on the substrate;
a first electrode pad; and
Including a second electrode pad,
Each light emitting cell includes a lower semiconductor layer, an upper semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer,
The lower semiconductor layer includes a first lower semiconductor layer and a second lower semiconductor layer spaced apart from each other,
The first light-emitting cell and the second light-emitting cell share a first lower semiconductor layer,
The third light emitting cell and the fourth light emitting cell share a second lower semiconductor layer,
The first light emitting cell is connected in series to the third light emitting cell,
The second light emitting cell is connected in series to the fourth light emitting cell,
The first electrode pad is electrically connected to the upper semiconductor layer of the first light emitting cell and the second light emitting cell,
The second electrode pad is electrically connected to lower semiconductor layers of the third light emitting cell and the fourth light emitting cell,
The first lower semiconductor layer and the second lower semiconductor layer are separated by a separation groove exposing an upper surface of the substrate;
The first light-emitting cell and the second light-emitting cell, and the third light-emitting cell and the fourth light-emitting cell are separated by a mesa separation groove exposing a first lower semiconductor layer and a second lower semiconductor layer, respectively;
The light emitting diode further includes a transparent electrode layer disposed on the upper semiconductor layer of each light emitting cell and a current blocking layer disposed below the first electrode pad,
The first electrode pad is disposed on the mesa separation groove, and is disposed over the first light emitting cell and the second light emitting cell,
The transparent electrode layers are respectively disposed between the first and second light emitting cells and the first electrode pad,
A portion of the current blocking layer is disposed between the first light emitting cell and the second light emitting cell and the transparent electrode layer;
Each of the transparent electrode layers on the first light emitting cell and the second light emitting cell has an opening exposing the current blocking layer,
The first electrode pad contacts the current blocking layer through the opening. delete delete delete The method of claim 1,
The light emitting diode of claim 1 , wherein the current blocking layer has an area larger than that of the first electrode pad so that the first electrode pad is limited and disposed above the current blocking layer. delete The method of claim 1,
Upper extensions disposed on the transparent electrode layer on each light emitting cell and electrically connected to the transparent electrode layer; and
Further comprising current blocking layers disposed between the transparent electrode layers and the light emitting cells under the upper extension portions,
A width of the current blocking layers is less than three times the width of the upper extension portions. The method of claim 7,
Further comprising lower extensions connected to the lower semiconductor layer of each light emitting cell,
each lower extension comprises a straight region extending in the same direction;
The straight area of the lower extension of the first light emitting cell is parallel to the straight area of the lower extension of the third light emitting cell, and the straight area of the lower extension of the second light emitting cell is the straight area of the lower extension of the fourth light emitting cell. and parallel light emitting diodes. The method of claim 8,
Upper extensions disposed on the transparent electrode layers of the first light emitting cell and the second light emitting cell are electrically connected to a first electrode pad,
Lower extensions connected to the lower semiconductor layers of the third light emitting cell and the fourth light emitting cell are electrically connected to the second electrode pad. The method of claim 9,
Each upper extension includes a main upper extension having a shape surrounding a portion of the corresponding lower extension and a secondary upper extension protruding from the main upper extension. The method of claim 10,
The auxiliary upper extensions on the first light emitting cell and the second light emitting cell are arranged to connect the main upper extensions to the first electrode pad;
The auxiliary upper extensions on the third and fourth light-emitting cells connect the main upper extensions on the third and fourth light-emitting cells to lower extensions of the first and second light-emitting cells, respectively. A light emitting diode arranged to do so. The method of claim 11,
The auxiliary upper extensions on the first light emitting cell and the second light emitting cell are connected to the main upper extension closer to the mesa separation groove than the corresponding lower extension. The method of claim 11,
The light emitting diode further comprises connecting parts connecting the lower extensions of the first and second light emitting cells and the auxiliary upper extensions on the third and fourth light emitting cells, respectively. The method of claim 13,
The light emitting diode further comprises an insulating layer insulating the connection parts from the second lower semiconductor layer of the third light emitting cell and the fourth light emitting cell. The method of claim 8,
The lower extensions of the third light emitting cell and the fourth light emitting cell further include lower extensions of a curved area connecting the lower extensions of the straight area to the second electrode pad,
The second electrode pad is disposed on the second lower semiconductor layer exposed by the mesa separation groove. The method of claim 15
The light emitting diode further comprises an insulating layer covering side surfaces of the upper semiconductor layer and the active layer around the second electrode pad. The method of claim 16
The insulating layer covering the side surfaces of the upper semiconductor layer and the active layer is spaced apart from the transparent electrode layer of the light emitting diode. The method of claim 15
The first electrode pad and the second electrode pad are disposed to face each other,
The first electrode pad is disposed near one edge of the substrate, and the second electrode pad is disposed near the other edge opposite to the one edge of the substrate. The method of claim 18
The main upper extensions on the third light emitting cell and the fourth light emitting cell have an inner end disposed between the lower extension of the third light emitting cell and the lower extension of the fourth light emitting cell, and disposed outside the lower extension, respectively. has an outer end;
An outer end of the lower extension is disposed closer to the other edge than the inner end. The method according to any one of claims 1, 5, and 7 to 19,
A light emitting diode having a symmetrical structure with respect to a line passing through the first electrode pad and the second electrode pad.

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