KR20240027671A - Light emitting diode with high efficiency - Google Patents

Abstract

A light emitting diode having a plurality of light emitting cells is provided. This light emitting diode includes a semiconductor laminate including a lower semiconductor layer, an upper semiconductor layer, and an active layer disposed between the lower semiconductor layer and the upper semiconductor layer, and having a separation groove in the upper semiconductor layer, the active layer, and the lower semiconductor layer; a first electrode pad and an upper extension electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension electrically connected to the lower semiconductor layer; a connection part connecting the upper extension part and the lower extension part across the separation groove and having a width wider than the width of the upper extension part and the lower extension part; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer, wherein the first current blocking layer includes a plurality of dots spaced apart from each other, and the width of each dot is equal to the width of the lower extension portion. width, the width of the second current blocking layer is narrower than the width of the second electrode pad, and the shortest distance from the separation groove to the first current blocking layer is greater than the separation distance between the plurality of dots. It is characterized by

Description

High efficiency light emitting diode{LIGHT EMITTING DIODE WITH HIGH EFFICIENCY}

The present invention relates to light emitting diodes, and more particularly to high efficiency light emitting diodes.

Light-emitting diodes (LEDs) are solid-state light-emitting devices that convert electrical energy into light. Light-emitting diodes are widely used as light sources in backlight units, lighting devices, signals, and large displays. As the lighting LED market expands and its application range expands to high current density and high output fields, there is a need to improve the characteristics of light emitting diodes for stable operation when driving at high currents.

In general, increasing the current density applied to a light emitting diode increases the amount of light emitted from the light emitting diode. However, as the current density increases, a droop phenomenon occurs in which external quantum efficiency decreases. The droop phenomenon means that the rate of light loss increases as the current density increases, and it is an obstacle to increasing the luminous efficiency expressed in lm/W.

The problem to be solved by the present invention is to provide a light emitting diode suitable for providing a high efficiency light emitting device.

Another problem to be solved by the present invention is to provide a light emitting diode with improved droop phenomenon.

Another problem to be solved by the present invention is to provide a light emitting diode that improves disconnection defects in connection parts that electrically connect at least two light emitting cells.

According to one embodiment of the present invention, a substrate; Located on the substrate, comprising a lower semiconductor layer, an upper semiconductor layer, and an active layer disposed between the lower semiconductor layer and the upper semiconductor layer, and exposing the substrate through the upper semiconductor layer, the active layer, and the lower semiconductor layer. A semiconductor laminate having a separation groove; a first electrode pad and an upper extension electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension electrically connected to the lower semiconductor layer; a connection part connecting the upper extension part and the lower extension part across the separation groove and having a width wider than the width of the upper extension part and the lower extension part; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer, wherein the first current blocking layer includes a plurality of dots spaced apart from each other, and the width of each dot is equal to the width of the lower extension portion. width, the width of the second current blocking layer is narrower than the width of the second electrode pad, and the shortest distance from the separation groove to the first current blocking layer is greater than the separation distance between the plurality of dots. A characterized light emitting diode is provided.

By arranging a plurality of light emitting cells on a substrate, the light emitting cells can be connected in series or in parallel and used. By connecting light-emitting cells in series, the driving current of the light-emitting diode can be reduced, thereby reducing the current density and improving light-emitting efficiency. Additionally, by connecting the light emitting cells in parallel, the current input to the light emitting cells can be distributed evenly across the light emitting cells, thereby improving the droop phenomenon. In addition, the reliability of the light emitting diode can be increased by forming a thick connection part for connecting the light emitting cells in series or parallel. In addition, by adopting a current blocking layer with a wider width than the lower extension between the lower semiconductor layer and the lower extension, the current can be prevented from concentrating in a specific area and distributed evenly over a wide area of the light emitting cell. Accordingly, the droop phenomenon can be further improved.

1 is a plan view for explaining a light emitting diode according to an embodiment of the present invention.
Figure 2 is a cross-sectional view taken along line AA in Figure 1.
Figure 3 is a cross-sectional view taken along line BB in Figure 1.
Figure 4 is a cross-sectional view taken along line CC of Figure 1.
Figure 5 is a cross-sectional view taken along line DD in Figure 1.
FIG. 6A is an enlarged plan view of the connection part of FIG. 1 according to an embodiment, and FIG. 6B is a cross-sectional view taken along the cutting line EE of FIG. 6A.
FIG. 7A is an enlarged plan view of the connection part of FIG. 1 according to another embodiment, and FIG. 7B is a cross-sectional view taken along the cutting line E'-E' of FIG. 7A.
FIG. 8 is an enlarged plan view of the first electrode pad of FIG. 1.
Figure 9 is a cross-sectional view taken along the cutting line FF in Figure 8.
FIG. 10 is an enlarged plan view of the second electrode pad of FIG. 1.
Figure 11 is a cross-sectional view taken along the cutting line GG in Figure 10.
Figure 12 is a plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 13 is a plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 14 is a plan view for explaining a light emitting diode according to another embodiment of the present invention.
Figure 15 is a cross-sectional view showing various embodiments of the side shape of a light emitting diode according to another embodiment of the present invention.
Figure 16 shows a form in which a light emitting diode is mounted inside a package according to various embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments introduced below are provided as examples so that the idea of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. Also, in the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Additionally, when one component is described as being "on top of" or "on" another component, it means that each component is "directly on" or "directly on" the other component, as well as when each component is described as being "directly on" or "directly on" the other component. This also includes cases where another component is interposed. Like reference numerals refer to like elements throughout the specification.

A light emitting diode according to an embodiment of the present invention includes a substrate; Located on the substrate, comprising a lower semiconductor layer, an upper semiconductor layer, and an active layer disposed between the lower semiconductor layer and the upper semiconductor layer, and exposing the substrate through the upper semiconductor layer, the active layer, and the lower semiconductor layer. A semiconductor laminate having a separation groove; a first electrode pad and an upper extension electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension electrically connected to the lower semiconductor layer; a connection part connecting the upper extension part and the lower extension part across the separation groove and having a width wider than the width of the upper extension part and the lower extension part; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer, wherein the first current blocking layer includes a plurality of dots spaced apart from each other, and the width of each dot is equal to the width of the lower extension portion. width, the width of the second current blocking layer is narrower than the width of the second electrode pad, and the shortest distance from the separation groove to the first current blocking layer is greater than the separation distance between the plurality of dots. It is characterized by

Here, the length of the connection area where the connection part and the lower extension part connect to the lower semiconductor layer in the area between the separation groove and the current blocking layer is the length of the connection area where the lower extension part connects to the lower semiconductor layer between two neighboring dots. It may be larger than the length of the connection area to be connected.

The upper extension part is disposed to be spaced apart from the lower extension part, and an end of the lower extension part may be directly connected to the lower semiconductor layer.

The upper extension may be arranged to surround an end of the lower extension.

In this case, the inclined distance from the end of the lower extension to the upper extension is greater than the vertical distance from the end of the lower extension to the upper extension, wherein the vertical distance extends from the end of the lower extension to the lower part. It is the distance to the upper extension in a direction perpendicular to the unit, and the inclined distance means the distance from the end of the lower extension to the upper extension in a direction inclined with respect to the vertical direction.

The first and second current blocking layers may include a SiO2 layer or a distributed Bragg reflector layer.

In addition, the light emitting diode further includes a transparent electrode layer disposed on the upper semiconductor layer, and a portion of the transparent electrode layer is disposed between the upper semiconductor layer and the first electrode pad and between the upper semiconductor layer and the upper extension portion. It can be.

Additionally, the light emitting diode may further include a third current blocking layer disposed below the first electrode pad and between the upper semiconductor layer and the transparent electrode layer.

Here, the transparent electrode layer has an opening exposing the third current blocking layer, and the first electrode pad can contact the third current blocking layer through the opening. The third current blocking layer may have a larger area than the first electrode pad so that the first electrode pad is disposed limited to the upper part of the third current blocking layer.

The semiconductor laminate may include a plurality of light emitting cells defined by the separation groove or the mesa separation groove, and the plurality of light emitting cells may include the lower extension portion and the upper extension portion, respectively.

The connection portion is disposed on the separation groove and can electrically connect the upper extension portion and the lower extension portion of two adjacent light emitting cells.

The plurality of light emitting cells include first to fourth light emitting cells, and the lower semiconductor layer includes a first lower semiconductor layer and a second lower semiconductor layer spaced apart from each other by the separation groove, and the first light emitting cell and the second light-emitting cell shares a first lower semiconductor layer, the third light-emitting cell and the fourth light-emitting cell share a second lower semiconductor layer, and the first light-emitting cell emits the third light through the connection part. Cells are connected in series, and the second light-emitting cell may be connected in series to the fourth light-emitting cell through the connection part.

The lower extension portion of each light-emitting cell includes a straight region extending in the same direction, and the straight region of the lower extension portion of the first light-emitting cell is located on the same axis as the straight region of the lower extension portion of the third light-emitting cell. The straight area of the lower extension of the second light emitting cell may be located on the same axis as the straight area of the lower extension of the fourth light emitting cell.

The first electrode pad is disposed on the mesa separation groove and spans the first light-emitting cell and the second light-emitting cell, and the second electrode pad is disposed on the mesa separation groove and the second lower semiconductor layer. can be electrically connected to.

The upper extension portions disposed on the transparent electrode layers of the first and second light emitting cells are electrically connected to the first electrode pad and disposed on the lower semiconductor layers of the third and fourth light emitting cells. The lower extension parts may be electrically connected to the second electrode pad.

The upper extension of each light-emitting cell may include a main upper extension that has a shape that surrounds a portion of the corresponding lower extension and an auxiliary upper extension that protrudes from the main upper extension.

The auxiliary extensions on the first and second light emitting cells are arranged to electrically connect the main upper extension to the first electrode pad, and the auxiliary extensions on the third and fourth light emitting cells are disposed on the third light emitting cell and the fourth light emitting cell. The main upper extensions on the light-emitting cell and the fourth light-emitting cell may be arranged to electrically connect to lower extensions of the first light-emitting cell and the second light-emitting cell, respectively.

The first light emitting cell and the third light emitting cell may be connected in parallel with the second light emitting cell and the fourth light emitting cell through the first electrode pad and the second electrode pad.

Each light emitting cell may include a step on the side of the substrate, and the side of the substrate may be exposed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 1 is a plan view for explaining a light emitting diode according to an embodiment of the present invention, Figure 2 is a cross-sectional view taken along the cutting line A-A of Figure 1, Figure 3 is a cross-sectional view taken along the cutting line B-B of Figure 1, and Figure 4 is a cross-sectional view taken along the cutting line B-B of Figure 1. 1 is a cross-sectional view taken along the cutting line C-C, and FIG. 5 is a cross-sectional view taken along the cutting line D-D in FIG. FIG. 6A is an enlarged plan view of the connection part of FIG. 1 according to an embodiment, and FIG. 6B is a cross-sectional view taken along the cutting line E-E of FIG. 6A. In addition, FIG. 7A is an enlarged plan view of the connection part of FIG. 1 according to another embodiment, and FIG. 7B is a cross-sectional view taken along the cutting line E'-E' of FIG. 7A. Additionally, FIG. 8 is an enlarged plan view of the first electrode pad of FIG. 1, and FIG. 9 is a cross-sectional view taken along the cutting line F-F of FIG. 8. Additionally, FIG. 10 is an enlarged plan view of the second electrode pad of FIG. 1, and FIG. 11 is a cross-sectional view taken along the cutting line G-G of FIG. 10.

First, referring to FIG. 1, the light emitting diode according to this embodiment includes a first light emitting cell (C1), a second light emitting cell (C2), a third light emitting cell (D1), and a fourth light emitting cell (D1) disposed on the substrate 21. It may include a light emitting cell (D2). In addition, the light emitting diode includes a first electrode pad 37 and a second electrode pad 35, upper extension parts 37a, 37b, 37c, 37d, lower extension parts 35a, 35b, and connection parts ( 35c), current blocking layers 31a, 31b, 31c, insulating layers 31d, 31e, and a transparent electrode layer 33. Here, the current blocking layer 31c disposed below the lower extension parts 35a and 35b is the first current blocking layer, and the current blocking layer 31b disposed below the second electrode pad 35 is the second current blocking layer. , the current blocking layer 31a disposed under the first electrode pad 37 is the third current blocking layer, and the current blocking layer 31a disposed under the upper extensions 37a, 37b, 37c, and 37d is the third current blocking layer. 4 It may be referred to as a current blocking layer. Each light emitting cell (C1, C2, D1, D2) is a semiconductor laminate including a lower semiconductor layer (23a or 23b), an active layer 25, and an upper semiconductor layer 27, as well shown in FIGS. 2 to 5. may include.

The substrate 21 is not particularly limited as long as it is a suitable substrate for growing a gallium nitride-based semiconductor layer. For example, it may be a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, etc. In particular, in this embodiment, the substrate 21 may be a patterned sapphire substrate (PSS).

The lower semiconductor layers 23a and 23b, the active layer 25 and the upper semiconductor layer 27 may be a -V series, particularly a gallium nitride based compound semiconductor layer. These semiconductor layers may include, for example, a nitride-based semiconductor such as (Al, Ga, In)N. The lower semiconductor layers 23a and 23b may contain n-type impurities (e.g., Si), and the upper semiconductor layers 27 may contain p-type impurities (e.g., Mg), but vice versa. It may be. The active layer 25 may have a multi-quantum well structure (MQW), and its composition ratio may be adjusted to emit light of a desired peak wavelength. After sequentially growing the lower semiconductor layer, the active layer, and the upper semiconductor layer on the substrate 21, the first to fourth light emitting cells C1, C2, D1, and D2 can be formed by patterning the semiconductor layers. . The semiconductor layers may be grown using, for example, metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor deposition.

Meanwhile, the first light-emitting cell (C1) and the second light-emitting cell (C2) are separated from the third light-emitting cell (D1) and the fourth light-emitting cell (D2) by a separation groove (30a), and the first light-emitting cell (C2) (C1) and the third light emitting cell (D1) may be separated from the second light emitting cell (C2) and the fourth light emitting cell (D2) by a mesa separation groove (27a), respectively. That is, the first and second light emitting cells (C1, C2) can be separated from the third and fourth light emitting cells (D1, D2) by an isolation process that forms a separation groove (30a) exposing the substrate 21. there is. On the other hand, the first light emitting cell (C1), the second light emitting cell (C2), and the third light emitting cell (D1) and fourth light emitting cell (D2) have a mesa separation groove exposing the lower semiconductor layers (23a, 23b). It can be separated by a mesa etching process to form (27a). Accordingly, the first light-emitting cell (C1) and the second light-emitting cell (C2) share the first lower semiconductor layer (23a), and the third light-emitting cell (D1) and the fourth light-emitting cell (D2) share the second lower semiconductor layer. The floor 23b can be shared. Additionally, the first lower semiconductor layer 23a and the second lower semiconductor layer 23b may be spaced apart from each other by a separation groove 30a. That is, the semiconductor laminate can be separated into first to fourth light emitting cells C1, C2, D1, and D2 by the mesa separation groove 27a and the separation groove 30a.

As can be seen with reference to FIG. 4, no electrode parts other than the first electrode pad 37 and the second electrode pad 35 are disposed in the mesa separation groove 27a, and the lower semiconductor layers 23a and 23b ) may be exposed.

Based on the mesa separation groove 27a, the first light emitting cell (C1) and the second light emitting cell (C2) may have shapes that are symmetrical to each other, and the third light emitting cell (D1) and the fourth light emitting cell (D2) may also They can have shapes that are symmetrical to each other. However, as the second electrode pad 35 is disposed, the first light emitting cell (C1) and the second light emitting cell (C2) have a slightly different shape from the third light emitting cell (D1) and the fourth light emitting cell (D2). can be different. These light emitting cells (C1, C2, D1, D2) may generally have a long rectangular shape.

Meanwhile, the first electrode pad 37 may be disposed near one edge 21a of the substrate 21, and the second electrode pad 35 may be disposed near the other edge 21b opposite the one edge. As shown in FIG. 1, the first electrode pad 37 and the second electrode pad 35 may be disposed to face each other. The first electrode pad 37 and the second electrode pad 35 may be disposed on the mesa separation groove 27a. Furthermore, the first electrode pad 37 may be formed across the first light emitting cell C1 and the second light emitting cell C2. The first electrode pad 37 and the second electrode pad 35 will be described again later with reference to FIGS. 8 to 11 .

A transparent electrode layer 33 may be disposed on each light emitting cell. The transparent electrode layer 33 can be connected to the upper semiconductor layer 27. The transparent electrode layer 33 is formed of a material having light transparency and conductivity. For example, it may be formed of a conductive oxide such as ITO, ZnO, IZO, etc., or a light transparent metal layer such as Ni/Au. Since the transparent electrode layer 33 has a lower sheet resistance than the upper semiconductor layer 27, current can be distributed over a wide area. Additionally, the transparent electrode layer 33 can make ohmic contact with the upper semiconductor layer 27 to input current into the upper semiconductor layer 27.

The lower semiconductor layers 23a and 23b are exposed through etching of the upper semiconductor layer 27 and the active layer 25 of each light-emitting cell, and lower extensions 35a and 35b are formed on the exposed lower semiconductor layers 23a and 23b. ) can be placed. The lower extensions 35a and 35b may be electrically connected to the lower semiconductor layers 23a and 23b.

The lower extension parts 35a disposed in the first light-emitting cell C1 and the second light-emitting cell C2 include straight areas and may be parallel to each other. Furthermore, as shown in FIGS. 1 and 5, the lower extension portion 35a of the first light emitting cell C1 is located on the same axis as the straight area of the lower extension portion 35b of the third light emitting cell D1. can do.

Meanwhile, the lower extension portions 35b disposed in the third light emitting cell D1 and the fourth light emitting cell D2 are connected to the second electrode pad 35 and may include a straight region and a curved region. The curved area may connect the straight area and the second electrode pad 35. Lower extension portions of the straight areas on the third light emitting cell D1 and fourth light emitting cell D2 may be parallel to each other. Additionally, the lower extension portion 35b may pass through the center of each light emitting cell D1 and D2.

Upper extension parts 37a, 37b, 37c, and 37d may be disposed on the transparent electrode layer 33. An auxiliary upper extension part 37a and a main upper extension part 37b are disposed on the first and second light emitting cells C1 and C2, and an auxiliary upper extension part 37b is disposed on the third and fourth light emitting cells D1 and D2. An upper extension portion 37c and a main upper extension portion 37d may be disposed.

The main upper extension portion 37b disposed in the first light emitting cell C1 and the second light emitting cell C2 may be disposed to surround an end and a portion of the side of the lower extension portion 35a. Accordingly, a part of the main upper extension 37b is located outside the lower extension 35a, another part is located inside the lower extension 35a, and another part is located inside the lower extension 35a. It may be disposed between the end of and one edge 21a of the substrate 21. Additionally, the main upper extension 37b has two ends and these ends may be located inside and outside the lower extension 35a, respectively. Here, the inside of the lower extension portion 35a refers to the side of the mesa separation groove 27a with respect to the lower extension portion 35a and the virtual straight line extending it, and the outside refers to the side opposite to the inside. The main upper extension part 37b may have a symmetrical structure with respect to a straight line passing through the lower extension part 35a.

The main upper extension portion 37b disposed in the first light emitting cell C1 and the second light emitting cell C2 extends from one edge 21a of the substrate 21 on which the first electrode pad 37 is disposed. It may extend toward the other edge 21b where the electrode pad 35 is disposed. As shown in FIG. 1, the distance between the main upper extension part 37b and the lower extension part 35a may not be constant, and may move away and then become closer along the extension direction of the main upper extension part 37b. The distance from the lower extension 35a to the main upper extension 37b is generally greater than the distance from the main upper extension 37b to the edge of the first conductivity type semiconductor layer 23 or to the mesa separation groove 27a. You can. However, the distance from the inner end or outer end to the lower extension portion 35b is the distance from the outer end to the edge of the first conductive semiconductor layer 23 or the distance from the inner end to the mesa separation groove 27a. It can be shorter. Accordingly, the current can be distributed evenly while reducing the concentration of current at the bottom edge of the first or second light emitting cell.

Meanwhile, the auxiliary upper extension portion 37a disposed in the first light emitting cell C1 and the second light emitting cell C2 may connect the first electrode pad 37 and the main upper extension portion 37b. The auxiliary upper extension 37a may have a straight shape, and one end may be connected to the first electrode pad 37 and the other end may be connected to the main upper extension 37b. The point where one end of the auxiliary upper extension 37a is connected to the first electrode pad 37 may be further away from one edge 21a of the substrate 21 than the center of the first electrode pad 37. Additionally, the connection point of the other end may be located inside the lower extension part 35b and may be closer to one edge 21a of the substrate 21 than the end of the lower extension part 35b.

The main upper extension portion 37d disposed in the third light emitting cell D1 and fourth light emitting cell D2 is disposed to surround an end portion and a portion of the side surface of the lower extension portion 35b. Accordingly, a part of the main upper extension 37d is disposed on the outside of the lower extension 35b, another part is disposed on the inside of the lower extension 35b, and another part is disposed on the inside of the lower extension 35b. It may be disposed between the end of and the separation groove (30a). Additionally, the main upper extension 37d has two ends, namely an inner end and an outer end, and these ends may be located inside and outside the lower extension 35b, respectively. Here, the inside of the lower extension portion 35b refers to the side of the mesa separation groove 27a with respect to the lower extension portion 35b and the imaginary straight line extending from it, and the outside refers to the side opposite to the inside.

The main upper extension portion 37d may extend from the separation groove 30a side to the other edge 21b of the substrate 21 on which the second electrode pad 35 is disposed. As shown in FIG. 1, the distance between the main upper extension part 37d and the lower extension part 35b may not be constant, and may move away and then become closer along the extension direction of the main upper extension part 37d.

The main upper extension 37d may have a generally symmetrical structure with respect to the straight area of the lower extension 35b, but the outer end of the lower extension 35b is closer to the other edge 21b of the substrate 21 than the inner end. It can be located closer to . That is, as shown in FIG. 1, the area of the main upper extension 37d located on the outside of the lower extension 35b is longer than the area located on the inside, and the curved area of the lower extension 35b is It can bend accordingly.

Meanwhile, the auxiliary upper extension portion 37c disposed in the third light emitting cell D1 and the fourth light emitting cell D2 is connected to the first light emitting cell C1 and the second light emitting cell C2 from the main upper extension portion 37d. ) may extend toward the lower extension portion 35a. The auxiliary upper extension part 37c may have a straight shape and may be located on the same axis as the lower extension part 35a. One end of the auxiliary upper extension part 37c may be connected to the main upper extension part 37d, and the other end may be connected to the connection part 35c.

The distance between the ends of the lower extensions 35a and 35b and the main upper extensions 37b and 37d surrounding them may not be constant. That is, the upper extension parts 37b and 37d surrounding the ends of the lower extension parts 35a and 35b may not have a semicircular shape with a constant radius. Referring to FIG. 1, the inclined distance d2 may be greater than the vertical distance d1 between the ends of the lower extensions 35a and 35b and the main upper extensions 37b and 37d. Here, the vertical distance d1 refers to the distance from the ends of the lower extensions 35a and 35b to the main upper extensions 37b and 37d in a direction perpendicular to the lower extensions 35a and 35b. Additionally, the inclined distance d2 refers to the distance from the ends of the lower extensions 35a and 35b to the main upper extensions 37b and 37d in a direction inclined with respect to the vertical direction. By making the inclined distance d2 larger than the vertical distance d1, the main upper extension parts 37b and 37d can be arranged closer to the upper edge of each light emitting cell. Since the main upper extensions 37b and 37d are formed closer to the upper edge of the light emitting cell, current can be smoothly distributed up to the upper edge of the light emitting cell.

Referring to Figures 1 and 5, the connection part 35c may connect the auxiliary upper extension part 37c and the lower extension part 35a. That is, the lower extension portion 35a on the first light emitting cell (C1) is connected to the auxiliary upper extension portion (37c) on the third light emitting cell (D1) through the connecting portion (35c), and the lower extension portion (35a) on the first light emitting cell (C1) is connected to the auxiliary upper extension portion (37c) on the third light emitting cell (D1) through the connection portion (35c). The lower extension part 35a may be connected to the auxiliary upper extension part 37c on the fourth light emitting cell D2 through another connection part 35c. Accordingly, the first light emitting cell (C1) can be connected in series to the third light emitting cell (D1), and the second light emitting cell (C2) can be connected in series to the fourth light emitting cell (D2). Meanwhile, the first and third light emitting cells C1 and D1 may be connected in parallel to the second and fourth light emitting cells C2 and D2.

FIG. 6A is an enlarged plan view of the connection part of FIG. 1 according to one embodiment, and FIG. 6B is a cross-sectional view taken along line E-E of FIG. 6A.

The connection portion 35c is for electrically connecting the two light emitting cells C1 and D1 spaced apart by the separation groove 30a. As mentioned above, the connection portion 35c is provided at one end of the lower extension portion on the first light emitting cell C1 ( 35a), and the other end may be connected to the auxiliary upper extension 37c on the third light emitting cell D1. Referring to FIG. 6A, the width w1 of the connecting portion 35c may be larger than the width w2 of the lower extension portion 35a. In addition, the first current blocking layer 31c may not be disposed under the connection portion 35c and the lower extension portion 35a connected to the connection portion 35c on the first light emitting cell C1, and accordingly, the connection portion ( The lower extension portion 35a connected to 35c) and the connecting portion 35c may be directly connected to the lower semiconductor layer 23a. In this way, the connection portion 35c having a relatively thick width w1 and the lower extension portion 35a connected to the connection portion 35c are directly connected to the lower semiconductor layer 23a, thereby forming the main upper extension portion 37b. Horizontal distribution of current can be efficiently achieved in the outer portion of the first light emitting cell C1 where no is formed. Additionally, by forming the width w1 of the connection portion 35c to be relatively thick, the risk of disconnection of the connection portion 35c can be reduced and the reliability of the light emitting diode can be increased.

Also, referring to FIGS. 6A and 6B, the first current blocking layer 31c may be disposed between the lower extension portion 35a and the lower semiconductor layer 23a in the form of a plurality of dots. The width of the first current blocking layer 31c may be larger than the width of the lower extension portion 35a, and accordingly, the lower extension portion 35a may be directly connected to the lower semiconductor layer 23a only between each dot. there is. That is, the distance at which the lower extension part 35a is connected to the lower semiconductor layer 23a can be determined according to the separation distance d1 between each dot.

A lower extension connected to the connection portion 35c and the connection portion 35c between the first current blocking layer 31c and the separation groove 30a, that is, between the last dot of the first current blocking layer 31c and the separation groove 30a. The distance d2 at which the portion 35a is connected to the lower semiconductor layer 23a may be greater than the separation distance d1 between each dot of the first current blocking layer 31c. That is, between the first current blocking layer 31c and the separation groove 30a, the area where the connection portion 35c and the lower extension portion 35a connected to the connection portion 35c are connected to the lower semiconductor layer 23a are each The area between the dots of the lower extension portion 35a may be larger than the area connected to the lower semiconductor layer 23a, and thus the resistance may be reduced. Through this, the current can be smoothly distributed to the outer shell of the first light emitting cell (C1). That is, the upper extension portion 37b may not be formed to the outer edge of the first light emitting cell C1, and accordingly, the distance d3 between the end of the upper extension portion 37b and the connection portion 35c may be relatively large. there is. In this case, the current may not reach the outer shell of the first light emitting cell (C1), but the separation distance (d2) is increased so that the connection portion (35c) and the lower extension portion (35a) connected to the connection portion (35c) are connected to the lower semiconductor. The resistance value can be reduced by increasing the area connected to the layer 23a, and thus the current can be smoothly distributed in the outer region of the first light emitting cell C1.

The insulating layer 31d located below the connection portion 35c is formed on some sides of the lower semiconductor layer 23a of the first light-emitting cell C1, the lower semiconductor layer 23b of the third light-emitting cell D1, and the active layer ( 25), it may extend to the side of the upper semiconductor layer 27 and the upper surface of the upper semiconductor layer 27.

FIG. 7A is an enlarged plan view of the connection part of FIG. 1 according to another embodiment, and FIG. 7B is a cross-sectional view taken along the cutting line E'-E' of FIG. 7A. Compared to FIG. 6, most of the configurations of FIG. 7 are the same, but there is a slight difference in the shapes of the insulating layer 31d and the upper extension portion 37b. Accordingly, the area where the connection portion 35c is connected to the lower semiconductor layer 23a may vary. Hereinafter, the description of the same configuration will be omitted and the description will focus on the differences.

Referring to FIGS. 7A and 7B, compared to the embodiment of FIG. 6, the insulating layer 31d extends further toward the first light emitting cell C1 to form the lower semiconductor layer 23a of the first light emitting cell C1. ) and a portion of the upper surface of the lower semiconductor layer 23a. In this case, between the first current blocking layer 31c and the separation groove 30a, the distance ( d4) may be reduced compared to the embodiment of FIG. 6. That is, compared to the embodiment of FIG. 6, between the first current blocking layer 31c and the separation groove 30a, the connection portion 35c and the lower extension portion 35a connected to the connection portion 35c are lower semiconductor layer ( The area connected to 23a) is reduced, so the current density can be increased. However, the connection distance d4 may still be greater than the separation distance d1 between the plurality of dots of the first current blocking layer 31c. Alternatively, the connection distance d4 may be smaller than the separation distance d1 between the plurality of dots of the first current blocking layer 31c.

Additionally, referring to FIG. 7A, the distance d5 between the end of the upper extension portion 37b and the connection portion 35c may be reduced compared to the embodiment of FIG. 6. That is, the upper extension part 37c extends further in the direction of the connection part 35c, so that the distance d5 between the end of the upper extension part 37c and the connection part 35c can be reduced compared to the embodiment of FIG. 6. . In the embodiment of FIG. 7, between the first current blocking layer 31c and the separation groove 30a, the connection portion 35c and the lower extension portion 35a connected to the connection portion 35c are separated from the lower semiconductor layer 23a. In response to the decrease in the connected area, the distance (d5) between the end of the upper extension part (37b) and the connection part (35c) with a relatively wide width (w2) is reduced, so that the current flows horizontally to the outer edge of the first light emitting cell (C1). This is to facilitate dispersion.

Referring again to FIGS. 1 to 5, the first electrode pad 37, the second electrode pad 35, the upper extensions 37a, 37b, 37c, 37d, the lower extensions 35a, 35b, and the connection portion. (35c) can be formed together in the same process using the same materials, and can be formed, for example, in a multilayer structure of Cr/Al/Cr/Ni/Au. However, the present invention is not limited to this, and each element may be formed in a different process using different materials.

Meanwhile, the upper extensions 37a, 37b, 37c, and 37d, the lower extensions 35a, 35b, and the connection portion 35c are located on an imaginary line passing through the first electrode pad 37 and the second electrode pad 35. It may have a symmetrical structure. Furthermore, the light emitting diode according to this embodiment may have a symmetrical structure with respect to an imaginary line passing through the first electrode pad 37 and the second electrode pad 35. Accordingly, the current can be distributed evenly.

A fourth current blocking layer 31a may be disposed below the upper extensions 37a, 37b, 37c, and 37d. Additionally, the third current blocking layer 31a may be disposed below the first electrode pad 37. The third and fourth current blocking layers 31a are disposed between the transparent electrode layer 33 and the upper semiconductor layer 27 of the light emitting cells C1, C2, D1, and D2. Furthermore, the fourth current blocking layer 31a may be connected to the insulating layer 31d located below the connection portion 35c.

The third and fourth current blocking layers 31a are made of an insulating material and may be formed as a single layer or multiple layers. For example, the third and fourth current blocking layers 31a may include SiOx or SiNx, and may also include a distributed Bragg reflector (DBR) in which insulating material layers with different refractive indices are stacked. The fourth current blocking layer 31a prevents the current injected into the upper extensions 37a, 37b, 37c, and 37d from being concentrated only around the upper extensions 37a, 37b, 37c, and 37d, thereby preventing the light emitting cells ( Current can be distributed over a wide area (C1, C2, D1, D2). The line width of the fourth current blocking layer 31a disposed below the upper extension parts 37a, 37b, 37c, and 37d may be larger than the line width of the upper extension parts 37a, 37b, 37c, and 37d. However, if the line width is too large, light emitted from the light-emitting cells may be absorbed, causing light loss. Accordingly, the line width of the fourth current blocking layer 31a may be less than three times the line width of the upper extension portions 37a, 37b, 37c, and 37d.

Additionally, the third current blocking layer 31a located below the first electrode pad 37 may insulate the first electrode pad 37 from the first lower semiconductor layer 23a. Furthermore, the third current blocking layer 31a may be interposed between the first electrode pad 37 and the first and second light emitting cells C1 and C2. In this case, the third current blocking layer 31a may be interposed between the transparent electrode layer 33 and the upper semiconductor layer 27.

FIG. 8 is an enlarged plan view of the first electrode pad 37 of FIG. 1, and FIG. 9 is a cross-sectional view taken along the cutting line F-F of FIG. 8.

Referring to FIGS. 8 and 9 , a third current blocking layer 31a having a larger area than the first electrode pad 37 is disposed below the first electrode pad 37 . The first electrode pad 37 may be located limited to the upper part of the third current blocking layer 31a. The first electrode pad 37 is located on the mesa separation groove 27a and may be disposed across the first light emitting cell C1 and the second light emitting cell C2. Accordingly, the third current blocking layer 31a can insulate the first electrode pad 37 and the first lower semiconductor layer 23a on the mesa separation groove 27a. Additionally, the third current blocking layer 31a may be interposed between the transparent electrode layer 33 and the upper semiconductor layer 27 on the first and second light emitting cells C1 and C2. Meanwhile, a portion of the transparent electrode layer 33 is located between the first electrode pad 37 and the third current blocking layer 31a and may include an opening 33a exposing the third current blocking layer 31a. there is. The transparent electrode layers 33 on the first light emitting cell (C1) and the second light emitting cell (C2) each have an opening (33a), and the openings (33a) are symmetrical to each other with the mesa separation groove (27a) interposed therebetween. can be formed.

The opening 33a may have a shape like a portion of a donut. That is, the opening 33a may include a concave side wall and a convex side wall, and may include a flat side wall connecting the concave side wall and the convex side wall. By forming the opening 33a in the transparent electrode layer 33, the adhesive force of the first electrode pad 37 can be increased. However, the shape of the opening 33a is not limited to this and can be modified into various shapes within a target range that can increase the adhesive force of the first electrode pad 37. Also, in this embodiment, the opening 33a is formed in the transparent electrode layer 33, but the opening may be formed in the third current blocking layer 31a to expose the upper semiconductor layer 27.

FIG. 10 is an enlarged plan view of the second electrode pad portion of FIG. 1, and FIG. 11 is a cross-sectional view taken along the cutting line G-G of FIG. 10.

Referring to FIGS. 10 and 11 , the second electrode pad 35 may be disposed in the mesa separation groove 27a and electrically connected to the second lower semiconductor layer 23b, as described above. Meanwhile, the third light emitting cell D1 and the fourth light emitting cell D2 may be located adjacent to the second electrode pad 35.

A second current blocking layer 31b may be disposed below the second electrode pad 35. The second current blocking layer 31b is disposed between the second electrode pad 35 and the second lower semiconductor layer 23b to smooth horizontal distribution of the current injected into the second lower semiconductor layer 23b. there is. The area of the second current blocking layer 31b may be smaller than that of the second electrode pad 35. That is, the horizontal and vertical widths of the second current blocking layer 31b are smaller than those of the second electrode pad 35, and therefore the second current blocking layer 31b is below a portion of the second electrode pad 35. It can be located limited to . For example, the area of the second current blocking layer 31b may be limited to 90% or less of the area of the second electrode pad 35. When the area of the second current blocking layer 31b exceeds 90% of the area of the second electrode pad 35, the forward voltage Vf may increase. Therefore, by setting the area of the second current blocking layer 31b to 90% or less of the area of the second electrode pad 35, high luminous efficiency can be achieved without increasing the forward voltage. The second current blocking layer 31b is made of the same insulating material as the third and fourth current blocking layers 31a, and may be formed as a single layer or multiple layers. For example, the second current blocking layer 31b may include SiOx or SiNx, and may also include a distributed Bragg reflector (DBR) in which insulating material layers with different refractive indices are alternately stacked.

The insulating layer 31e may cover the side surfaces of the third light emitting cell D1 and the fourth light emitting cell D2 near the second electrode pad 35. As shown, the insulating layer 31e may cover the side surfaces of the third and fourth light emitting cells D1 and D2 except for the portion where the lower extension portion 35a passes. When the wire is ball-bonded on the second electrode pad 35, the insulating layer 31e is short-circuited when the wire contacts the upper semiconductor layer 27 of the third light-emitting cell (D1) or the fourth light-emitting cell (D2). This can be prevented from occurring.

The insulating layer 31e may be spaced apart from the transparent electrode layer 33, and therefore, the area of the insulating layer 31e may be formed to be relatively very small. Accordingly, light loss due to the insulating layer 31e can be reduced.

Referring again to FIGS. 1, 3, and 5, first current blocking layers 31c may be disposed under the lower extension portions 35a and 35b. As shown, the first current blocking layer 31c disposed below each of the lower extensions 35a and 35b may have a plurality of dots spaced apart from each other rather than one continuous line. That is, as shown in FIG. 1, the first current blocking layer 31c may include a plurality of dots spaced apart from each other. Each dot is disposed between the lower extensions 35a and 35b and the lower semiconductor layers 23a and 23b. Here, the width of the first current blocking layer 31c, that is, each dot, is larger than the width of the lower extension parts 35a and 35b. Therefore, the lower extensions 35a, 35b and the lower semiconductor layers 23a, 23b are not directly connected in the portion where the first current blocking layer 31c is interposed, and the lower extensions (35a, 35b) are not directly connected to each other in the area between each dot. 35a, 35b) contacts the lower semiconductor layers 23a, 23b. Additionally, the plurality of dots may be arranged to be spaced apart from each other at equal intervals, or may be arranged to be spaced apart from each other at different intervals.

By disposing the first current blocking layer 31c between the lower extensions 35a and 35b and the lower semiconductor layers 23a and 23b, the current is prevented from concentrating near the lower extensions 35a and 35b, thereby preventing the current from being concentrated near the lower extensions 35a and 35b. It can help with horizontal distribution. By distributing the current widely in the horizontal direction in the semiconductor stack, luminous efficiency can be increased. In particular, the line width of the first current blocking layers 31c is made larger than that of the lower extensions 35a and 35b, so that in the portion where the first current blocking layers 31c are interposed, the lower extensions 35a and 35b ) and the lower semiconductor layers 23a and 23b can be blocked. While the line width of the first current blocking layers 31c is made smaller than that of the lower extensions 35a and 35b, the line width of the first current blocking layers 31c is made smaller than that of the lower extensions 35a and 35b. By making it larger and arranging it in the form of dots, the current can be further dispersed. .

However, the first current blocking layers 31c may not be disposed at the ends of the lower extension parts 35a and 35b. That is, the ends of the lower extensions 35a and 35b may be directly connected to the lower semiconductor layers 23a and 23b. Here, direct connection means contact between the ends and the lower semiconductor layers 23a and 23b without any other material (eg, a current blocking layer) intervening. Referring to FIG. 1, the upper extension parts 37b and 37d have a structure surrounding the ends of the lower extension parts 35a and 35b. At this time, if the first current blocking layers 31c are disposed at the ends of the lower extensions 35a and 35b, the lower extensions 35a and 35b are directly electrically connected to the lower semiconductor layers 23a and 23b at the ends. Connection may not occur, and thus current distribution may not be smoothly achieved near the ends of the lower extension parts 35a and 35b.

The number of dots of the first current blocking layer 31c may be determined in various ways depending on the relative lengths of the lower extension parts 35a and 35b. For example, in FIG. 1 , five first current blocking layers 31c are arranged to be spaced apart from each other between the lower extension 35a and the first lower semiconductor layer 23a. Additionally, six first current blocking layers 31c are arranged to be spaced apart from each other between the lower extension portion 35b and the second lower semiconductor layer 23b. This includes a curved area for connecting the lower extension portions 35b on the third and fifth light emitting cells D1 and D2 with the second electrode pad 35, so that the relative lengths of the first and second light emitting cells C1 and C2 are This is because it is longer than the lower extension portion 35a of the top. The separation distance between the plurality of first current blocking layers 31c may be the same or different from each other. However, the number of the plurality of first current blocking layers 31c shown in FIG. 1 is only an example for convenience of explanation and should not be understood as a limitation of the embodiment.

12 to 14 are plan views for explaining a light emitting diode according to another embodiment of the present invention. 12 to 14, the shape of the first electrode pad 37, the second electrode pad 35, the upper extension portions, and the lower extension portions, and the number of light emitting cells are somewhat different from the light emitting diodes disclosed in Fig. 1. There are differences, but most of the rest of the configuration is the same. Therefore, description of the same configuration will be omitted and description will focus on the differences.

Figure 12 is a plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 12, the light emitting diode according to this embodiment includes first to third light emitting cells (C1, C2, C3) and fourth to sixth light emitting cells (D1, D2, D3) disposed on the substrate 21. ) and the seventh to ninth light emitting cells (E1, E2, E3). In addition, the light emitting diode includes a first electrode pad 37 and a second electrode pad 35, upper extensions 37a, 37b, 37c, 37d, 37e, 37f, and lower extensions 35a, 35b, 35d, 35e).

The first to third light emitting cells C1, C2, and C3 may be separated from the fourth to sixth light emitting cells D1, D2, and D3 by a separation groove 30a. Additionally, the fourth to sixth light emitting cells D1, D2, and D3 may be separated from the seventh to ninth light emitting cells E1, E2, and E3 by a separation groove 30b. That is, the first lower semiconductor layer 23a and the second lower semiconductor layer 23b are separated from each other by the separation groove 30a, and the second lower semiconductor layer 23b and the third lower semiconductor layer 23c are separated from each other by the separation groove 30a. It can be separated by a groove (30b). Accordingly, the first light-emitting cell (C1), the second light-emitting cell (C2), and the third light-emitting cell (C3) share the first lower semiconductor layer (23a), and the fourth light-emitting cell (D1) and the fifth light-emitting cell (D1) share the first lower semiconductor layer (23a). The cell D2 and the sixth light emitting cell D3 may share the second lower semiconductor layer 23b. Additionally, the seventh light emitting cell (E1), the eighth light emitting cell (E2), and the ninth light emitting cell (E3) may share the third lower semiconductor layer (23c). The separation grooves 30a and 30b are formed through an isolation process, and the substrate 21 may be exposed through the separation grooves 30a and 30b. On the other hand, the first light emitting cell (C1) and the second light emitting cell (C2), the fourth light emitting cell (D1) and the fifth light emitting cell (D2), and the seventh light emitting cell (E1) and the eighth light emitting cell (E2) ) can be separated from each other by a mesa etching process to form a mesa separation groove 27a exposing the lower semiconductor layers 23a, 23b, and 23c. In addition, the second light emitting cell (C2) and the third light emitting cell (C3), the fifth light emitting cell (D2) and the sixth light emitting cell (D3), and the eighth light emitting cell (E2) and the ninth light emitting cell (E3) The lower semiconductor layers 23a, 23b, and 23c may be separated by a mesa etching process to form a mesa separation groove 27b exposing the lower semiconductor layers 23a, 23b, and 23c. That is, the semiconductor laminate including the lower semiconductor layers 23a, 23b, and 23c, the active layer 25, and the upper semiconductor layer 27 is divided into the first to first to fourth layers by the mesa separation groove 27a and the separation grooves 30a and 30b. It is separated into ninth light emitting cells (C1, C2, C3, D1, D2, D3, E1, E2, E3).

The first light emitting cell C1 and the third light emitting cell C3 may have a shape that is symmetrical with respect to an imaginary line connecting the first electrode pad 37 and the second electrode pad 35. Each of the fourth to sixth light emitting cells D1, D2, and D3 may have the same shape. The shape of the fourth to sixth light emitting cells D1, D2, and D3 may be the same as that of the first light emitting cell C1 except for the auxiliary upper extension portion 37a. Additionally, the seventh light emitting cell E1 and the ninth light emitting cell E3 may have shapes that are symmetrical to each other based on an imaginary line connecting the first electrode pad 37 and the second electrode pad 35.

Here, the second light emitting cell (C2) in which the first electrode pad 37 is formed and the eighth light emitting cell (E2) related to the formation of the second electrode pad 35 have a relatively large difference in shape from other light emitting cells. has The first electrode pad 37 may be disposed near one edge 21a of the substrate 21, and the second electrode pad 35 may be disposed near the other edge 21b opposite the one edge. As shown in FIG. 12, the first electrode pad 37 and the second electrode pad 35 may be disposed to face each other.

The first electrode pad 37 may be formed on the second light emitting cell C2. A third current blocking layer 31a may be located below the first electrode pad 37. Specifically, the third current blocking layer 31a may be interposed between the transparent electrode layer 33 and the upper semiconductor layer 27 below the first electrode pad 37. The width of the third current blocking layer 31a may be larger than the width of the first electrode pad 37, and accordingly, the third current blocking layer 31a connects the first electrode pad 37 to the first lower semiconductor layer. It can be insulated from (23a). A portion of the transparent electrode layer 33 is located below the first electrode pad 37 and may include an opening 33a exposing the third current blocking layer 31a. The opening 33a may have a circular shape. By forming the opening 33a in the transparent electrode layer 33, the adhesive force of the first electrode pad 37 can be increased. However, the shape of the opening 33a is not limited to a circular shape and may include various shapes within a target range that can increase the adhesive force of the first electrode pad 37.

The second electrode pad 35 may be disposed on the mesa groove 27c. That is, to form the second electrode pad 35, a portion of the lower end of the eighth light emitting cell E2 near the other edge 21b may be mesa-etched to form the mesa groove 27c. The second electrode pad 35 may be disposed in the mesa separation groove 27c and electrically connected to the second lower semiconductor layer 23c.

A second current blocking layer 31b may be disposed below the second electrode pad 35. The second current blocking layer 31b is disposed between the second electrode pad 35 and the third lower semiconductor layer 23c to smoothly horizontally distribute the current injected into the third lower semiconductor layer 23c. there is. The area of the second current blocking layer 31b may be smaller than that of the second electrode pad 35. That is, the horizontal and vertical widths of the second current blocking layer 31b are smaller than those of the second electrode pad 35, and therefore, it may be located in a partial area of the second electrode pad 35. For example, the area of the second current blocking layer 31b may be limited to 90% or less of the area of the second electrode pad 35.

The insulating layer 31e may cover the side of the mesa groove 27c where the second electrode pad 35 is disposed. As shown in FIG. 12, the insulating layer 31e covers the side of the mesa groove 27c and is also formed in the portion where the lower extension 35b passes, so that it can have an overall connected curved shape. In the portion where the lower extension part 35b passes, the insulating layer 31e may be formed first, and then the lower extension part 35b may be formed thereon. Accordingly, the height of the lower extension portion 35b in the portion where the insulating layer 31e is formed may be higher than in other portions. The insulating layer 31e can prevent a short circuit from occurring when the bonding material contacts the upper semiconductor layer 27 of the eighth light emitting cell E2 when ball bonding the wire on the second electrode pad 35. there is.

The lower extension parts 35a disposed in the first, third, fourth, fifth, and sixth light emitting cells C1, C3, D1, D2, and D3 may include a straight region (i.e., vertical direction) and be parallel to each other. One end of the lower extensions 35a may be electrically connected to the connection portion 35c, and the other end may be spaced apart from the main upper extensions 37c and may be surrounded by the main upper extensions 37c. The lower extension portion 35b is formed on the second light emitting cell C2, includes a straight area, and due to the first electrode pad 37, its length may be relatively shorter than the other lower extension portions 35a. Additionally, the number of first current blocking layers 31c disposed accordingly may be smaller. The lower extension portion 35b formed on the second light emitting cell C2 and the lower extension portion 35e formed on the eighth light emitting cell E2 connect the first electrode pad 37 and the second electrode pad 35. It can be located on a connected virtual line.

The lower extension portion 35d is connected to the second electrode pad 35 and includes two interconnected straight regions. The two straight regions may be parallel to the horizontal and vertical directions of the substrate 21 and orthogonal to each other. The horizontal straight area connects the vertical straight area with the second electrode pad 35. As shown in FIG. 12, in order to form the lower extension 35d (particularly the horizontal straight region), the 7th to 9th light emitting cells E1, E2, Some areas of E3) may be mesa-etched.

The lower extension portion 35e may be formed on the eighth light emitting cell E2. One end of the lower extension 35e may be connected to the second electrode pad 35, and the other end may be surrounded by the main upper extension 37f. The length of the lower extension portion 35e may be relatively shorter than the other lower extension portions 35a and 35d due to the second electrode pad 35, and the length of the first current blocking layer 31c disposed accordingly may be relatively shorter than that of the other lower extension portions 35a and 35d. The number may be smaller.

The lower extension parts 35a, 35b, 35d, and 35e may be parallel to each other and may pass through the center of each light emitting cell. First current blocking layers 31c may be disposed under each lower extension portion 35a, 35b, 35d, and 35e. The main upper extension parts 37c, 37e, and 37f have a structure surrounding the ends of the lower extension parts 35a, 35b, 35d, and 35e. Accordingly, for the same reason as described in the embodiment of FIG. 1, the first current blocking layers 31c may not be disposed at the ends of the lower extensions 35a, 35b, 35d, and 35e.

Meanwhile, upper extension parts 37a, 37b, 37c, 37d, 37e, and 37f may be disposed on the transparent electrode layer 33. The auxiliary upper extension part 37a may electrically connect the main upper extension parts 37b and 37c on the first to third light emitting cells C1, C2, and C3. Specifically, the main upper extension parts 37b and 37c of two light emitting cells adjacent to the left and right of the auxiliary upper extension part 37a can be electrically connected. The auxiliary upper extension portion 37a is formed across two light emitting cells adjacent to each other on the left and right, and may have a curved shape. For example, referring to FIG. 12, the auxiliary upper extension 37a connects the main upper extension 37c on the first light-emitting cell C1 and the main upper extension 37b on the second light-emitting cell C2. You can connect. Accordingly, the first light emitting cell (C1) and the second light emitting cell (C2) may be electrically connected in parallel.

The auxiliary upper extension part 37d connects the main upper extension parts 37c, 37e, 37f on the fourth to ninth light emitting cells D1, D2, D3, E1, E2, and E3 with the lower extension parts 35a, 35b. You can connect. The auxiliary upper extension part 37d may have a straight shape and may be located on the same axis as the lower extension parts 35a and 35b. One end of the auxiliary upper extension portion 37d may be connected to the main upper extension portions 37c, 37e, and 37f, and the other end may be connected to the connection portion 35c.

The main upper extension portion 37b may extend from the first electrode pad 37 on the second light emitting cell C2. Specifically, the main upper extension portion 37b may extend from one edge 21a of the substrate to the other edge 21b where the second electrode pad 35 is disposed. Referring to FIG. 12 , two main upper extension parts 37b may be formed symmetrically with respect to an imaginary line connecting the first electrode pad 37 and the second electrode pad. The main upper extension 37b may have a curved shape, and accordingly, the main upper extension 37b and the first electrode pad 35 are combined to form a portion of the end and side of the lower extension 35e. It may have an enclosing structure.

The main upper extension portion 37c may be arranged to surround a portion of the end and side of the lower extension portion 35a on the first, third, fourth, fifth, and sixth light emitting cells C1, C3, D1, D2, and D3. there is. Accordingly, a portion of the main upper extension portion 37c may be disposed on one side of the lower extension portion 35a, and another portion may be disposed on the other side opposite to one side of the lower extension portion 35d. The main upper extension part 37c may have a symmetrical structure with respect to a straight line passing through the lower extension part 35a.

The main upper extension portion 37e is formed on the seventh light emitting cell E1 and the ninth light emitting cell E2 and may be arranged to surround a portion of the end and side of the lower extension portion 35d. As previously mentioned, the lower extension portion 35d has a shape in which two straight regions in the horizontal and vertical directions are combined, where the main upper extension portion 37e is a vertical straight region of the lower extension portion 35d. It may be arranged to surround part of the end and side of the. A portion of the main upper extension portion 37e may be disposed on the outside of the lower extension portion 35d, and another portion may be disposed on the inside of the lower extension portion 35d. Here, the outside refers to the part located further away from the second electrode pad 35 based on the lower extension portion 35d, and the inside refers to the part that faces the outside and is located closer to the second electrode pad 35. means part. As shown in FIG. 12, the length of the main upper extension 37e disposed on the inside may be shorter than the length of the main upper extension 37e disposed on the outside. This is to prevent current from concentrating and flowing into the lower extension portion 35d by spacing the end of the main upper extension portion 37e disposed inside and the lower extension portion 35d disposed below it a certain distance from each other.

The main upper extension portion 37f is formed on the eighth light emitting cell E2 and may have a structure that surrounds a portion of the end and side of the lower extension portion 35e. The shape of the main upper extension part 37f is generally similar to that of the main upper extension part 37c, except that the length of the second electrode pad 35 is relatively short as it is located at the bottom of the eighth light emitting cell E2. It may have characteristics that are formed.

In Figure 12, the 1st, 4th and 7th light emitting cells (C1, D1, E1) are grouped into the first group, the 2nd, 5th and 8th light emitting cells (C2, D2, E2) are grouped into the second group, and the 3rd, 6th and 8th light emitting cells (C2, D2, E2) are grouped into the first group. 9 Light-emitting cells (C3, D3, E3) can be defined as the third group. Each light emitting cell within each group may be electrically connected in series through the auxiliary upper extension portion 37d and the connection portion 35c. Additionally, the first group, second group, and third group may be electrically connected in parallel through horizontal straight areas of the auxiliary upper extension portion 37a and lower extension portion 35d.

Figure 13 is a plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 13, the light emitting diode according to this embodiment may include first to eighth light emitting cells (C1, C2, D1, D2, E1, E2, F1, F2) disposed on the substrate 21. there is. In addition, the light emitting diode includes a first electrode pad 37 and a second electrode pad 35, and includes upper extensions 37a, 37b, 37c, and 37d and lower extensions 35a, 35b, and 35d. can do.

The first and second light emitting cells (C1, C2) are separated from the third and fourth light emitting cells (D1, D2) by a separation groove (30a), and the third and fourth light emitting cells (D1, D2) are separated by a separation groove (30a). It can be separated from the fifth and sixth light emitting cells (E1 and E2) by (30b). Additionally, the fifth and sixth light emitting cells E1 and E2 are separated from the seventh and eighth light emitting cells F1 and F2 by a separation groove 30c. The separation grooves 30a, 30b, and 30c are formed through an isolation process, and the substrate 21 may be exposed through the separation grooves 30a, 30b, and 30c. On the other hand, the first light emitting cell (C1) and the second light emitting cell (C2), the third light emitting cell (D1) and the fourth light emitting cell (D2), the fifth light emitting cell (E1) and the sixth light emitting cell (E2) , and the seventh light emitting cell (F1) and the eighth light emitting cell (F2) will be separated by a mesa etching process to form a mesa separation groove (27a) exposing the lower semiconductor layers (23a, 23b, 23c, 23d). You can. Accordingly, the first light-emitting cell (C1) and the second light-emitting cell (C2) are the first lower semiconductor layer (23a), and the third light-emitting cell (D1) and the fourth light-emitting cell (D2) are the second lower semiconductor layer ( 23b), the fifth light emitting cell (E1) and the sixth light emitting cell (E2) are the third lower semiconductor layer (23c), and the seventh light emitting cell (F1) and the eighth light emitting cell (F2) are the fourth lower semiconductor layer. (23d) can be shared. That is, the semiconductor laminate including the lower semiconductor layers 23a, 23b, 23c, 23d, the active layer 25, and the upper semiconductor layer 27 is in the mesa separation groove 27a and the separation grooves 30a, 30b, 30c. It can be separated into first to eighth light emitting cells (C1, C2, D1, D2, E1, E2, F1, F2).

No electrode parts other than the first electrode pad 37 and the second electrode pad 35 are placed in the mesa separation groove 27a, and the lower semiconductor layers 23a, 23b, 23c, and 23d may be exposed. there is. Based on the mesa separation groove 27a or an imaginary line connecting the first electrode pad 37 and the second electrode pad 35, the first light emitting cell C1, the second light emitting cell C2, and the third light emitting cell C1 The light emitting cell (D1) and the fourth light emitting cell (D2), the fifth light emitting cell (E1) and the sixth light emitting cell (E2), and the seventh light emitting cell (F1) and eighth light emitting cell (F2) are each symmetrical. It can have a shape. Therefore, the description will focus on the first, third, fifth, and seventh light emitting cells (C1, D1, E1, and F1) located on the left side of the light emitting diode.

The first, third, fifth, and seventh light emitting cells (C1, D1, E1, and F1) may have a structure that is electrically connected in series. Additionally, the 2nd, 4th, 6th, and 8th light emitting cells (C2, D2, E2, and F2) may have a structure that is electrically connected in series. And the 1st, 3, 5, and 7th light emitting cells (C1, D1, E1, F1) and the 2nd, 4th, 6th, and 8th light emitting cells (C2, D2, E2, F2) may have a structure in which they are electrically connected in parallel. there is. By connecting multiple light emitting cells in parallel, the input current can be evenly distributed to each light emitting cell, thereby reducing the voltage rise when driving at high currents and improving the droop phenomenon.

The first electrode pad 37 may be disposed near one edge 21a of the substrate 21, and the second electrode pad 35 may be disposed near the other edge 21b opposite the one edge. As shown in FIG. 13, the first electrode pad 37 and the second electrode pad 35 may be disposed to face each other. Furthermore, the first electrode pad 37 may be formed across the first light emitting cell C1 and the second light emitting cell C2.

The shape of the first electrode pad 35 in FIG. 13 is similar to that in FIG. 1 . A third current blocking layer 31a having a larger area than the first electrode pad 37 may be disposed under the first electrode pad 37 . The first electrode pad 37 may be located limited to the upper part of the third current blocking layer 31a. The first electrode pad 37 is located on the mesa separation groove 27a and may be disposed across the first light emitting cell C1 and the second light emitting cell C2. Accordingly, the third current blocking layer 31a can insulate the first electrode pad 37 and the first lower semiconductor layer 23a on the mesa separation groove 27a. Additionally, the third current blocking layer 31a may be interposed between the transparent electrode layer 33 and the upper semiconductor layer 27 on the first and second light emitting cells C1 and C2. Meanwhile, a portion of the transparent electrode layer 33 is located below the first electrode pad 37 and may include an opening 33a exposing the third current blocking layer 31a. The transparent electrode layers 33 on the first light-emitting cell C1 and the second light-emitting cell C2 each include openings 33a, and the openings 33a are adjacent to each other with the mesa separation groove 27a therebetween. It can be formed symmetrically.

The opening 33a may have a semicircular shape. By forming the opening 33a in the transparent electrode layer 33, the adhesive force of the first electrode pad 37 can be increased. However, the shape of the opening 33a is not limited to this and may include various shapes within a target range that can increase the adhesive force of the first electrode pad 37. Also, in this embodiment, the opening 33a is formed in the transparent electrode layer 33, but the opening may be formed in the third current blocking layer 31a to expose the upper semiconductor layer 27.

The second electrode pad 35 may be disposed in the mesa separation groove 27a near the other edge of the substrate 21 and electrically connected to the fourth lower semiconductor layer 23d. Meanwhile, the seventh light-emitting cell F1 and the eighth light-emitting cell F2 may be located adjacent to the second electrode pad 35. A second current blocking layer 31b may be disposed below the second electrode pad 35. The second current blocking layer 31b is disposed between the second electrode pad 35 and the second lower semiconductor layer 23b to smooth horizontal distribution of the current injected into the second lower semiconductor layer 23b. there is. The area of the second current blocking layer 31b may be smaller than that of the second electrode pad 35. That is, the horizontal and vertical widths of the second current blocking layer 31b are smaller than those of the second electrode pad 35, and therefore, it may be located in a partial area of the second electrode pad 35. For example, the area of the second current blocking layer 31b may be limited to 90% or less of the area of the second electrode pad 35.

The insulating layer 31e may cover the side surfaces of the seventh light-emitting cell F1 and the eighth light-emitting cell F2 near the second electrode pad 35. Referring to FIG. 13, the insulating layer 31e covers the side surfaces of the seventh light emitting cell F1 and the eighth light emitting cell F2, and is also formed in the portion where the lower extension part 35a passes, forming a curve connected as a whole. It can have a shape. In the portion where the lower extension 35a passes, the insulating layer 31e may be formed first, and then the lower extension 35a may be formed thereon. Accordingly, the height of the lower extension portion 35a may be structurally higher in the portion where the insulating layer 31e is formed compared to other portions. When the wire is ball-bonded on the second electrode pad 35, the insulating layer 31e is formed so that the bonding material contacts the upper semiconductor layer 27 of the third light-emitting cell D1 or fourth light-emitting cell D2. It can prevent short circuits from occurring. The insulating layer 31e may be spaced apart from the transparent electrode layer 33, and therefore, the area of the insulating layer 31e may be formed to be relatively very small. Accordingly, light loss due to the insulating layer 31e can be reduced.

The lower semiconductor layers 23a, 23b, 23c, and 23d are exposed through the upper semiconductor layer 27 and the active layer 25 of each light-emitting cell, and the lower semiconductor layers 23a, 23b, 23c, and 23d are exposed. Extension portions 35a, 35b, and 35d may be disposed. The lower extensions 35a, 35b, and 35d may be electrically connected to the lower semiconductor layers 23a, 23b, 23c, and 23d.

The lower extension parts 35a, 35b disposed in the first to sixth light emitting cells (C1, C2, D1, D2, E1, E2) include two straight regions (horizontal and vertical directions) and a curved region connecting them. can do. The lower extension portion 35a formed on the first and fifth light emitting cells C1 and E1 and the lower extension portion 35b formed on the third light emitting cell D1 may have a mirror symmetrical shape. One end of the lower extensions (35a, 35b) is connected to the connection portion (35c) and electrically connected to the main upper extension (37c or 37d) of the light emitting cell adjacent above and below, and the other end is connected to the main upper extension (37c or 37d). ) can be surrounded by a curved area close to the center. For example, one end of the lower extension portion 35a formed in the first light emitting cell C1 may be connected to the auxiliary upper extension portion 37a of the third light emitting cell D1 through a connection portion 35c. Through this, the first light emitting cell (C1) and the third light emitting cell (D1) can be electrically connected in series.

Additionally, referring to FIG. 13, the lower extension portion 35a of the first light emitting cell C1 extends vertically from the bottom left, not the center of the first light emitting cell C1, and is bent to the right, and the third light emitting cell C1 In (D1), the lower extension portion 35b extends vertically from the lower right side of the third light emitting cell D1 and may be bent to the left. Additionally, the lower extension portion 35a of the fifth light emitting cell E1 may extend vertically from the lower left side of the fifth light emitting cell E1 and be bent to the right. That is, in the light emitting diode according to this embodiment, unlike the light emitting diode shown in FIGS. 1 and 13, the lower extension portions 35a and 35b may extend from the left or right side rather than the center of the bottom of each light emitting cell.

The lower extension portion 35d is formed on the seventh light emitting cell F1 and may be connected to the second electrode pad 35. The lower extension portion 35d may include a straight region and a curved region. The curved area may connect the straight area and the second electrode pad 35. Unlike the embodiments of FIGS. 1 and 13, the straight region may be formed in the horizontal direction of the light emitting diode.

First current blocking layers 31c may be disposed below each lower extension part 35a, 35b, and 35d. The first current blocking layers 31c may have a plurality of shapes spaced apart from each other. The first current blocking layers 31c are disposed between the lower extensions 35a, 35b, and 35d and the lower semiconductor layers 23a, 23b, 23c, and 23d to form the lower semiconductor layers 23a, 23b, 23c, and 23d. It can help distribute the injected current in the horizontal direction. Here, for the same reason as the embodiments of FIGS. 1 and 12 , the first current blocking layers 31c may not be disposed on the other ends of the lower extensions 35a, 35b, and 35d.

Meanwhile, upper extension parts 37a, 37b, 37c, and 37d may be disposed on the transparent electrode layer 33. The main upper extension portion 37a may extend in the horizontal direction from the first electrode pad 37 on the first light emitting cell C1 toward the vertical axis edge 21c of the substrate 21. Referring to FIG. 13 , the main upper extension 37a may include a round shape in contact with the first electrode pad 37 and two curves extending horizontally from the round shape. The main upper extension portion 37a includes two ends and may be arranged to surround the ends and a portion of the side of the lower extension portion 35a. Accordingly, a portion of the main upper extension portion 37a may be disposed above the lower extension portion 35a, and another portion may be disposed below the lower extension portion 35a. Here, an area close to one edge 21a of the substrate 21 based on the lower extension 35a corresponds to the upper side, and an area close to the other edge 21b opposite the one edge corresponds to the lower side. The main upper extension 37a may have a generally symmetrical structure with respect to the straight area of the lower extension 35a, but the upper end of the main upper extension 37a is closer to the vertical axis edge 21c of the substrate 21 than the lower end. ) can be located closer to . That is, as shown in FIG. 13, the area of the main upper extension 37a located above the lower extension 35a is longer than the area located below, and the curved area of the lower extension 35a is It can bend accordingly.

The auxiliary upper extension 37b may be formed at the upper left or upper right of the 3rd, 5th, and 7th light emitting cells. The auxiliary upper extension portion 37b may have a straight shape vertically vertically. One end of the auxiliary upper extension 37b may be connected to the connection part 35c and the other end may be connected to the main upper extension 37c or 37d. For example, the auxiliary upper extension portion 37b formed on the third light emitting cell (D1) is formed at the upper right corner of the third light emitting cell, and one end is connected to the connection portion 35c to form the first light emitting cell (C1). It may be electrically connected to the auxiliary upper extension portion 35a. Additionally, the other end of the auxiliary upper extension 37b may be connected to the upper right of the main upper extension 37c of the third light emitting cell D1. Through this, the first light-emitting cell (C1) and the third light-emitting cell (D1) can be electrically connected in series, and in the same way, the third light-emitting cell (D1) and the fifth light-emitting cell (E1) can be electrically connected in series. there is.

The main upper extension portion 37c is formed on the third and seventh light emitting cells D1 and F1, and extends in the horizontal direction from the vertical axis edge 21c of the substrate 21 toward the mesa separation groove 27a. You can have The main upper extension 37c is generally similar to the shape of the main upper extension 37a formed on the first light emitting cell C1, and may have a mirror symmetrical structure. There is a difference in the area and location where the main upper extension 37a contacts the first electrode pad 37 and the area where the main upper extension 37c contacts the auxiliary upper extension 37a. Referring to FIG. 13, the area where the upper extension 37a is in contact with the first electrode pad 37 is larger than the area where the main upper extension 37c is in contact with the auxiliary upper extension 37a, and the mesa separation groove ( It can be seen that it is placed close to 27a). The main upper extension part 37d is formed on the fifth light emitting cell and may have a mirror symmetrical shape with the main upper extension part 37c.

The shapes of the upper and lower extensions on the 2nd, 4th, 6th, and 8th light emitting cells (C2, D2, E2, F2) are the mesa separation groove 27a or the first electrode pad 37 and the second electrode pad ( The upper extensions (37a, 37b, 37c, 37d, 37e) and lower extensions (35a) on the first, third, fifth and seventh light emitting cells (C1, D1, E1, F1) based on the virtual line connecting 35). , 35b, 35d) and can be symmetrical.

Figure 14 is a plan view for explaining a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 14, the light emitting diode according to this embodiment may include first to eighth light emitting cells (C1, C2, D1, D2, E1, E2) disposed on the substrate 21. In addition, the light emitting diode includes a first electrode pad 37 and a second electrode pad 35, and upper extensions 37a, 37b, 37c, 37d, 37e, 37f, 37g, 37h and lower extensions ( 35a, 35b, 35d, 35e, 35f, 35g).

The light emitting cells C1, C2, D1, D2, E1, and E2 may be separated into individual light emitting cells through separation grooves 30a, 30b, and 30c. Specifically, the first and second light emitting cells (C1, C2) are separated from the third and fourth light emitting cells (D1, D2) by a separation groove (30a), and the third and fourth light emitting cells (D1, D2) are It can be separated from the fifth and sixth light emitting cells (E1 and E2) by the separation groove (30b). Additionally, the first, third, and fifth light emitting cells C1, D1, and E1 may be separated from the second, fourth, and sixth light emitting cells C2, D2, and E2 through the separation groove 30c. That is, the semiconductor laminate including the lower semiconductor layers (23a, 23b, 23c), the active layer 25, and the upper semiconductor layer 27 is separated from the first to sixth light emitting cells by the separation grooves (30a, 30b, 30c). It can be separated into (C1, C2, D1, D2, E1, E2).

The separation grooves 30a, 30b, and 30c are formed through an isolation process, and the substrate 21 may be exposed through the separation grooves 30a, 30b, and 30c. Each light emitting cell may have a rectangular shape with a horizontal width greater than a vertical width. The first to sixth light emitting cells (C1, C2, D1, D2, E1, E2) may have a structure electrically connected in series. Referring to FIG. 14, the first electrode pad 37 is formed at the upper right corner of the second light emitting cell (C2), and the second electrode pad 35 is formed at the lower left corner of the fifth light emitting cell (E1). It is formed on the groove 27a. That is, in the substrate 21, the first electrode pad 37 and the second electrode pad 35 may be formed diagonally. In addition, based on the separation groove 30c, the first light emitting cell C1 and The fourth light-emitting cell D2, the third light-emitting cell D1, and the sixth light-emitting cell E2 may each have symmetrical shapes.

Specifically, the first electrode pad 37 may be formed in the upper right area of the first light emitting cell C1. A third current blocking layer 31a may be located below the first electrode pad 37. Specifically, the third current blocking layer 31a may be interposed between the transparent electrode layer 33 and the upper semiconductor layer 27 below the first electrode pad 37. The width of the third current blocking layer 31a is larger than the width of the first electrode pad 37, and accordingly, the third current blocking layer 31a connects the first electrode pad 37 to the first lower semiconductor layer 23a. ) can be insulated from A portion of the transparent electrode layer 33 is located below the first electrode pad 37 and may include an opening 33a exposing the third current blocking layer 31a. The opening 33a may have a circular shape. By forming the opening 33a in the transparent electrode layer 33, the adhesive force of the first electrode pad 37 can be increased. Here, the shape of the opening 33a is not limited to a circular shape and may include various shapes within a target range that can increase the adhesive force of the first electrode pad 37.

The second electrode pad 35 may be disposed on the mesa groove 27a. That is, to form the second electrode pad 35, a portion of the lower left area of the fifth light emitting cell E1 may be mesa-etched to form the mesa groove 27a. The second electrode pad 35 may be disposed in the mesa groove 27a and electrically connected to the third lower semiconductor layer 23c.

A second current blocking layer 31b may be disposed below the second electrode pad 35. The second current blocking layer 31b is disposed between the second electrode pad 35 and the third lower semiconductor layer 23c to smoothly horizontally distribute the current injected into the third lower semiconductor layer 23c. there is. The area of the second current blocking layer 31b is smaller than that of the second electrode pad 35. That is, the horizontal and vertical widths of the second current blocking layer 31b are smaller than those of the second electrode pad 35, and therefore, it may be located in a partial area of the second electrode pad 35. For example, the area of the second current blocking layer 31b may be limited to 90% or less of the area of the second electrode pad 35.

The insulating layer 31e may cover the side of the mesa groove 27a. As shown in FIG. 14, the insulating layer 31e covers the side of the mesa groove 27a and is also formed in the area where the lower extension 35a passes, so that it can have a single linear shape connected as a whole. At the portion where the lower extension 35a passes, the insulating layer 31e may be formed first, and then the lower extension 35a may be formed thereon. Accordingly, the height of the lower extension portion 35a may be higher in the portion where the insulating layer 31e is formed than in other portions. The insulating layer 31e can prevent a short circuit from occurring when the bonding material contacts the upper semiconductor layer 27 of the fifth light emitting cell E1 when ball bonding the wire on the second electrode pad 35. there is.

The lower semiconductor layers 23a, 23b, and 23c may be exposed through the upper semiconductor layer 27 and the active layer 25 of each light-emitting cell, and lower extensions may be formed on the exposed lower semiconductor layers 23a, 23b, and 23c. (35a, 35b, 35d, 35e, 35f, 35g) can be arranged. The lower extensions 35a, 35b, 35d, 35e, 35f, and 35g may be electrically connected to the lower semiconductor layers 23a, 23b, and 23c.

The lower extension portion 35a is formed on the second light emitting cell C2 and may have a straight shape. The lower extension portion 35a may be formed along the center line of the second light emitting cell E2. The straight area (horizontal direction) of the lower extension portion 35a and the lower extension portion 35b of the first light emitting cell C1 may be located on a straight line. One end of the lower extension portion 35a is connected to the connection portion 35c and may be electrically connected to the auxiliary upper extension portion 37h of the first light emitting cell C1. Accordingly, the second light emitting cell (C2) and the first light emitting cell (C1) can be electrically connected in series. The other end of the lower extension 35a may be surrounded by the main upper extension 37b. However, since the first electrode pad 37 is formed on the second light emitting cell C2, the length of the lower extension portion 35a may be formed relatively short.

The lower extension portion 35b is formed on the first light emitting cell C1 and may include two straight regions (horizontal and vertical directions) and a curved region connecting them. The vertical straight area of the lower extension portion 35b is formed at the bottom of the left side of the first light emitting cell C1, and one end is connected to the connection portion 35c to form an auxiliary upper extension portion of the third light emitting cell D1. It is connected to (37a), and the other end may be connected to the curved area. Accordingly, the first light emitting cell (C1) and the third light emitting cell (D1) may be electrically connected in series. To form a straight vertical area of the lower extension portion 35b, the lower left side of the first light emitting cell C1 may be mesa-etched. Additionally, the horizontal straight region may be formed along the center line of the first light emitting cell C1, one end may be connected to the curved region, and the other end may be surrounded by the main upper extension portion 37c.

The lower extension portion 35d is formed on the third light emitting cell D1 and may have a straight shape. The lower extension portion 35d may be formed along the center line of the third light emitting cell D1. The straight area (horizontal direction) of the lower extension portion 35d and the lower extension portion 35e of the fourth light emitting cell D2 may be located on a straight line. One end of the lower extension portion 35d is connected to the connection portion 35c and may be electrically connected to the auxiliary upper extension portion 37h of the fourth light emitting cell D2. As a result, the third light-emitting cell D1 and the fourth light-emitting cell D2 can be electrically connected in series. The other end of the lower extension portion 35d may be surrounded by the main upper extension portion 37d.

The lower extension portion 35e is formed on the fourth light emitting cell D2 and may have a shape symmetrical to the lower extension portion 35b with respect to the separation groove 30c.

The lower extension portion 35f is formed on the fifth light emitting cell E1 and may include a curved area and a straight area. One end of the curved area may be connected to the second electrode pad 35 and the other end may be connected to one end of the straight area. The other end of the immediate area may be wrapped in two main upper extension parts (37g). Additionally, a straight area may be formed at the center of the fifth light emitting cell E1.

The lower extension portion 35g is formed on the sixth light emitting cell E2 and may have a shape symmetrical to the lower extension portion 35d with respect to the separation groove 30c.

First current blocking layers 31c may be disposed under each lower extension portion 35a, 35b, 35d, and 35e. The first current blocking layers 31c may have a plurality of shapes spaced apart from each other. The first current blocking layers 31c are disposed between the lower extensions 35a, 35b, 35d, 35e, 35f, 35g and the lower semiconductor layers 23a, 23b, and 23c to form the lower semiconductor layers 23a, 23b, and 23c. ) can help distribute the injected current in the horizontal direction. However, the first current blocking layers 31c may not be disposed at the ends of the lower extensions 35a, 35b, 35d, 35e, 35f, and 35g.

Meanwhile, upper extension parts 37a, 37b, 37c, 37d, 37e, 37f, 37g, and 37h may be disposed on the transparent electrode layer 33. The main upper extension portion 37b may extend from the first electrode pad 37 toward the separation groove 30c on the second light emitting cell C2. The main upper extension part 37b may be arranged to surround the end and a portion of the side of the lower extension part 35a. Accordingly, a part of the main upper extension 37b is located above the lower extension 35a, another part is located below the lower extension 35a, and another part is located on the lower side of the lower extension 35a. It may be disposed between the end of and the edge 21d of the substrate 21. Additionally, the main upper extension 37b has two ends, and these ends may be located above and below the lower extension 35a, respectively. Here, the upper side of the lower extension 35a refers to an area close to one edge 21a of the substrate with respect to the lower extension 35a and the virtual straight line extending it, and the lower side refers to the side opposite to the upper side. do. The distance between the main upper extension part 37b and the lower extension part 35a may not be constant, and may move away and then become closer along the extension direction of the main upper extension part 37b.

The main upper extension portion 37c may extend in the horizontal direction from the separation groove 30c toward one side 21c of the substrate 21 on the first light emitting cell C1. The main upper extension portion 37c may have a curved shape. The main upper extension portion 37c may be arranged to surround an end portion and a portion of the side surface of the straight area (horizontal direction) of the lower extension portion 35b. Accordingly, a part of the main upper extension 37c is located above the lower extension 35b, another part is located below the lower extension 35b, and another part is located on the lower side of the lower extension 35b. It may be disposed between the end of and the separation groove (30c). Additionally, the main upper extension 37b has two ends, and these ends may be located above and below the lower extension 35b, respectively. The main upper extension part 37c may have a symmetrical structure with respect to an imaginary line passing through a straight area of the lower extension part 35b.

The main upper extension 37c is formed on the first light emitting cell C1, and most of the shape except for the area where the auxiliary upper extensions 37a and 37h are connected is the main upper extension of the sixth light emitting cell ( Similar to 37f). In addition, the main upper extensions 37d and 37e are formed on the third light emitting cell D1 and the fourth light emitting cell D2, and most of the remaining areas except the area where the auxiliary upper extensions 37a and 37h are connected are It may have a mirror symmetrical shape with the main upper extension portion 37c.

The main upper extension portion 37g may extend in the horizontal direction from the separation groove 30c toward one side 21c of the substrate 21 on the fifth light emitting cell E1. The main upper extension part 37g may be arranged to surround the end and a portion of the side of the lower extension part 35f. Accordingly, a part of the main upper extension 37g is located above the lower extension 35f, another part is located below the lower extension 35f, and another part is located on the lower side of the lower extension 35f. It may be disposed between the end of and the separation groove (30c). The distance between the main upper extension part 37g and the lower extension part 35f may not be constant, and may move away and then become closer along the extension direction of the main upper extension part 37g. The main upper extension 37g may have a generally symmetrical structure with respect to the straight area of the lower extension 35f, but the upper end of the lower extension 35f is closer to the edge 21c of the substrate 21 than the lower end. It can be located closer. That is, as shown in FIG. 14, the area of the main upper extension 37g located above the lower extension 35f is longer than the area located below, and the curved area of the lower extension 35f is It may bend accordingly.

Meanwhile, the auxiliary upper extensions 37a formed on the third and sixth light emitting cells D1 and E2 may connect the main upper extension with the lower extension between the upper and lower light emitting cells. For example, one end of the auxiliary upper extension portion 37a formed on the third light emitting cell D1 is connected to the connection portion 35c and is electrically connected to the lower extension portion 35b formed on the first light emitting cell C1. can be connected Additionally, the other end of the auxiliary upper extension 37a formed on the third light emitting cell D1 may be connected to the main upper extension 37d. Through this structure, the first light emitting cell (C1) and the third light emitting cell (D1) can be electrically connected in series. The auxiliary upper extensions 37a may extend obliquely from one side of the top of the light emitting cells to the lower right or left, and be connected to the main upper extensions 37d and 37f.

also. The auxiliary upper extensions 37h formed on the first, fourth, and fifth light emitting cells C1, D2, and E1 may connect the main upper extension with the lower extension between left and right adjacent light emitting cells. For example, one end of the auxiliary upper extension portion 37h formed on the first light emitting cell C1 is connected to the connection portion 35c and is electrically connected to the lower extension portion 35a formed on the second light emitting cell C2. can be connected Additionally, the other end of the auxiliary upper extension 37h formed on the first light emitting cell C1 may be connected to the center of the main upper extension 37c. Through this structure, the first light emitting cell (C1) and the second light emitting cell (C2) can be electrically connected in series. The auxiliary upper extensions 37h have a straight shape and may be arranged in a straight line with the lower extensions 35b, 35e, and 35g.

Figure 15 is a cross-sectional view showing various embodiments of the side shape of a light emitting diode according to another embodiment of the present invention. The embodiment of the side surface of the substrate shown in FIGS. 15A to 15C can be applied to the side surface of the light emitting diodes shown in FIGS. 1 and 12 to 14 presented above.

When examined in detail, the patterned substrate 21 is exposed on the side of the light emitting diode shown in FIG. 15A, and a step is formed in the semiconductor stack. The patterned substrate 21 is exposed through an isolation process, and steps are formed through a mesa etching process. That is, first, the patterned substrate 21 is exposed from the side of the light emitting diode through an isolation process, and then a step is formed in the lower semiconductor layer 23 through a mesa etching process. When a step is formed in the semiconductor stack, there is an advantage in increasing the bonding force when depositing the connecting metal.

The patterned substrate 21 is exposed on the side of the light emitting diode shown in FIG. 15B, but unlike FIG. 15A, no steps are formed in the semiconductor stack. This is because, unlike FIG. 15A, the mesa etching process was performed first, followed by the isolation process.

On the side of the light emitting diode shown in FIG. 15C, unlike FIGS. 15A and 15B presented previously, the substrate 21 is not exposed and a step is formed in the semiconductor stack. This is because an isolation process was not performed on the side of the light emitting diode, and only a mesa etching process was performed. During the isolation process, the semiconductor stack, that is, the light emitting area, is inevitably removed, but the side of the light emitting diode shown in Figure 15c has the advantage of securing the maximum light emitting area by omitting the isolation process.

A light emitting diode according to an embodiment of the present invention can operate at a relatively high voltage using light emitting cells connected in series. Therefore, the total driving current can be lowered. Furthermore, the current can be evenly distributed by connecting the light emitting cells in parallel and using the lower and upper extension parts. Additionally, the light emitting diode can be packaged through a conventional process, and a wavelength conversion layer containing a phosphor can be disposed on the light emitting diode. Accordingly, a light emitting device that emits white light can be provided.

Figure 16 shows a package mounting form of a light emitting diode according to various embodiments of the present invention. FIG. 16 shows the light emitting diode shown in FIG. 1 packaged in a lead frame through wire bonding. However, instead of the light emitting diode shown in Figure 1, the light emitting diode shown in Figures 12 to 14 may be packaged.

A light emitting diode according to an embodiment of the present invention can operate at a relatively high voltage using light emitting cells connected in series. Therefore, the total driving current can be lowered. Furthermore, the current can be evenly distributed by connecting the light emitting cells in parallel and using the lower and upper extension parts. Additionally, the light emitting diode can be packaged through a conventional process, and a wavelength conversion layer containing a phosphor can be disposed on the light emitting diode. Accordingly, a light emitting device that emits white light can be provided.

Claims (1)

A semiconductor laminate including a lower semiconductor layer, an upper semiconductor layer, and an active layer disposed between the lower semiconductor layer and the upper semiconductor layer, and having a separation groove in the upper semiconductor layer, the active layer, and the lower semiconductor layer;
a first electrode pad and an upper extension electrically connected to the upper semiconductor layer;
a second electrode pad and a lower extension electrically connected to the lower semiconductor layer;
a connection part connecting the upper extension part and the lower extension part across the separation groove and having a width wider than the width of the upper extension part and the lower extension part;
a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and
It includes a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer,
The first current blocking layer includes a plurality of dots spaced apart from each other, and the width of each dot is greater than the width of the lower extension portion,
The width of the second current blocking layer is narrower than the width of the second electrode pad,
A light emitting diode wherein the shortest distance from the separation groove to the first current blocking layer is greater than the separation distance between the plurality of dots.