JP6382924B2 - ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体 - Google Patents

ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体 Download PDF

Info

Publication number
JP6382924B2
JP6382924B2 JP2016246448A JP2016246448A JP6382924B2 JP 6382924 B2 JP6382924 B2 JP 6382924B2 JP 2016246448 A JP2016246448 A JP 2016246448A JP 2016246448 A JP2016246448 A JP 2016246448A JP 6382924 B2 JP6382924 B2 JP 6382924B2
Authority
JP
Japan
Prior art keywords
tlb
core
request
processor
processor core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016246448A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017220211A (ja
Inventor
エリック・ノーサップ
ベンジャミン・チャールズ・セレブリン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
Google LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Google LLC filed Critical Google LLC
Publication of JP2017220211A publication Critical patent/JP2017220211A/ja
Application granted granted Critical
Publication of JP6382924B2 publication Critical patent/JP6382924B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533Hypervisors; Virtual machine monitors
    • G06F9/45558Hypervisor-specific management and integration aspects
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533Hypervisors; Virtual machine monitors
    • G06F9/45558Hypervisor-specific management and integration aspects
    • G06F2009/45583Memory management, e.g. access or allocation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15Use in a specific computing environment
    • G06F2212/152Virtualized environment, e.g. logically partitioned system
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68Details of translation look-aside buffer [TLB]
    • G06F2212/682Multiprocessor TLB consistency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68Details of translation look-aside buffer [TLB]
    • G06F2212/683Invalidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2016246448A 2016-06-08 2016-12-20 ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体 Active JP6382924B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662347495P 2016-06-08 2016-06-08
US62/347,495 2016-06-08
US201615293627A 2016-10-14 2016-10-14
US15/293,627 2016-10-14

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018146132A Division JP6716645B2 (ja) 2016-06-08 2018-08-02 ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体

Publications (2)

Publication Number Publication Date
JP2017220211A JP2017220211A (ja) 2017-12-14
JP6382924B2 true JP6382924B2 (ja) 2018-08-29

Family

ID=57569990

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2016246448A Active JP6382924B2 (ja) 2016-06-08 2016-12-20 ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体
JP2018146132A Active JP6716645B2 (ja) 2016-06-08 2018-08-02 ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2018146132A Active JP6716645B2 (ja) 2016-06-08 2018-08-02 ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体

Country Status (6)

Country Link
EP (2) EP3255550B1 (enExample)
JP (2) JP6382924B2 (enExample)
CN (2) CN107480075B (enExample)
DE (2) DE102016124749B4 (enExample)
DK (2) DK3502906T3 (enExample)
GB (1) GB2551226A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108710584B (zh) * 2018-05-22 2021-08-31 郑州云海信息技术有限公司 一种提高tlb刷新效率的方法
CN114595164B (zh) * 2022-05-09 2022-08-16 支付宝(杭州)信息技术有限公司 在虚拟化平台中管理tlb高速缓存的方法和装置
WO2025236116A1 (en) * 2024-05-11 2025-11-20 Yangtze Memory Technologies Co., Ltd. Data migration in memory systems

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63286944A (ja) * 1987-05-20 1988-11-24 Hitachi Ltd アドレス変換バツフア無効化方式
JPH01109452A (ja) * 1987-10-22 1989-04-26 Fujitsu Ltd 変換索引バッファ情報の消去制御方式
JP2806778B2 (ja) * 1994-01-28 1998-09-30 甲府日本電気株式会社 変換索引バッファクリア命令処理方式
JP4361909B2 (ja) * 1995-03-20 2009-11-11 富士通株式会社 キャッシュコヒーレンス装置
US5906001A (en) * 1996-12-19 1999-05-18 Intel Corporation Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
US20040117590A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Aliasing support for a data processing system having no system memory
US7073043B2 (en) * 2003-04-28 2006-07-04 International Business Machines Corporation Multiprocessor system supporting multiple outstanding TLBI operations per partition
US7188229B2 (en) * 2004-01-17 2007-03-06 Sun Microsystems, Inc. Method and apparatus for memory management in a multi-processor computer system
US7281116B2 (en) * 2004-07-30 2007-10-09 Hewlett-Packard Development Company, L.P. Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
US7454590B2 (en) * 2005-09-09 2008-11-18 Sun Microsystems, Inc. Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores
JP4908017B2 (ja) * 2006-02-28 2012-04-04 富士通株式会社 Dmaデータ転送装置及びdmaデータ転送方法
US20120203831A1 (en) * 2011-02-03 2012-08-09 Kent Schoen Sponsored Stories Unit Creation from Organic Activity Stream
CN101398768B (zh) * 2008-10-28 2011-06-15 北京航空航天大学 一种分布式虚拟机监视器系统的构建方法
CN102262557B (zh) * 2010-05-25 2015-01-21 运软网络科技(上海)有限公司 通过总线架构构建虚拟机监控器的方法及性能服务框架
US9916257B2 (en) * 2011-07-26 2018-03-13 Intel Corporation Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
CN106708753B (zh) * 2012-03-30 2021-04-02 英特尔公司 在使用共享虚拟存储器的处理器中加速操作的装置和方法
US9081707B2 (en) * 2012-12-29 2015-07-14 Intel Corporation Apparatus and method for tracking TLB flushes on a per thread basis
US9411745B2 (en) * 2013-10-04 2016-08-09 Qualcomm Incorporated Multi-core heterogeneous system translation lookaside buffer coherency
US9619387B2 (en) * 2014-02-21 2017-04-11 Arm Limited Invalidating stored address translations
WO2016012831A1 (en) 2014-07-21 2016-01-28 Via Alliance Semiconductor Co., Ltd. Simultaneous invalidation of all address translation cache entries associated with x86 process context identifier
JP6663108B2 (ja) * 2016-02-29 2020-03-11 富士通株式会社 物理演算処理装置、情報処理装置及び情報処理装置の制御方法

Also Published As

Publication number Publication date
DE102016124749A1 (de) 2017-12-14
EP3255550A1 (en) 2017-12-13
JP2017220211A (ja) 2017-12-14
CN112286839B (zh) 2024-05-10
CN112286839A (zh) 2021-01-29
GB2551226A (en) 2017-12-13
DE202016008132U1 (de) 2017-04-24
JP2018181378A (ja) 2018-11-15
EP3255550B1 (en) 2019-04-03
DE102016124749B4 (de) 2023-08-10
JP6716645B2 (ja) 2020-07-01
EP3502906A1 (en) 2019-06-26
DK3255550T3 (da) 2019-07-15
CN107480075A (zh) 2017-12-15
GB201621246D0 (en) 2017-01-25
DK3502906T3 (da) 2021-08-30
CN107480075B (zh) 2020-10-27
EP3502906B1 (en) 2021-06-16

Similar Documents

Publication Publication Date Title
US10977191B2 (en) TLB shootdowns for low overhead
US9772962B2 (en) Memory sharing for direct memory access by a device assigned to a guest operating system
US9671970B2 (en) Sharing an accelerator context across multiple processes
US20240330199A1 (en) Secure memory access in a virtualized computing environment
CN113454590B (zh) 定向中断虚拟化
US10367688B2 (en) Discovering changes of network interface controller names
CN107491340B (zh) 跨物理机的巨型虚拟机实现方法
US11010084B2 (en) Virtual machine migration system
JP6716645B2 (ja) ハードウェア内で変換索引バッファ(tlb)シュートダウンを指示および追跡するための方法およびシステム、並びに非一時的なコンピュータ可読媒体
EP3274896B1 (en) Configuration of a memory controller for copy-on-write with a resource controller
US10341177B2 (en) Parallel computing system and migration method
KR20220001016A (ko) 게스트 운영체제에 입출력 메모리 관리 유닛 레지스터 복사본을 제공하는 방법
JP5881852B2 (ja) 仮想計算機システム
US11409551B2 (en) Emulating VPID correctly for a nested hypervisor
US12423132B2 (en) Efficient queue shadowing for virtual machines
US20230214247A1 (en) Robust resource removal for virtual machines
US20170139755A1 (en) Efficient chained post-copy virtual machine migration

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20171003

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20171226

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180302

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180703

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180802

R150 Certificate of patent or registration of utility model

Ref document number: 6382924

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250