DK3502906T3 - Tlb-shootdown for lav overhead - Google Patents

Tlb-shootdown for lav overhead Download PDF

Info

Publication number
DK3502906T3
DK3502906T3 DK19151501.4T DK19151501T DK3502906T3 DK 3502906 T3 DK3502906 T3 DK 3502906T3 DK 19151501 T DK19151501 T DK 19151501T DK 3502906 T3 DK3502906 T3 DK 3502906T3
Authority
DK
Denmark
Prior art keywords
low overhead
tlb shootdown
shootdown
tlb
overhead
Prior art date
Application number
DK19151501.4T
Other languages
Danish (da)
English (en)
Inventor
Eric Northup
Benjamin Charles Serebrin
Original Assignee
Google Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Google Llc filed Critical Google Llc
Application granted granted Critical
Publication of DK3502906T3 publication Critical patent/DK3502906T3/da

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DK19151501.4T 2016-06-08 2016-12-14 Tlb-shootdown for lav overhead DK3502906T3 (da)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662347495P 2016-06-08 2016-06-08
US201615293627A 2016-10-14 2016-10-14
EP16204029.9A EP3255550B1 (en) 2016-06-08 2016-12-14 Tlb shootdowns for low overhead

Publications (1)

Publication Number Publication Date
DK3502906T3 true DK3502906T3 (da) 2021-08-30

Family

ID=57569990

Family Applications (2)

Application Number Title Priority Date Filing Date
DK19151501.4T DK3502906T3 (da) 2016-06-08 2016-12-14 Tlb-shootdown for lav overhead
DK16204029.9T DK3255550T3 (da) 2016-06-08 2016-12-14 TLB shootdowns til lave omkostninger

Family Applications After (1)

Application Number Title Priority Date Filing Date
DK16204029.9T DK3255550T3 (da) 2016-06-08 2016-12-14 TLB shootdowns til lave omkostninger

Country Status (6)

Country Link
EP (2) EP3255550B1 (enExample)
JP (2) JP6382924B2 (enExample)
CN (2) CN107480075B (enExample)
DE (2) DE102016124749B4 (enExample)
DK (2) DK3502906T3 (enExample)
GB (1) GB2551226A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108710584B (zh) * 2018-05-22 2021-08-31 郑州云海信息技术有限公司 一种提高tlb刷新效率的方法
CN114595164B (zh) * 2022-05-09 2022-08-16 支付宝(杭州)信息技术有限公司 在虚拟化平台中管理tlb高速缓存的方法和装置
WO2025236116A1 (en) * 2024-05-11 2025-11-20 Yangtze Memory Technologies Co., Ltd. Data migration in memory systems

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JPS63286944A (ja) * 1987-05-20 1988-11-24 Hitachi Ltd アドレス変換バツフア無効化方式
JPH01109452A (ja) * 1987-10-22 1989-04-26 Fujitsu Ltd 変換索引バッファ情報の消去制御方式
JP2806778B2 (ja) * 1994-01-28 1998-09-30 甲府日本電気株式会社 変換索引バッファクリア命令処理方式
JP4361909B2 (ja) * 1995-03-20 2009-11-11 富士通株式会社 キャッシュコヒーレンス装置
US5906001A (en) * 1996-12-19 1999-05-18 Intel Corporation Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines
US20040117590A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Aliasing support for a data processing system having no system memory
US7073043B2 (en) * 2003-04-28 2006-07-04 International Business Machines Corporation Multiprocessor system supporting multiple outstanding TLBI operations per partition
US7188229B2 (en) * 2004-01-17 2007-03-06 Sun Microsystems, Inc. Method and apparatus for memory management in a multi-processor computer system
US7281116B2 (en) * 2004-07-30 2007-10-09 Hewlett-Packard Development Company, L.P. Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
US7454590B2 (en) * 2005-09-09 2008-11-18 Sun Microsystems, Inc. Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores
JP4908017B2 (ja) * 2006-02-28 2012-04-04 富士通株式会社 Ｄｍａデータ転送装置及びｄｍａデータ転送方法
US20120203831A1 (en) * 2011-02-03 2012-08-09 Kent Schoen Sponsored Stories Unit Creation from Organic Activity Stream
CN101398768B (zh) * 2008-10-28 2011-06-15 北京航空航天大学 一种分布式虚拟机监视器系统的构建方法
CN102262557B (zh) * 2010-05-25 2015-01-21 运软网络科技(上海)有限公司 通过总线架构构建虚拟机监控器的方法及性能服务框架
US9916257B2 (en) * 2011-07-26 2018-03-13 Intel Corporation Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
CN106708753B (zh) * 2012-03-30 2021-04-02 英特尔公司 在使用共享虚拟存储器的处理器中加速操作的装置和方法
US9081707B2 (en) * 2012-12-29 2015-07-14 Intel Corporation Apparatus and method for tracking TLB flushes on a per thread basis
US9411745B2 (en) * 2013-10-04 2016-08-09 Qualcomm Incorporated Multi-core heterogeneous system translation lookaside buffer coherency
US9619387B2 (en) * 2014-02-21 2017-04-11 Arm Limited Invalidating stored address translations
WO2016012831A1 (en) 2014-07-21 2016-01-28 Via Alliance Semiconductor Co., Ltd. Simultaneous invalidation of all address translation cache entries associated with x86 process context identifier
JP6663108B2 (ja) * 2016-02-29 2020-03-11 富士通株式会社 物理演算処理装置、情報処理装置及び情報処理装置の制御方法

Also Published As

Publication number Publication date
DE102016124749A1 (de) 2017-12-14
EP3255550A1 (en) 2017-12-13
JP2017220211A (ja) 2017-12-14
CN112286839B (zh) 2024-05-10
CN112286839A (zh) 2021-01-29
GB2551226A (en) 2017-12-13
DE202016008132U1 (de) 2017-04-24
JP6382924B2 (ja) 2018-08-29
JP2018181378A (ja) 2018-11-15
EP3255550B1 (en) 2019-04-03
DE102016124749B4 (de) 2023-08-10
JP6716645B2 (ja) 2020-07-01
EP3502906A1 (en) 2019-06-26
DK3255550T3 (da) 2019-07-15
CN107480075A (zh) 2017-12-15
GB201621246D0 (en) 2017-01-25
CN107480075B (zh) 2020-10-27
EP3502906B1 (en) 2021-06-16

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