JP6363191B2 - データマスキングを介してメモリｉ／ｏ電力を低減するためのシステムおよび方法 - Google Patents

データマスキングを介してメモリｉ／ｏ電力を低減するためのシステムおよび方法 Download PDF

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JP6363191B2
JP6363191B2 JP2016528851A JP2016528851A JP6363191B2 JP 6363191 B2 JP6363191 B2 JP 6363191B2 JP 2016528851 A JP2016528851 A JP 2016528851A JP 2016528851 A JP2016528851 A JP 2016528851A JP 6363191 B2 JP6363191 B2 JP 6363191B2
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data masking
power
data
memory
masking operation
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Japanese (ja)
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JP2016537720A (ja
JP2016537720A5 (OSRAM
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ハウ−ジン・ロ
デクスター・チュン
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1009—Data masking during input/output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
JP2016528851A 2013-11-13 2014-11-13 データマスキングを介してメモリｉ／ｏ電力を低減するためのシステムおよび方法 Expired - Fee Related JP6363191B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/079,620 2013-11-13
US14/079,620 US9383809B2 (en) 2013-11-13 2013-11-13 System and method for reducing memory I/O power via data masking
PCT/US2014/065356 WO2015073613A1 (en) 2013-11-13 2014-11-13 System and method for reducing memory i/o power via data masking

Publications (3)

Publication Number Publication Date
JP2016537720A JP2016537720A (ja) 2016-12-01
JP2016537720A5 JP2016537720A5 (OSRAM) 2017-12-07
JP6363191B2 true JP6363191B2 (ja) 2018-07-25

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JP2016528851A Expired - Fee Related JP6363191B2 (ja) 2013-11-13 2014-11-13 データマスキングを介してメモリｉ／ｏ電力を低減するためのシステムおよび方法

Country Status (6)

Country Link
US (1) US9383809B2 (OSRAM)
EP (1) EP3069345B1 (OSRAM)
JP (1) JP6363191B2 (OSRAM)
KR (1) KR20160085779A (OSRAM)
CN (1) CN105706168B (OSRAM)
WO (1) WO2015073613A1 (OSRAM)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180335828A1 (en) * 2017-05-19 2018-11-22 Qualcomm Incorporated Systems and methods for reducing memory power consumption via device-specific customization of ddr interface parameters
US10332582B2 (en) 2017-08-02 2019-06-25 Qualcomm Incorporated Partial refresh technique to save memory refresh power
JP7197998B2 (ja) 2018-05-02 2022-12-28 キヤノン株式会社 メモリコントローラおよびメモリコントローラで実施される方法
US10795830B2 (en) 2018-07-20 2020-10-06 Qualcomm Incorporated Write access control for double data rate write-x/datacopy0 commands
CN109388177B (zh) * 2018-10-15 2021-07-27 北京电子工程总体研究所 基于多内核dsp的内核间时序同步方法和数据传输方法
US11150818B2 (en) * 2019-09-11 2021-10-19 International Business Machines Corporation Memory array having power consumption characteristics
CN115565563A (zh) * 2021-07-02 2023-01-03 脸萌有限公司 存储电路、芯片、数据处理方法和电子设备
US11948625B2 (en) 2021-09-09 2024-04-02 Winbond Electronics Corporation Systems on chips, memory circuits, and methods for accessing data in a memory circuit directly using a transistor-level operation signal

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW493119B (en) 2001-03-28 2002-07-01 Via Tech Inc Method for automatically identifying the type of memory and motherboard using the same
JP2006066020A (ja) 2004-08-30 2006-03-09 Fujitsu Ltd 半導体記憶装置
US7477257B2 (en) * 2005-12-15 2009-01-13 Nvidia Corporation Apparatus, system, and method for graphics memory hub
JP2009187615A (ja) * 2008-02-05 2009-08-20 Elpida Memory Inc 半導体記憶装置
CN101673227A (zh) * 2008-09-11 2010-03-17 英业达股份有限公司 存储器位错误产生装置
US7830726B2 (en) 2008-09-30 2010-11-09 Seagate Technology Llc Data storage using read-mask-write operation
US8332876B2 (en) 2008-11-20 2012-12-11 Ati Technologies Ulc Method, system and apparatus for tri-stating unused data bytes during DDR DRAM writes
JP2011170942A (ja) 2010-02-22 2011-09-01 Elpida Memory Inc 半導体装置
JP5398664B2 (ja) 2010-08-13 2014-01-29 ルネサスエレクトロニクス株式会社 半導体メモリ
JP5876271B2 (ja) * 2011-11-01 2016-03-02 ルネサスエレクトロニクス株式会社 メモリ制御装置
US8726139B2 (en) * 2011-12-14 2014-05-13 Advanced Micro Devices, Inc. Unified data masking, data poisoning, and data bus inversion signaling

Also Published As

Publication number Publication date
CN105706168B (zh) 2018-07-03
WO2015073613A1 (en) 2015-05-21
KR20160085779A (ko) 2016-07-18
EP3069345B1 (en) 2020-07-15
JP2016537720A (ja) 2016-12-01
EP3069345A1 (en) 2016-09-21
CN105706168A (zh) 2016-06-22
US20150134989A1 (en) 2015-05-14
US9383809B2 (en) 2016-07-05

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