JP6360191B2 - Power converter - Google Patents

Description

  The present invention relates to power conversion using a semiconductor switching element, and more particularly to improvement of short-circuit tolerance.

  In order to save energy in power electronics devices, low-loss power semiconductor switching devices using wide gap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have been studied. Since SiC and GaN have a breakdown electric field strength about 10 times higher than that of silicon (Si), the thickness of the drift layer can be reduced to 1/10 of Si in the case of switching elements having the same breakdown voltage. By thinning the drift layer in this manner, the drift layer resistance can be greatly reduced, so that the on-resistance of the entire element can be reduced.

  Power semiconductor switching elements are used in power conversion devices such as inverters. In power converters, there is a possibility that a load short circuit may occur due to a malfunction or connection error, but normally the control system monitors the load current, and when the load short circuit occurs, the circuit is shut off to protect the device. To do. However, since it takes about several microseconds for the control system to detect the load short circuit and operate the protection circuit, the semiconductor switching element is exposed to high voltage and large current stress during this time.

  The load short-circuit tolerance is an index indicating a period during which a high-voltage and large-current stress can be sustained during the time until the protection circuit operates when the load is short-circuited. In general, the on-state continues for 10 microseconds when the load is short-circuited. However, the element is required not to be broken.

  The cause of the destruction of the element when the load is short-circuited is that the temperature of the element rapidly rises due to a large power loss that occurs when the load is short-circuited. In the case of a switching element using Si, since the band gap of Si is about 1.1 eV, at a temperature of 200 ° C. or higher, Si becomes an intrinsic state, loses rectification, causes thermal runaway, and destroys the element.

  In the case of a semiconductor switching element using SiC or GaN, the thickness of the drift layer can be reduced to one-tenth of that of Si, but this reduces the heat capacity of the element, so that heat generation is 10 times that of Si when the load is short-circuited. As a result, the temperature rises markedly as compared with an element using Si. In the case of wide gap semiconductors such as SiC and GaN, the intrinsic carrier density is low and theoretically does not become intrinsic even at a high temperature of 1000 ° C. However, at such high temperatures, the reliability of the elements other than the semiconductor, such as electrodes and insulating films, deteriorates remarkably, so it is necessary to perform heat dissipation design and loss control different from those using Si elements. is there.

  Patent Document 1 discloses a structure in which a load short-circuit tolerance is increased in a semiconductor switching element using a wide gap semiconductor. In the technique disclosed in Patent Document 1, an electrode having a thickness of 50 μm or more made of aluminum or an aluminum alloy is brought into contact with the element surface to enhance a heat dissipation effect, and a current detection transistor is connected in parallel with the main semiconductor switching element. A load short circuit is detected, and when the load is short circuited, the gate voltage of the main semiconductor switching element is limited.

  Patent Document 2 discloses a technique for improving the short-circuit tolerance by limiting the interval between the well regions.

JP 2006-319213 A JP 2012-33731 A

  As described above, when a power conversion device such as an inverter is operated using a semiconductor switching element, the element may be broken due to heat generated when the load is short-circuited. In particular, wide gap semiconductors such as SiC have a large temperature rise when a load is short-circuited. Therefore, it is necessary to ensure the short-circuit tolerance of the element in order to prevent the semiconductor switching element from being destroyed. When reducing the saturation current with a single semiconductor switching element to suppress loss during load short-circuiting, methods such as increasing the channel length have a trade-off relationship between saturation current and on-resistance, reducing saturation current. And the on-resistance increases. In order to reduce the loss of the semiconductor switching element, it is a problem to reduce the saturation current without increasing the on-resistance.

  The technique disclosed in Patent Document 1 includes the formation of a very thick electrode of 50 μm or more, and the number of parts is increased to limit the current when the load is short-circuited. Disadvantageous.

  In the technique disclosed in Patent Document 2, the depletion layer extends from the well region to the drift layer even during normal operation, and the current path flowing from the channel to the drift layer is limited by the depletion layer extending from the opposite well region. The on-resistance during normal operation increases. Furthermore, if the impurity concentration of the drift layer is lowered in order to ensure the breakdown voltage of the device, the depletion layer extends to the drift layer, which is disadvantageous for increasing the breakdown voltage.

  In view of the above problems, an object of the present invention is to provide a semiconductor device, a power module, and a power conversion device that can reduce saturation current without increasing on-resistance, and have low loss and a large short-circuit tolerance. It is.

  In the present invention, the above-described problem is solved by having a constricted region in which the body region and the insulating film face each other across the drift region.

  According to the present invention, there is provided a semiconductor switching element capable of reducing a saturation current without increasing an on-resistance, and having a low loss and a large short-circuit tolerance. Therefore, it is possible to suppress element destruction at the time of load short-circuiting of a power conversion device using this element, and it is possible to provide a power module and a power conversion device with low loss and high reliability.

It is a figure which shows the structure of IGBT of the comparative example of the Example of this invention. It is a top view of the n channel IGBT chip | tip which is a semiconductor device of the Example of this invention. It is an enlarged top view for demonstrating a unit active cell. It is a figure corresponding to the A-A 'section of Drawing 3 for explaining a unit active cell. It is an expanded sectional view for demonstrating a constriction area | region. It is a figure which shows the relationship between the space | interval W of the body area | region in a constriction area | region, and a gate insulating film, and a saturation current. It is a figure which shows the current-voltage characteristic of n channel IGBT when the space | interval W of the body region in a constriction area | region and a gate insulating film is changed. It is a figure for demonstrating the cross-section of n channel IGBT which concerns on the 2nd Example of this invention. It is a figure for demonstrating the constriction area | region of n channel IGBT which concerns on the 2nd Example of this invention. It is a figure for demonstrating the cross-section of n channel IGBT which concerns on the 3rd Example of this invention. It is a figure for demonstrating the power converter device which concerns on the 4th Example of this invention. It is a figure for demonstrating the power converter device which concerns on the 5th Example of this invention. It is a figure which shows the circuit structure of the three-phase motor system which concerns on the 6th Example of this invention. It is a figure which shows the motor drive system of the railway vehicle which concerns on the 7th Example of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a top view of an n-channel insulated gate bipolar transistor (IGBT) chip which is a semiconductor device according to an embodiment of the present invention. A termination region 101 is provided in the peripheral region of the semiconductor chip so as to go around the end of the chip, and most of the inner region is an active region 102 and a gate pad region 103. In the active region 102, unit active cells 104 of transistors are laid. Note that the unit active cells 104 are spread over the entire active area 102, but in FIG. 2, the unit active cells 104 are displayed only in the central portion for easy viewing of the drawing. FIG. 3 is an enlarged top view for explaining the unit active cell 104. FIG. 4 is a diagram corresponding to the A-A ′ cross section of FIG. 3 for explaining the unit active cell 104.

As shown in FIG. 4, in the semiconductor device of this example, an n ⁻ type drift region 4 containing nitrogen, phosphorus, etc. is formed in the SiC substrate on the first main surface side of the SiC substrate, and the lower part thereof That is, an n-type buffer region 3 containing nitrogen, phosphorus or the like is formed on the second main surface side of the SiC substrate. Here, “−” and “+” are signs representing the relative impurity concentration of conductivity type of n-type or p-type. For example, in the case of n-type, “n ⁻ ”, “n”, “n” The impurity concentration of the n-type impurity increases in the order of “ ⁺ ” and “n ⁺⁺ ”. The buffer region 3 is not necessarily required, but is provided for improving the breakdown voltage and suppressing conduction loss. A p ⁺ -type collector region 2 containing aluminum or boron is formed below the buffer region 3, and a collector electrode 1 is provided below the p ⁺ -type collector region 2.

A p-type body region 5 containing aluminum, boron, or the like is formed inside the drift region 4. An n ⁺ -type emitter region 6 containing nitrogen, phosphorus, etc., and aluminum, boron, etc. are formed inside the body region 5. A p ⁺ -type emitter region 7 is formed. A gate insulating film 8 is formed so as to cover a part of the n ⁺ -type emitter region 6, the body region 5, and the drift region 4, and a gate electrode 9 is provided so as to cover the gate insulating film 8. ing. An emitter electrode 10 is formed so as to cover the remaining part of the n ⁺ -type emitter region 6 and the p ⁺ -type emitter region 7, and an interlayer insulating film 11 is formed to insulate the gate electrode 9 from the emitter electrode 10. Is formed.

A trench structure 12 is formed in an intermediate region between adjacent body regions 5 inside the drift region 4, and a constriction region 13 is provided in which the body region 5 and the gate insulating film 8 face each other with the drift region 4 interposed therebetween. It has been. Here, the side walls and the bottom surface of the trench structure 12 are boundaries between the gate insulating film 8 and the drift layer 4. That is, the sidewall of the trench structure 12 has the gate insulating film 8. When the element structure is viewed from the top, as shown in FIG. 3, the drift layer 4, the body region 5, and the emitter region 6 exist along the longitudinal direction of the trench structure 12. Therefore, the body region 5 exists in the short direction of the trench structure 12 at a distance from the trench structure 12. As shown in FIG. 3, it is desirable that the end portion 14 in the longitudinal direction of the trench structure 12 is in contact with the body region 5. Thereby, the gate insulating film 8 and the body region 5 are in contact with each other at the end portion 14 in the longitudinal direction of the trench structure 12, and it is possible to prevent current from flowing through the end portion 14 in the longitudinal direction. Can be improved. Further, in this embodiment, the body region 5 is continuously formed up to the portion in contact with the end portion 14 in the longitudinal direction of the trench structure 12, but the impurity concentration in the vicinity of the end portion 14 of the body region 5 is set to the body region 5 . By further increasing the impurity concentration in other portions, the effect of suppressing the saturation current can be further improved.

  The collector electrode 1 can be formed by a method such as sputtering or metal vapor deposition using a metal such as aluminum, titanium, nickel, or gold. For example, the collector region 2, the buffer region 3, and the drift region 4 may be formed by epitaxially growing the collector region 2, the buffer region 3, and the drift region 4 on the n-type or p-type bulk substrate in this order and then grinding the bulk substrate. It can be formed by grinding the bulk substrate after epitaxial growth in the order of the drift region 4, the buffer region 3, and the collector region 2 on the n-type or p-type bulk substrate.

The impurity concentration of the collector region 2 is, for example, 1 × 10 18 cm −3 or more. The impurity concentration of the buffer region 3 is, for example, a value lower than the impurity concentration of the collector region 2. The impurity concentration of the drift region 4 is, for example, less than 5 × 10 15 cm −3. The body region 5 can be formed in the drift region by , for example, impurity implantation or epitaxial growth. The emitter region 6 is a region formed by, for example, implanting impurities so as to have a high concentration of 1 × 10 19 cm −3 or more. The trench structure 12 can be formed by, for example, dry etching. The gate insulating film 8 can be formed, for example, by wet oxidation, dry oxidation, or CVD (Chemical Vapor Deposition) of a silicon oxide film (SiO 2 film) after dry etching for forming the trench structure 12.

The gate electrode 9 is an electrode region formed by, after forming the gate insulating film 8, directly after CVD of polysilicon or CVD of amorphous silicon, and denatured into polysilicon by heat treatment. The interlayer insulating film 11 can be formed by CVD or the like of a silicon oxide film (SiO ₂ film), and the emitter electrode 10 is formed by sputtering or metal vapor deposition using a metal such as aluminum, titanium, or nickel. can do.

  FIG. 5 shows an enlarged cross-sectional view near the constriction region 13. In this embodiment, the length L of the gate insulating film 8 facing the body region 5 in the narrowed region 13 is made longer than the interval W between the body region 5 and the gate insulating film 8 in the narrowed region 13. In the present embodiment, the length L of the gate insulating film facing the body region 5 corresponds to the depth of the trench structure 12. The length L of the gate insulating film is, for example, 0.65 μm, and the interval W is, for example, 0.5 μm.

  When the load is short-circuited, a power supply voltage is applied between the collector and emitter of the element, and the current flowing at that time is usually determined by the saturation current characteristic of the channel portion. In the present embodiment, the current flowing from the emitter region 6 through the channel to the drift region 4 is restricted by the constriction region 13, whereby the current flowing to the element when the load is short-circuited can be suppressed. Since the path of the current flowing from the channel to the drift region 4 spreads within the drift region 4 at an angle of about 45 °, the path of the current flowing to the drift region 4 is limited by making the length L longer than the interval W. be able to. Further, in the present embodiment, as described above, the trench structure 12 and the body region 5 are in contact with each other at the end portion 14 in the longitudinal direction of the trench structure 12, and the current path other than the constriction region 13 can be narrowed. The suppression effect can be further improved.

Next, considering the normal operation, since a depletion layer extends from the body region 5 into the drift region 4 in the constriction region 13, the current flowing through the constriction region 13 is suppressed. On the other hand, when a voltage is applied to the gate electrode, an accumulation layer having a high electron concentration is formed in the region in contact with the gate insulating film 8 in the drift region 4, so that the drift region passes from the emitter region 6 through the channel. After flowing through the channel, the current flowing through 4 flows to the drift region 4 through the accumulation layer. Since the accumulation layer has a high electron concentration, the current flows through the constricted region 13 with almost no suppression, and an increase in on-resistance can be prevented.

The results of a computer experiment modeling the IGBT of this example are shown in FIGS. FIG. 6 shows the relationship between the interval W and the saturation current density. In this computer experiment, the saturation current density is calculated when the length L is 0.65 μm, the gate voltage is 15 V, and the collector voltage is half the withstand voltage. As shown in FIG. 6, in a region where the interval W is as large as a micron order, the saturation current density decreases only slightly even if the interval W decreases. On the other hand, when the interval W is less than 1 μm, the saturation current density decreases as the interval W decreases, and when the interval W is near 0.65 μm, the saturation current density decreases rapidly. Thus, the effect of reducing the saturation current density can be obtained by setting the interval W, which is the width of the constriction region, to less than 1 μm, that is, by setting the interval W to a submicron or less. Further, by making the length L longer than the interval W, it is possible to sufficiently suppress the current flowing through the element when the load is short-circuited. FIG. 7 shows the relationship between the collector-emitter voltage and the collector current density. When the length L is 0.65 μm and the interval W is 1.0 μm is indicated by a one-dot chain line, the interval W is 0.5 μm is indicated by a broken line, and the IGBT structure without the constriction region shown in FIG. The solid lines indicate the calculation results. For example, the ON voltage at a collector current density of 100 A / cm ² is 3.6 V.

As described above, the semiconductor device of this embodiment has a constricted region in which the body region and the insulating film are opposed to each other with the drift region interposed therebetween, thereby sufficiently reducing the saturation current and suppressing an increase in on-voltage. It becomes possible. Since the present invention relates to an insulated gate structure on the element surface, the present invention is not limited to an IGBT, and can be applied to a semiconductor switching element having an insulated gate structure such as a metal oxide semiconductor field effect transistor (MOSFET). When applied to the MOSFET, the p ⁺ -type collector region 2 of this embodiment is not provided. Further, the present invention is not limited to the n-type channel structure but can be applied to a p-type channel structure. As a semiconductor material used in the semiconductor device, for example, Si or GaN can be applied in addition to the SiC of this embodiment.

  FIG. 8 shows a cross-sectional structure of an n-channel IGBT according to the second embodiment of the present invention. FIG. 9 shows an enlarged view of the vicinity of the constriction region 13 of this embodiment. In this embodiment, as shown in FIG. 9, the length L of the gate insulating film in the narrowed region 13 is set to the length of the body region in the narrowed region 13, that is, the depth of the body region 5. It is shorter than the length D. Others are the same as those in the first embodiment, and thus the description thereof is omitted.

  As in this embodiment, the end portion of the gate insulating film 8 is present in the region sandwiched between the body regions 5, so that the electric field generated in the gate insulating film 8 during the off operation can be relaxed and the reliability of the gate insulating film 8 can be reduced. It becomes possible to improve the property.

FIG. 10 shows a cross-sectional structure of an n-channel IGBT according to the third embodiment of the present invention. In the third embodiment, an n ⁻ type drift region 4 containing nitrogen, phosphorus or the like is formed on the SiC substrate, and an n type buffer region 3 containing nitrogen, phosphorus or the like is formed below the n ⁻ type drift region 4. A p ⁺ -type collector region 2 containing aluminum or boron is formed below the buffer region, and a collector electrode 1 is provided below the p ⁺ -type collector region 2. A p-type body region 5 containing aluminum, boron, or the like is formed inside the drift region 4. The body region 5 contains an n ⁺ -type emitter region 6 containing nitrogen, phosphorus, etc., and aluminum, boron, etc. A p ⁺ -type emitter region 7 is formed. By forming the trench structure 12 in the region where the body region 5 in the drift region 4 is opposed, the constriction region 13 in which the body region 5 and the gate insulating film 8 are opposed to each other across the drift region 4 is provided. . Gate insulating film 8 is formed so as to cover part of emitter region 6, body region 5, and drift region 4. A first gate electrode 9 a is provided so as to cover the gate insulating film 8, and a second gate electrode 9 b is provided so as to cover the gate insulating film 8 in the narrowed region 13. The first gate electrode 9a and the second gate electrode 9b can be formed, for example, by depositing polysilicon or the like and patterning it by dry etching, as in the first embodiment.

Further, an emitter electrode 10 is formed so as to cover the remaining part of the emitter region 6 and the p ⁺ -type emitter region 7, and the first gate electrode 9a, the second gate electrode 9b, and the emitter electrode 10 are connected to each other. An interlayer insulating film 11 is formed for insulation.

  As in this embodiment, the gate electrode is separated into two, the inversion layer is controlled by one gate electrode, and the storage layer is controlled by the other gate electrode, so that the gate capacitance is reduced and the inversion layer is controlled. It is possible to improve the switching speed.

  The structure of the gate electrode of this embodiment can be applied to other semiconductor switching elements having an insulated gate structure such as a MOSFET, and can be applied not only to an n-type channel structure but also to a p-type channel structure. The semiconductor material can be applied to, for example, Si or GaN other than the SiC exemplified in this embodiment.

  In this embodiment, as shown in FIG. 11, the gate voltage 111 is always applied to the second gate electrode 9b for controlling the storage layer, and the first gate electrode 9a is applied to the semiconductor device of the third embodiment. This is a power conversion device for switching elements by connecting the output of the gate drive circuit 110.

  In the power conversion device of this embodiment, the storage layer is always generated during the device operation using the second gate electrode 9b, and the element is switched by repeating generation and disappearance of the inversion layer using the first gate electrode 9a. As a result, an increase in gate capacitance can be suppressed and the switching speed can be improved.

  In the power conversion apparatus of this embodiment, as shown in FIG. 12, a first gate electrode 9a and a second gate electrode 9b are connected via a resistor 112 and an inductor 113, and the first gate electrode 9a is driven by a gate. The output of the circuit 110 is connected.

  In the power converter of this embodiment, the power module is provided with a single gate terminal, and the output of the gate drive circuit 110 is connected to the gate terminal. Thereby, the gate control signal from the gate drive circuit 110 is input to the first gate electrode 9a. Further, a second gate electrode 9b is connected to the gate terminal via a resistor 112 and an inductor 113, and a gate control signal delayed by the resistor 112 and the inductor 113 is input to the second gate electrode 9b. The gate voltage is set to be applied to the second gate electrode 9b in the initial state, and the gate control signal is switched faster than the delay due to the resistor 112 and the inductor 113 during the operation of the element, so that the second gate electrode 9b is always switched. It can be kept on. Therefore, it is possible to input different control signals to the first gate electrode 9a and the second gate electrode 9b using one gate terminal of the power module, thereby suppressing an increase in gate capacitance and improving the switching speed. It becomes possible.

  In addition, since the resistor 112 and the inductor 113 can be incorporated in a power module using a semiconductor switching element, the gate drive circuit 110 provided outside can be simplified. Therefore, the cost of the power conversion device can be reduced.

  The sixth embodiment is a three-phase motor system to which the semiconductor switching element, power module, or power converter according to the first to fifth embodiments of the present invention is applied.

FIG. 13 shows a circuit configuration of the three-phase motor system of the present embodiment. In the three-phase motor system of the present embodiment converts the alternating current electric energy of the DC power supply by the inverter and variable speed controls the rotational speed of the three-phase motor 20 8. In each phase of the U terminal 205, the V terminal 206, and the W terminal 207, the upper arm portion 201a and the lower arm portion 201b are connected in series, and three series connection circuits thereof are connected in parallel. Each arm unit 201 includes a semiconductor switching element 202 such as an IGBT and a free wheel diode 203, for example.

  By applying the semiconductor switching elements, power modules, or power converters of the first to fifth embodiments of the present invention to the upper arm portion 201a and the lower arm portion 201b of FIG. When a load short-circuit occurs due to factors such as the above, it is possible to suppress the heat generation of the element that occurs when the load is short-circuited. Therefore, destruction of the element due to heat can be prevented until the protection circuit operates when the load is short-circuited, and the reliability of the power conversion device can be improved.

The power conversion device to which the semiconductor switching element with increased short-circuit tolerance of the present invention is applied can be applied to, for example, a railway vehicle. FIG. 14 shows a block diagram of an example of a three-phase motor system applied to a railway vehicle. For example, a high voltage alternating current of 25 kV or 15 kV flows through the overhead line 301, and electric power is supplied to the railway vehicle via the pantograph 302. The high-voltage alternating current supplied to the railway vehicle is stepped down to, for example, 3.3 kV alternating current by the insulated main transformer 303 and then forward converted to 3.3 kV direct current by the converter 305. Thereafter, the DC is converted to AC by the inverter 307 through the capacitor 306, the desired three-phase alternating current is outputted to the three-phase motor 20 8, a three-phase motor 20 8 is driven.

  By applying the semiconductor switching element, power module, or power converter of the first to fifth embodiments to the converter 305 or the inverter 307 constituting the three-phase motor system of the railway vehicle, low power consumption and high reliability are achieved. It becomes possible to provide a high-speed railway vehicle.

1: collector electrode, 2: p ⁺ type collector region, 3: n type buffer region, 4: n ⁻ type drift region, 5: p type body region, 6: n ⁺ type emitter region, 7: p ⁺ type emitter region 8: Gate insulating film, 9: Gate electrode, 10: Emitter electrode, 11: Interlayer insulating film, 12: Trench structure, 13: Narrow region, 14: Termination portion in the longitudinal direction of the trench structure.

Claims (9)

A power conversion device having a semiconductor device,
The semiconductor device includes:
A semiconductor substrate having a first main surface and a second main surface;
A drift region provided on the first main surface side in the semiconductor substrate;
A first electrode provided on the second main surface side;
A body region provided in the drift region;
A trench provided in the drift region and spaced apart from the body region, and having a sidewall of an insulating film;
The body region and the drift region, a first gate electrode facing each other across the insulating film,
A second gate electrode provided inside the trench and insulated from the first gate electrode;
A semiconductor region entirely contained within the body region;
The insulated from the first gate electrode and the second gate electrode, and a second electrode connected to a part of the semiconductor region,
The spacing is less than 1 μm and shorter than the depth of the trench;
The longitudinal end of the trench is in contact with the body region;
The impurity concentration in the vicinity of the end portion of the body region is higher than the impurity concentration in other portions of the body region,
The first gate electrode is directly connected to a terminal connected to the output of the gate driving circuit;
The second gate electrode is connected to the same terminal as the terminal via a resistor and an inductor;
In an initial state, a voltage is applied to the second gate electrode,
During the operation of the power converter, the control signal from the gate drive circuit to the first gate electrode and the second gate electrode is switched faster than the delay of the control signal by the resistor and the inductor. The power converter characterized by this. The power conversion device according to claim 1,
The power converter according to claim 1, wherein a depth of the body region is larger than a depth of the trench. The power conversion device according to claim 1,
The semiconductor device includes:
A collector region provided on the second main surface side and having a conductivity type different from that of the drift region;
The power converter according to claim 1, wherein the collector region is connected to the first electrode. The power conversion device according to claim 1,
The power conversion device, wherein the semiconductor substrate contains silicon carbide. A power conversion device having a semiconductor device,
The semiconductor device includes:
A semiconductor substrate having a first main surface and a second main surface;
A first semiconductor region having a first conductivity type provided on the first main surface side in the semiconductor substrate;
A first electrode provided on the second main surface side;
A second semiconductor region having a second conductivity type different from the first conductivity type provided in the first semiconductor region;
A trench provided in the first semiconductor region and having a sidewall of an insulating film;
The said first semiconductor region second semiconductor region, a first gate electrode facing each other across the insulating film,
A second gate electrode provided inside the trench and insulated from the first gate electrode;
A fifth semiconductor region which is entirely contained in the second semiconductor region and has the first conductivity type;
A second electrode insulated from the first gate electrode and the second gate electrode and connected to a part of the fifth semiconductor region,
In the short direction of the trench, there is the second semiconductor region spaced apart from the trench,
An end of the trench in a longitudinal direction is in contact with a third semiconductor region having the second conductivity type;
The impurity concentration in the vicinity of the end of the third semiconductor region is higher than the impurity concentration in other portions of the third semiconductor region,
The first gate electrode is directly connected to a terminal connected to the output of the gate driving circuit;
The second gate electrode is connected to the same terminal as the terminal via a resistor and an inductor;
In an initial state, a voltage is applied to the second gate electrode,
During the operation of the power converter, the control signal from the gate drive circuit to the first gate electrode and the second gate electrode is switched faster than the delay of the control signal by the resistor and the inductor. The power converter characterized by this.   The power conversion device according to claim 5,
  The power conversion device, wherein the second semiconductor region and the third semiconductor region are continuous.   The power conversion device according to claim 5,
  The semiconductor device includes:
  A fourth semiconductor region having the second conductivity type provided on the second main surface side;
  The power conversion device, wherein the fourth semiconductor region is connected to the first electrode.   The power conversion device according to claim 5,
  The power conversion device, wherein the semiconductor substrate contains silicon carbide.   A power conversion device having a semiconductor device,
  The semiconductor device includes:
  A semiconductor substrate having a first main surface and a second main surface;
  A drift region provided on the first main surface side in the semiconductor substrate;
  A first electrode provided on the second main surface side;
  A body region provided in the drift region;
  A gate insulating film provided on the body region and the drift region, and having a trench;
  A first gate electrode facing the drift region and the body region with the gate insulating film interposed therebetween;
  A second gate electrode provided inside the trench and insulated from the first gate electrode;
  A semiconductor region entirely contained within the body region;
  A second electrode insulated from the first gate electrode and the second gate electrode and connected to a part of the semiconductor region,
  The body region and the sidewall of the trench face each other with an interval of less than 1 μm,
  The longitudinal end of the gate insulating film is in contact with the body region,
  The impurity concentration in the vicinity of the end portion of the body region is higher than the impurity concentration in other portions of the body region,
  The first gate electrode is directly connected to a terminal connected to the output of the gate driving circuit;
  The second gate electrode is connected to the same terminal as the terminal via a resistor and an inductor;
  In an initial state, a voltage is applied to the second gate electrode,
  During the operation of the power converter, the control signal from the gate drive circuit to the first gate electrode and the second gate electrode is switched faster than the delay of the control signal by the resistor and the inductor. The power converter characterized by this.

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