JP6511125B2 - Semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device and a power converter.

  As background art of this technical field, there are JP, 2011-138952, A (patent documents 1) and JP, 2004-134644 (patent documents 2).

  In JP 2011-138952 A (patent document 1), a growth layer made of Si crystal is formed by epitaxial growth on the surface of a substrate portion made of SiC crystal, and the first and second conductive type first and second layers are formed in the growth layer. An SiC power transistor is described which forms a region of and a channel region of a second conductivity type.

  JP-A-2004-134644 (Patent Document 2) discloses carbonization in which a semiconductor layer having a band gap different from that of silicon carbide is formed between the channel region formed in the surface layer of the epitaxial layer and the gate insulating film. A silicon semiconductor device is described.

JP, 2011-138952, A JP 2004-134644 A

  In a power metal / insulator / semiconductor field effect transistor (MISFET) that is one of power semiconductor devices, a planar type using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) Power MISFET (hereinafter referred to as SiC power MISFET) is used. SiC power MISFETs have attracted particular attention in the field of power saving or environmentally friendly inverter technology because they can be made high withstand voltage and low loss.

  By the way, in the SiC power MISFET, a gate insulating film is formed on the channel region of the surface layer portion of the epitaxial layer made of SiC formed on the surface of the SiC substrate. However, when forming the gate insulating film, C—C bonds or Si—Si bonds are formed in the epitaxial layer due to strain, and the bottom (or edge) of the conduction band at the interface between the epitaxial layer and the gate insulating film. There is a change in Quantum Roughness.

  This causes the SiC power MISFET to have problems such as deterioration of channel mobility, deterioration of subthreshold characteristics, and fluctuation of threshold voltage.

  In order to solve the above problems, the SiC power MISFET according to the present invention has a silicon (Si) atomic layer between the channel region formed in the surface layer portion of the epitaxial layer made of SiC and the gate insulating film. The silicon (Si) atomic layer consists of one atomic layer. By forming a silicon (Si) atomic layer, C—C bonds and Si—Si bonds are less likely to be formed on the surface layer portion of the epitaxial layer, and the occurrence of quantum roughness at the interface between the epitaxial layer and the gate insulating film is suppressed. Be done.

According to the present invention, a SiC power MISFET with stable operating characteristics can be provided.
Problems, configurations, and effects other than those described above will be apparent from the description of the embodiments below.

FIG. 6 is a layout diagram in which basic cells of the SiC power MISFET according to Example 1 are arranged in 3 rows × 3 columns. FIG. 6 is a plan view of relevant parts showing two basic cells of the SiC power MISFET according to Embodiment 1 in an enlarged manner. It is principal part sectional drawing (sectional drawing in alignment with the II line of FIG. 2) which shows the basic cell of the SiC power MISFET by Example 1. FIG. 5 is a schematic view showing an interface between an epitaxial layer made of SiC and a gate insulating film according to Example 1 in an enlarged manner. FIG. FIG. 7 is a main-portion cross-sectional view showing an example of a manufacturing process of the SiC power MISFET according to Example 1; FIG. 6 is a cross-sectional view of main parts showing a manufacturing process of the SiC power MISFET subsequently to FIG. 5; FIG. 7 is a cross-sectional view of main parts showing a manufacturing process of the SiC power MISFET subsequently to FIG. 6; FIG. 8 is a cross-sectional view of main parts showing a manufacturing process of the SiC power MISFET subsequently to FIG. 7; FIG. 9 is a cross-sectional view of main parts showing a manufacturing process of the SiC power MISFET subsequently to FIG. 8; FIG. 10 is a cross-sectional view of main parts showing a manufacturing process of the SiC power MISFET subsequently to FIG. 9; It is an equivalent circuit schematic which shows the 1st example of the power converter device (inverter) which used the SiC power MISFET by Example 1 as a switching element. It is an equivalent circuit schematic which shows the 2nd example of the power converter device (inverter) which used the SiC power MISFET by Example 1 as a switching element. It is an equivalent circuit schematic which shows an example which applied the power converter device (converter and inverter) which used the SiC power MISFET by Example 1 as a switching element to the motor drive for railways. When driving the SiC power MISFET mounted in the power converter used for the three phase motor drive by Example 1, it is a voltage waveform figure applied to the gate of SiC power MISFET. FIG. 18 is a cross-sectional view of essential parts showing a basic cell of a SiC power MISFET according to Example 2; FIG. 18 is a main-portion cross-sectional view showing an example of the manufacturing process of the SiC power MISFET according to Example 2; FIG. 17 is a main-portion cross-sectional view showing the manufacturing process of the SiC power MISFET, following FIG. 16; FIG. 18 is a cross-sectional view of a main portion showing the manufacturing process of the SiC power MISFET subsequently to FIG. 17; FIG. 20 is a top view of the relevant part of a semiconductor chip on which the SiC power MISFET according to the third embodiment is mounted. FIG. 20 is a top view of the essential part of a semiconductor wafer on which a plurality of semiconductor chips mounted with the SiC power MISFETs according to Example 3 are formed. It is principal part sectional drawing along the AA of FIG. FIG. 21 is a plan view of relevant parts showing a basic cell region (four basic cells) of the SiC power MISFET according to Example 3 (a plan view enlarging a region B of FIG. 19). FIG. 21 is a main-portion cross-sectional view showing an example of the manufacturing process of the SiC power MISFET according to Example 3; FIG. 24 is an essential part cross-sectional view showing the manufacturing process of the SiC power MISFET, following FIG. 23; FIG. 25 is a plan view of relevant parts showing the manufacturing process of the SiC power MISFET continued from FIG. 24;

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but unless specifically stated otherwise, they are not unrelated to each other, one is the other And some or all of the variations, details, and supplementary explanations.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are particularly clearly shown and where they are considered to be obviously essential in principle. Needless to say.

  In addition, when we say “consists of A”, “consists of A”, “have A”, and “include A”, except for those cases where it is clearly stated that it is only that element, etc., the other elements are excluded. It goes without saying that it is not something to do. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

  In the drawings used in the following embodiments, even a plan view may be hatched to make it easier to see. Further, in all the drawings for describing the following embodiments, components having the same function are denoted by the same reference symbols in principle, and the repetitive description thereof will be omitted. Hereinafter, the present embodiment will be described in detail based on the drawings.

  «Structure of SiC power MISFET»

  The structure of the SiC power MISFET according to the first embodiment will be described with reference to FIGS. 1, 2 and 3. FIG. FIG. 1 is a layout diagram in which basic cells of the SiC power MISFET according to the first embodiment are arranged in 3 rows × 3 columns. FIG. 2 is a plan view of relevant parts showing two basic cells of the SiC power MISFET according to the first embodiment in an enlarged manner. FIG. 3 is a sectional view of an essential part showing a basic cell of the SiC power MISFET according to the first embodiment (a sectional view taken along the line I-I of FIG. 2). The SiC power MISFET is a planar type DMOS (Double diffused Metal Oxide Semiconductor) MISFET.

As shown in FIGS. 1, 2 and 3, n ^{− made of} SiC having a lower impurity concentration than n ⁺ SiC substrate 1 on the surface (first main surface) of n ⁺ SiC substrate 1 made of SiC. -type epitaxial layer 2 is formed, n ⁺ -type SiC substrate 1 and the n ^- SiC epitaxial substrate 3 -type epitaxial layer 2 which is formed. The n ⁺ -type SiC substrate 1 is a region functioning as a drain layer, and its impurity concentration is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The thickness of the n ⁻ -type epitaxial layer 2 is, for example, about 5.0 to 20.0 μm, and the impurity concentration thereof is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ .

In the n ⁻ -type epitaxial layer 2, a plurality of p-type body regions (well regions) 4 are formed spaced apart from each other with a predetermined depth from the surface of the n ⁻ -type epitaxial layer 2. The depth of the p-type body region 4 from the surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.5 to 2.0 μm, and the impurity concentration thereof is, for example, 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^−3. It is an extent.

In p type body region 4, n ⁺ type source region 5 (an area shown by hatching in FIGS. 1 and 2) has a predetermined depth from the surface of n ⁻ type epitaxial layer 2. It is formed. The n ⁺ -type source region 5 is formed in the p-type body region 4 so as to be separated from the end side surface of the p-type body region 4, and from the surface of the n ⁻ -type epitaxial layer 2 of the n ⁺ -type source region 5. The depth is, for example, about 0.1 to 0.5 μm, and the impurity concentration thereof is, for example, about 1 × 10 ²⁰ cm ⁻³ .

Further, ap ⁺ -type potential fixing region 6 for fixing the potential of the p-type body region 4 is formed. The depth of the p ⁺ -type potential fixed region 6 from the surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.1 to 0.5 μm, and the impurity concentration thereof is, for example, about 1 × 10 ²⁰ cm ^−3. .

A region sandwiched between the p-type body regions 4 adjacent to each other is a portion functioning as a JFET (Junction Field Effect Transistor) region (doping region) 7. The impurity concentration of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ⁻³ and is set higher than the impurity concentration of the n ⁻ -type epitaxial layer 2. Further, the end side surface of p type body region 4 (the interface between JFET region 7 and p type body region 4) and the end side surface of n ⁺ type source region 5 (p type body region 4 and n ⁺ type source region 5) P-type body region 4 located between the

In the n ⁻ -type epitaxial layer 2, a region in which the p-type body region 4 and the JFET region 7 are not formed is a region which functions as a drift layer serving to secure a withstand voltage.

Note that “ ⁻ ” and “ ⁺ ” are symbols indicating relative impurity concentration of n type or p type conductivity type, and for example, n type in the order of “n ⁻ ”, “n” and “n ⁺ ” The impurity concentration of the impurity is increased, and the impurity concentration of the p-type impurity is increased in the order of “p ⁻ ”, “p” and “p ⁺ ”.

A gate insulating film 10 is formed on the channel region 8. The gate insulating film 10 is composed of a lower insulating film and an upper insulating film. For example lower insulating film a first silicon oxide (SiO ₂₎ film (hereinafter, referred to as a first 1SiO ₂ film) 10A, an upper insulating film a second silicon oxide (SiO ₂₎ film (hereinafter, referred to as a first 2SiO ₂ film 10 B), but their relative dielectric constants or densities are different. The thickness of the first SiO ₂ film 10A is, for example, about 1.5 nm, and the thickness of the _second SiO ₂ film 10B is, for example, about 50 to 100 nm.

Furthermore, between the n ⁻ -type epitaxial layer 2 and the gate insulating film 10, a silicon (Si) atomic layer (hereinafter referred to as a Si atomic layer) 9A is formed. The Si atomic layer 9A is preferably an atomic layer in which silicon (Si) atoms are uniformly formed, but silicon (Si) atoms may be formed in an island shape. The structures of the Si atomic layer 9A and the gate insulating film 10 will be described in detail later with reference to FIG.

  A gate electrode 11 is formed on the gate insulating film 10. The gate electrode 11 is formed in a lattice shape in plan view, and is formed so as to surround the p-type body region 4.

The gate insulating film 10 and the gate electrode 11 are covered with an interlayer insulating film 12. A part of the n ⁺ -type source region 5 and the p ⁺ -type potential fixing region 6 are exposed at the bottom of the opening 13 formed in the interlayer insulating film 12, and a metal silicide layer 14 is formed on these surfaces.

Furthermore, a part of n ⁺ -type source region 5 and p ⁺ -type potential fixing region 6 are electrically connected to source wiring electrode 15 through metal silicide layer 14, and the back surface of SiC substrate 1 (second main surface Is electrically connected to the drain wiring electrode 17 via the metal silicide layer 16. Although illustration is omitted, similarly, the gate electrode 11 is electrically connected to the gate wiring electrode. A source potential is externally applied to the source wiring electrode 15, a drain potential is externally applied to the drain wiring electrode 17, and a gate potential is externally applied to the gate wiring electrode 17.

In the first embodiment, the upper layer of the gate insulating film 10 is formed of the silicon oxide (SiO ₂ ) film (the _second SiO ₂ film 10B), but the present invention is not limited to this. The upper layer of the gate insulating film 10 is an insulating film having a dielectric constant higher than that of a silicon oxide (SiO ₂ ) film, for example, a high material such as silicon oxynitride (SiNO) or hafnium oxide (HfO ₂ ) -based material. It is desirable to be composed of a dielectric constant insulating film (High-k insulating film). When the upper layer of the gate insulating film 10 is made of, for example, a high dielectric constant insulating film such as a hafnium oxide (HfO ₂ ) based material, the gate electrode 11 is made of, for example, a metal film such as titanium nitride (TiN). In this case, the Si atomic layer 9A, the gate insulating film (the first SiO ₂ film 10A and the high dielectric constant insulating film), and the metal gate are formed on the surface of the n ⁻ -type epitaxial layer 2 made of, for example, SiC.

  Further, the layout of the SiC power MISFET in the element formation region is not limited to those shown in FIGS. 1 and 2. For example, a plurality of p-type body regions 4 are spaced apart from each other in the first direction X and extend along the second direction Y, and a plurality of gate electrodes 11 are disposed between the adjacent p-type body regions 4 The layout may be arranged to extend along the first direction Y.

Next, features of the SiC power MISFET according to the first embodiment will be described with reference to FIG. FIG. 4 is a schematic view showing the interface between the n ⁻ -type epitaxial layer 2 made of SiC according to the first embodiment and the gate insulating film 10 in an enlarged manner.

The SiC power MISFET according to the first embodiment is characterized in that a Si atomic layer 9A is formed between the n ^-- type epitaxial layer 2 and the gate insulating film 10.

As shown in FIG. 4, a Si atomic layer 9A is formed between the n ⁻ -type epitaxial layer 2 and the first SiO ₂ film 10A. The Si atomic layer 9A is formed of one atomic layer (atomic layer), and the thickness thereof is about 0.5 nm.

The silicon (Si) of the Si atomic layer 9A combines with the silicon (Si) of the n ⁻ -type epitaxial layer 2 to form a Si—Si bond. The Si atomic layer 9A has a function as a buffer layer that reduces the strain caused by heat and suppresses the movement of carbon (C) of the n ⁻ -type epitaxial layer 2.

Further, on the Si atomic layer 9A, the Si atomic layer 9B which constitutes a part of the first SiO ₂ film 10A is formed. The silicon (Si) of the Si atomic layer 9B reacts with oxygen (O) to form silicon oxide (SiO ₂ ), that is, a part of the first SiO ₂ film 10A. The Si atomic layer 9B is formed of one atomic layer (atomic layer), and the thickness thereof is about 0.5 nm.

In general, a silicon oxide (SiO ₂ ) film constituting the gate insulating film 10 is formed by a thermal CVD method. However, when a silicon oxide (SiO ₂ ) film is formed directly on the Si atomic layer 9A by thermal CVD, oxygen (O) does not bond well to the dangling bonds of silicon (Si) in the Si atomic layer 9A. The Si—O bond of the atomic layer 9A may be unstable, and the movement of carbon (C) of the n ⁻ -type epitaxial layer 2 may not be suppressed.

Therefore, a Si atomic layer 9B is further formed on the Si atomic layer 9A, and oxygen (O) is bonded to silicon (Si) of the Si atomic layer 9B by a thermal oxidation method to form a first SiO ₂ film 10A. Thereby, the Si-Si bond between the n ^-- type epitaxial layer 2 and the Si atomic layer 9A is stabilized, so that the movement of carbon (C) in the n ^-- type epitaxial layer 2 can be suppressed. Then, since the form via the first 1SiO ₂ film 10A on the Si atom layer 9A thick silicon oxide (SiO ₂₎ film (e.g., a 2SiO ₂ film 10B shown in FIG. 3), n ^- -type epitaxial layer 2 and the Si The Si-Si bond with atomic layer 9A will not be unstable. Since silicon (Si) of the Si atomic layer 9B bonds with oxygen (O) to form a Si-O bond, the Si atomic layer 9B is referred to as an atomic layer constituting a part of the first SiO ₂ film 10A. be able to.

As described above, the Si atomic layer 9A and the Si atomic layer 9B are formed on the n ⁻ -type epitaxial layer 2, but they have different functions.

In particular, by bonding silicon (Si) of the Si atomic layer 9A to silicon (Si) of the n ⁻ -type epitaxial layer 2, C—C bonds and Si—Si bonds are formed in the surface layer portion of the n ⁻ -type epitaxial layer 2 Can be avoided. Therefore, the Si atomic layer 9A has an effect that the occurrence of quantum roughness at the interface between the n ⁻ -type epitaxial layer 2 and the gate insulating film 10 can be suppressed. As a result, in the SiC power MISFET, problems such as deterioration of channel mobility, deterioration of subthreshold characteristics and fluctuation of threshold voltage due to quantum roughness can be avoided to obtain stable operation characteristics. Can.

Furthermore, the gate insulating film 10 according to the first embodiment is composed of the good first SiO ₂ film 10A formed by the thermal oxidation method and the _second SiO ₂ film 10B formed thereon by the thermal CVD method. Therefore, the withstand voltage is improved as compared to a gate insulating film formed only of a silicon oxide (SiO ₂ ) film formed by a thermal CVD method. Therefore, the breakdown voltage of the SiC power MISFET can be improved.
«Method of manufacturing SiC power MISFET»

  The method of manufacturing the SiC power MISFET according to the first embodiment will be described in the order of steps with reference to FIGS. 5 to 10 are main-portion cross-sectional views showing an example of a manufacturing process of the SiC power MISFET according to the first embodiment.

First, as shown in FIG. 5, an n ⁺ -type SiC substrate 1 is prepared. An n-type impurity is introduced into the n ⁺ -type SiC substrate 1. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . Further, although the n ⁺ -type SiC substrate 1 has both surfaces of the Si surface and the C surface, the surface of the n ⁺ -type SiC substrate 1 may be either the Si surface or the C surface. The n ⁺ -type SiC substrate 1 is a region functioning as a drain layer.

Next, an n ⁻ -type epitaxial layer 2 of SiC is formed on the surface of the n ⁺ -type SiC substrate 1 by an epitaxial growth method. An n-type impurity lower than the impurity concentration of the n ⁺ -type SiC substrate 1 is introduced into the n ⁻ -type epitaxial layer 2. The impurity concentration of the n ⁻ -type epitaxial layer 2 depends on the element rating of the SiC power MISFET, and is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the n ⁻ -type epitaxial layer 2 is, for example, 5.0 to 20.0 μm. By the steps described above, SiC epitaxial substrate 3 formed of n ⁺ -type SiC substrate 1 and n ⁻ -type epitaxial layer 2 is formed.

Then, n ^- n-type impurity -type epitaxial layer 2, for example, nitrogen (N) atoms are implanted, n ^- -type epitaxial layer 2 to form a JFET region 7. The impurity concentration of the JFET region 7 is, for example, about 3 × 10 ¹⁶ cm ⁻³ .

Next, p-type impurities such as aluminum (Al) atoms are ion implanted into the n ⁻ -type epitaxial layer 2 with a maximum energy of 500 keV. As a result, the p-type body region 4 is formed in the element formation region of the n ⁻ -type epitaxial layer 2 and the floating field limiting ring (FLR) structure is formed in the peripheral formation region although not shown. Form.

The depth from the surface of the n ⁻ -type epitaxial layer 2 of the p-type body region 4 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the p-type body region 4 is, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . Although the FLR structure is formed at the end of the peripheral formation region, it is not limited thereto. The structure of the termination may be, for example, a junction termination extension (JTE) structure.

Next, an n-type impurity such as nitrogen (N) atom is ion-implanted into the n ⁻ -type epitaxial layer 2 at a maximum energy of 120 keV to separate from the end side surface of the p-type body region 4 in the p-type body region 4. An n ⁺ -type source region 5 is formed. The depth of the n ⁺ -type source region 5 from the surface of the n ⁻ -type epitaxial layer 2 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the n ⁺ -type source region 5 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

Next, a p-type impurity such as aluminum (Al) atom is ion-implanted into the n ⁻ -type epitaxial layer 2 at a maximum energy of 150 keV, and the p ⁺ -type potential fixing region 6 is fixed in the region for fixing the potential of the p-type body region 4. Form. The depth from the surface of the n ⁻ -type epitaxial layer 2 of the p ⁺ -type potential fixed region 6 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the p ⁺ -type potential fixed region 6 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

  Next, although not shown, a carbon (C) film is deposited on the front and back surfaces of the SiC epitaxial substrate 3 by, for example, a plasma CVD (Chemical Vapor Deposition) method. The thickness of the carbon (C) film is, for example, about 0.03 μm. After covering the front and back surfaces of the SiC epitaxial substrate 3 with this carbon (C) film, the SiC epitaxial substrate 3 is subjected to a heat treatment at a temperature of about 1,700 ° C. for about 2 to 3 minutes. Thereby, activation of each impurity ion-implanted into the SiC epitaxial substrate 3 is performed. After the heat treatment, the carbon (C) film is removed by oxygen plasma treatment, for example.

Next, as shown in FIG. 6, Si atomic layers 9A and 9B are formed on the surface of the n ⁻ -type epitaxial layer 2 by epitaxial growth. The total thickness of the two Si atomic layers 9A and 9B is, for example, about 1.0 nm. The Si atomic layers 9A and 9B are formed by epitaxially growing silicon (Si) at a temperature of 1,050 to 1,250 degrees using, for example, a mixed gas of silane (SiH ₄ ) and nitrogen (N ₂ ). be able to. The Si atomic layers 9A and 9B may be formed uniformly or in the form of islands.

Next, as shown in FIG. 7, oxygen (O) is bonded to the dangling bond of silicon (Si) in the Si atomic layer 9B by thermal oxidation to form a first SiO ₂ film 10A on the Si atomic layer 9A. Form The thickness of the first SiO ₂ film 10A is, for example, 1.5 nm or less.

Next, as shown in FIG. 8, a _second SiO ₂ film 10B is formed on the first SiO ₂ film 10A by a thermal CVD method, and a gate insulating film 10 composed of the first SiO ₂ film 10A and the _second SiO ₂ film 10B. Form The thickness of the _second SiO ₂ film 10B is, for example, about 50 nm. The relative dielectric constants or the densities of the first SiO ₂ film 10A and the _second SiO ₂ film 10B are different from each other. Here, by further heat treatment in a nitrogen oxide (NO or N ₂ O) atmosphere, the _second SiO ₂ film 10 B is changed to a silicon oxynitride (SiNO) film, and the first SiO ₂ film 10 A and silicon oxynitride (SiNO) You may form the gate insulating film 10 which consists of films | membranes.

  Next, as shown in FIG. 9, a polycrystalline silicon (Si) film is formed on gate insulating film 10, and this polycrystalline silicon (Si) film is processed by dry etching to form gate electrode 11. Do. The thickness of the gate electrode 11 is, for example, about 0.2 to 0.5 μm.

Next, as shown in FIG. 10, an interlayer insulating film 12 is formed on the surface of the n ⁻ -type epitaxial layer 2 by plasma CVD, for example, so as to cover the gate electrode 11 and the gate insulating film 10. Thereafter, interlayer insulating film 12 and gate insulating film 10 are processed by dry etching to form opening 13 reaching a part of n ⁺ -type source region 5 and p ⁺ -type potential fixing region 6.

Next, as shown in FIG. 3, a metal silicide layer 14, for example, is formed on the surface of a part of the n ⁺ -type source region 5 exposed on the bottom of the opening 13 and the p ⁺ -type potential fixing region 6. A nickel silicide (NiSi) layer is formed. Further, a metal silicide layer 16 such as a nickel silicide (NiSi) layer is formed on the back surface of the n ⁺ -type SiC substrate 1.

  Next, a drain wiring electrode 17 is formed to cover the metal silicide layer 16. The thickness of the drain wiring electrode 17 is, for example, about 0.4 μm.

  Next, the interlayer insulating film 12 is processed by dry etching to form an opening (not shown) reaching the gate electrode 11.

Next, the opening 13 reaching the metal silicide film 14 formed on part of the n ⁺ -type source region 5 and the surface of the p ⁺ -type potential fixing region 6 and the opening reaching the gate electrode 11 (not shown) On the interlayer insulating film 12 including the inside of the above, a laminated film consisting of a metal film, for example, a titanium (Ti) film, a titanium nitride (TiN) film and an aluminum (Al) film is deposited. The thickness of the aluminum (Al) film is preferably, for example, 2.0 μm or more. Subsequently, by processing the laminated film, gate wiring electrically connected to source wiring electrode 15 and gate electrode 11 electrically connected to a part of n ⁺ -type source region 5 through metal silicide layer 14 An electrode (not shown) is formed. Thereafter, external wirings are electrically connected to the source wiring electrode 15 and the gate wiring electrode (not shown).
«Power change device»

  A power converter (inverter) using the SiC power MISFET according to the first embodiment as a switching element will be described with reference to FIGS. 11 and 12. FIG. FIG. 11 is an equivalent circuit diagram showing a first example of a power conversion device (inverter) using the SiC power MISFET according to the first embodiment as a switch element. FIG. 12 is an equivalent circuit diagram showing a second example of a power conversion device (inverter) using the SiC power MISFET according to the first embodiment as a switch element.

  As shown in FIG. 11, the inverter according to the first embodiment includes a control circuit 21 and a power module 22. The control circuit 21 and the power module 22 are connected by a terminal 23 and a terminal 24. The power module 22 is connected to the power supply potential (Vcc) via the terminal 25 and to the ground potential (GND) via the terminal 26. The output of the power module is connected to the three-phase motor 30 via the terminals 27, 28 and 29.

The SiC power MISFET 31 according to the first embodiment is mounted on the power module 22 as a switching element. Further, an external reflux diode 32 is connected to each SiC power MISFET 31. The reflux diode 32 is provided to reduce the electric field applied to the interface between the metal and the semiconductor (Schottky interface) when a voltage is applied in the reverse direction, and to suppress the leakage current in the reverse operation. In FIG. 11, a diode 33 is a body diode formed of ap ⁺ -type potential fixed region 6 formed in a SiC power MISFET and an n ⁺ -type SiC substrate 1 (see FIG. 3 etc.).

  In each single phase, SiC power MISFET 31 and reflux diode 32 are connected in antiparallel between the power supply potential (Vcc) and the input potential of three-phase motor 30, and the input potential of three-phase motor 30 and the ground potential ( The SiC power MISFET 31 and the free wheeling diode 32 are connected in anti-parallel also with the GND). That is, two SiC power MISFETs 31 and two reflux diodes 32 are provided in each single phase of the three-phase motor 30, and six SiC power MISFETs 31 and six reflux diodes 32 are provided in three phases. The control circuit 21 is connected to the gate electrode of each SiC power MISFET 31, and the SiC power MISFET 31 is controlled by the control circuit 21. Therefore, the three-phase motor 30 can be driven by controlling the current flowing to the SiC power MISFET 31 of the power module 22 by the control circuit 21.

In the SiC power MISFET 31 according to the first embodiment, as described above, stable operation characteristics are obtained by suppressing the occurrence of quantum roughness at the interface between the n ⁻ -type epitaxial layer 2 and the gate insulating film 10, Can also be improved. Therefore, by applying the SiC power MISFET 31 according to the first embodiment to the power module 22, a high-performance and highly reliable power module 22 can be realized.

  Furthermore, as shown in FIG. 12, when the SiC power MISFET 31 according to the first embodiment is used as the power module 22, it is also possible to cause only the body diode 33 to function as a reflux diode without connecting the external reflux diode 32. it can.

  As a result, the highly reliable power module 22 can be realized without using the free wheeling diode 32.

  FIG. 13 is an equivalent circuit diagram showing an example in which a power converter (converter and inverter) using the SiC power MISFET according to the first embodiment as a switching element is applied to railway motor driving.

  In a railway, a direct current is taken from an overhead wire 41, a voltage is converted by a converter 42, and then an inverter 43 drives a load using a three-phase output such as a motor. Since the SiC power MISFET 31 according to the first embodiment can be applied not only to the inverter but also to the converter, a railway vehicle having a high-performance, high-reliability power converter can be realized.

  FIG. 14 is a voltage waveform diagram applied to the gate of the SiC power MISFET when driving the SiC power MISFET mounted on the power conversion device used for driving the three-phase motor according to the first embodiment.

  In a 3-phase motor drive circuit for railways, in order to avoid a malfunction called signal error etc., a phenomenon called "misfire", in IGBT (Insulated Gate Bipolar Transistor) using a Si substrate, the voltage at gate off is set to the negative side The method of setting to is adopted.

  In the SiC power MISFET according to the first embodiment, since the gate insulating film of good quality is formed, the deterioration of the gate insulating film can be suppressed even if the voltage at the gate off time is set to the negative side. Therefore, also in the SiC power MISFET according to the first embodiment, as shown in FIG. 14, since the method of setting the voltage at gate off to the negative side can be employed, the false firing in the three-phase motor drive circuit is avoided. be able to. In addition, a three-phase motor drive circuit using a Si substrate can be used as it is.

As described above, according to the first embodiment, the occurrence of quantum roughness at the interface between the n ⁻ -type epitaxial layer 2 and the gate insulating film 10 can be suppressed, so that the channel mobility is deteriorated in the SiC power MISFET. Thus, stable operation characteristics can be obtained without deterioration of subthreshold characteristics and fluctuation of threshold voltage.

Furthermore, since a good first SiO ₂ film 10A can be formed at the interface between the n ⁻ -type epitaxial layer 2 and the gate insulating film 10, the withstand voltage of the gate insulating film 10 can be improved to improve the withstand voltage of the SiC power MISFET. it can.

In the second embodiment, a trench type SiC power MISFET will be described.
«Structure of SiC power MISFET»

  The structure of the trench type SiC power MISFET according to the second embodiment will be described with reference to FIG. FIG. 15 is a cross-sectional view of essential parts showing a basic cell of the SiC power MISFET according to the second embodiment.

As shown in FIG. 15, by employing the trench structure, the gate insulating film 10 is formed on the side and bottom of the trench 18 provided perpendicularly to the n ⁻ -type epitaxial layer 2 made of SiC.

However, as in the first embodiment described above, the Si atomic layer 9A is formed between the n ⁻ -type epitaxial layer 2 and the gate insulating film 10. Si atomic layer 9A is, n ^- bonded -type epitaxial layer 2 of silicon (Si) to form a Si-Si bond, and relieve the strain caused by heat, n ^- -type epitaxial layer 2 carbon atoms in the (C) It has a function as a buffer layer that suppresses movement. Furthermore, a Si atomic layer (not shown) is formed on the Si atomic layer 9A. The Si atomic layer on the Si atomic layer 9A can be combined with oxygen (O) to form a Si-O bond to provide a good first SiO ₂ film 10A.

Thereby, also in the trench-type SiC power MISFET, substantially the same effect as the planar-type SiC power MISFET described in the first embodiment can be obtained.
«Method of manufacturing SiC power MISFET»

  A method of manufacturing the SiC power MISFET according to the second embodiment will be described in the order of steps with reference to FIGS. 16 to 18 are main-portion cross-sectional views showing an example of a manufacturing process of the SiC power MISFET according to the second embodiment.

First, as shown in FIG. 16, an n ⁻ -type epitaxial layer 2 of SiC is formed on the surface of an n ⁺ -type SiC substrate 1 in the same manner as in Example 1 described above, and n ⁺ -type SiC substrate 1 and n ⁻ The SiC epitaxial substrate 3 composed of the epitaxial layer 2 is formed.

Next, p-type body region 4 is formed in n ⁻ -type epitaxial layer 2, and n ⁺ -type source region 5 and p ⁺ -type potential fixing region 6 are formed in p-type body region 4.

Next, a trench 18 penetrating the n ⁺ -type source region 5 and the p-type body region 4 is formed. The depth of the trench 18 depends on the depth of the p-type body region 4 but needs to be deeper than the depth from the surface of the n ⁻ -type epitaxial layer 2 of the p-type body region 4. Thus, the end of the p-type body region 4 is located on the side surface of the trench 18.

Then, n ^- -type epitaxial layer 2 in the channel region 8a ^- an n-type impurity -type epitaxial layer 2 by oblique ion implantation, p-type body region 4 is formed n the sides of the trench 18. As an n-type impurity, nitrogen (N) atom or phosphorus (P) atom can be illustrated. The implantation angle is preferably an angle inclined about 10 to 45 degrees from the normal to the n ⁺ -type SiC substrate 1. The depth of the channel region 8a from the side surface of the trench 18 is, for example, about 0.05 to 0.2 μm. The impurity concentration of the channel region 8a is, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, Si atomic layers 9A and 9B are formed by the epitaxial growth method on the surface of the n ^-- type epitaxial layer 2 including the side and bottom of the trench 18 in the same manner as in Example 1 described above.

Next, as shown in FIG. 17, oxygen (O) is bonded to the dangling bond of silicon (Si) of the Si atomic layer 9B by a thermal oxidation method in the same manner as in Example 1 described above to form Si atoms. A first SiO ₂ film 10A is formed on the layer 9A. Furthermore, on the 1SiO ₂ film 10A, by thermal CVD to form a first 2SiO ₂ film 10B, a gate insulating film 10 consisting of a first 1SiO ₂ film 10A and the 2SiO ₂ film 10B.

Next, as shown in FIG. 18, the gate electrode 11, the interlayer insulating film 12, and the opening 13 are formed on the surface side of the n ⁺ -type SiC substrate 1 in the same manner as in Example 1 described above.

Next, as shown in FIG. 15, a metal silicide layer 14 is formed on the surface side of the n ⁺ -type SiC substrate 1, and a source wiring electrode 15 and a gate wiring electrode (not shown) are formed. . Further, a metal silicide layer 16 is formed on the back surface side of the n ⁺ -type SiC substrate 1, and a drain wiring electrode 17 is further formed. Here, as is apparent from the description using the typical trench type SiC power MISFET, the present invention is applicable to any structure as long as it is a MISFET having the side surface of the trench as a channel Can.

In the third embodiment, a planar type SiC power MISFET having a channel resistance lower than that of the planar type SiC power MISFET according to the above-described first embodiment and capable of suppressing a reduction in withstand voltage yield will be described.
«Structure of SiC power MISFET»

  The structure of the planar type SiC power MISFET according to the third embodiment will be described with reference to FIGS. FIG. 19 is a top view of relevant parts of a semiconductor chip on which the SiC power MISFET according to the third embodiment is mounted. FIG. 20 is a top view of an essential part of a semiconductor wafer on which a plurality of semiconductor chips mounted with the SiC power MISFET according to the third embodiment are formed. FIG. 21 is a cross-sectional view of essential parts taken along the line A-A of FIG. FIG. 22 is a plan view of relevant parts showing a basic cell region (four basic cells) of the SiC power MISFET according to the third embodiment (a plan view enlarging a region B of FIG. 19). Although a plurality of basic cells are formed on the semiconductor chip, only four basic cells are shown in FIG. 19 in order to clarify the structure of the basic cell. Further, in FIG. 20, only an outline of the gate wiring electrode and the channel region formed in each semiconductor chip is described.

As shown in FIG. 19, the semiconductor chip 51 has a transistor region (SiC power MISFET formation region) 52 in which a plurality of basic cells of the SiC power MISFET are connected in parallel, and a peripheral formation region surrounding the transistor region 52 in plan view The illustration is omitted). In the peripheral formation region, for example, a plurality of p-type FLRs formed to surround the transistor region 52 in plan view, and an n ⁺ -type guard ring formed to surround the plurality of p-type FLRs in plan view Is formed.

  The gate electrode 11 of each of the plurality of basic cells formed in the transistor region 52 has a stripe pattern (elongated rectangle) in a plan view, and a lead wire (gate bus line) connected to each stripe pattern All the gate electrodes 11 are electrically connected to a gate wiring electrode (gate pad) 53. The channel regions (the regions shown by hatching in FIG. 19) of the plurality of basic cells formed in the transistor region 52 also have a stripe pattern in plan view and are parallel to the gate electrode 11. It is arranged.

  The source region (not shown) of each of the plurality of basic cells is a source wiring electrode (source pad) through an opening (not shown) formed in the interlayer insulating film (not shown) covering the plurality of basic cells. It is electrically connected to 55. The gate wiring electrode 53 and the source wiring electrode 55 are formed apart from each other, and the source wiring electrode 55 is formed substantially over the entire surface of the transistor region 52 except for the region where the gate wiring electrode 53 is formed. It is formed.

  As shown in FIG. 20, the semiconductor chip 51 on which the SiC power MISFET is mounted is repeatedly arranged in the direction parallel to the orientation flat (hereinafter referred to as the orientation flat) OF of the semiconductor wafer SW and in the direction orthogonal to the orientation flat OF. It is done. The plurality of channel regions 8 b of the SiC power MISFET are arranged in parallel with the orientation flat OF, respectively.

  FIG. 21 is a cross-sectional view of the main part along the line AA shown in FIG. 19, and FIG. 22 is a plan view of the main part of the basic cell region B shown in FIG.

As shown in FIGS. 21 and 22, the point different from the SiC power MISFET according to the above-described first embodiment is that the channel impurity region 54 and the n ⁺ -type source region 57 are formed using the same mask pattern. The channel region (indicated by hatching in FIG. 22) 8b is formed in a self-aligned manner to suppress the variation in channel length. Further, by forming p type withstand voltage protective region 56 so as to cover the lower portion of channel impurity region 54, even if there is a region in which p type impurity is not ion implanted in channel impurity region 54, a decrease in withstand voltage yield is prevented. It can be done. The method of forming the channel region 8b will be described in detail in the method of manufacturing the SiC power MISFET described later.

An opening 13 reaching the n ⁺ -type source region 57 and the p ⁺ -type potential fixing region 6 is formed, and channel regions 8 b are formed on both sides of the opening 13 in the direction orthogonal to the orientation flat of the semiconductor wafer. Furthermore, the gate electrode 11 is formed so as to cover the channel region 8 b so as to be separated from the opening 13.
«Method of manufacturing SiC power MISFET»

  The method of manufacturing the SiC power MISFET according to the fourth embodiment will be described in the order of steps with reference to FIGS. 23 and 24 are main-portion cross-sectional views showing an example of a manufacturing process of the SiC power MISFET according to the third embodiment. FIG. 25 is a plan view of relevant parts showing one example of a manufacturing process of the SiC power MISFET according to the third embodiment.

First, as shown in FIG. 23, an n ⁻ -type epitaxial layer 2 of SiC is formed on the surface of an n ⁺ -type SiC substrate 1 in the same manner as in Example 1 described above, and n ⁺ -type SiC substrate 1 and n ⁻ -type A SiC epitaxial substrate 3 composed of the epitaxial layer 2 is formed.

Then, n ^- to form a mask pattern RP1 on the surface of the type epitaxial layer 2, through the mask pattern RP1 n ^- p-type impurity -type epitaxial layer 2, for example, aluminum (Al) atoms are ion-implanted. Thus, the p-type withstand voltage protection region 56 is formed. The p-type withstand voltage protection region 56 is located below the n ⁺ -type source region 57 and the p ⁺ -type potential fixing region 6 to be formed in a later step.

Although the p-type breakdown voltage protective region 56 is disposed to be embedded in the n ⁻ -type epitaxial layer 2 here, the p-type breakdown voltage protective region 56 may be disposed to be connected to the surface of the n ⁻ -type epitaxial layer 2. By making the p-type impurity concentration in the vicinity of the surface sufficiently lower than the p-type impurity concentration of the channel impurity region 54 to be formed later, the channel characteristics can be effectively not affected. Since the n-type region is surrounded by the p-type region, breakdown voltage failure can be prevented.

Next, as shown in FIGS. 24 and 25, ap type impurity such as an aluminum (Al) atom is ion implanted into the n ⁻ type epitaxial layer 2 to form ap ⁺ type potential fixing region 6.

Then, n ^- to form a mask pattern RP2 on the surface of the type epitaxial layer 2, through the mask pattern RP2 n ^- p-type impurity -type epitaxial layer 2, for example, aluminum (Al) atoms are ion-implanted. Thus, channel impurity region 54 is formed. At this time, multiple implantations of ion implantation inclined at a predetermined implantation angle θ1 from the normal to the SiC epitaxial substrate 3 and ion implantation inclined at a predetermined implantation angle θ2 on the opposite side to the orientation flat are performed.

Subsequently, n-type impurities such as nitrogen (N) atoms are ion-implanted into the n ⁻ -type epitaxial layer 2 through the mask pattern RP2. Thereby, the n ⁺ -type source region 57 is formed. By these ion implantations, the channel region 8b is formed in a self-aligned manner.

The n ⁺ -type source region 57 is formed so that the lower part thereof is covered by the p-type withstand voltage protection region 56. The distance between the end side surface of the n ⁺ -type source region 57 and the end side surface of the p-type withstand voltage protection region 56 (the distance D shown in FIGS. 24 and 25) is 0.2 μm, for example, when the channel length is 0.5 μm. The degree can be.

  In the sublimation method, a SiC wafer is formed by step-growing crystals in a direction parallel to the orientation flat (X3 direction shown in FIG. 20). Therefore, in the direction (X3 direction) parallel to the orientation flat, the crystal structure is asymmetric. On the other hand, since the crystal structure is symmetrical in the direction orthogonal to the orientation flat (X1 direction and X2 direction shown in FIG. 20), even if the region consisting of the ion implanted impurity is activated with symmetry, the impurity concentration The symmetry of the distribution is maintained.

Accordingly, the channel region 8 b can be formed in a self-aligned manner from the channel impurity region 54 and the n ⁺ -type source region 57, so that variations in channel length can be suppressed. In addition, if the channel length varies, the channel length is locally shortened. In order to avoid this, it is necessary to set the channel length long. However, since the variation in channel length can be suppressed, the channel length is set short. can do. As a result, the channel resistance can be lowered, and the performance of the SiC power MISFET can be improved.

Furthermore, since the lower part of the n ⁺ -type source region 57 is covered with the p-type withstand voltage protection region 56, a part of the channel impurity region 54 is formed, for example, by adhesion of particles during ion implantation. Even when not formed, the reduction in breakdown voltage yield of the SiC power MISFET can be suppressed.

Next, in the same manner as in Example 1 described above, the gate insulating film 10, the gate electrode 11, the interlayer insulating film 12, and the opening 13 are formed on the surface side of the n ⁺ -type SiC substrate 1.

Next, as shown in FIG. 21, a metal silicide layer 14 is formed on the surface side of the n ⁺ -type SiC substrate 1, and further, an electrode 55 for source wiring and an electrode (not shown) for gate wiring are formed. . Further, a metal silicide layer 16 is formed on the back surface side of the n ⁺ -type SiC substrate 1, and a drain wiring electrode 17 is further formed.

  As described above, according to the third embodiment, the channel resistance is lower than that of the planar SiC power MISFET shown in the first embodiment described above, and a decrease in breakdown voltage yield can be suppressed.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

  For example, although the present invention is applied to the MISFET in the above embodiment, the present invention can be applied to other power semiconductors such as IGBT.

1 n ⁺ type SiC substrate 2 n ⁻ type epitaxial layer 3 SiC epitaxial substrate 4 p type body region (well region)
5 n ⁺ type source region 6 p ⁺ type potential fixed region 7 JFET region (doping region)
8, 8a, 8b Channel region 9A, 9B Silicon atomic layer (Si atomic layer)
10 gate insulating film 10A first silicon oxide film (first SiO ₂ film)
10B Second silicon oxide film ( _second SiO ₂ film)
11 gate electrode 12 interlayer insulating film 13 opening 14 metal silicide layer 15 electrode for source wiring 16 metal silicide layer 17 electrode for drain wiring 18 trench 21 control circuit 22 power module 23, 24, 25, 26, 27, 28, 29 terminal 30 Three-phase motor 31 SiC power MISFET
32 reflux diode 33 body diode 41 overhead wire 42 converter 43 inverter 51 semiconductor chip 52 transistor area (SiC power MISFET formation area)
53 Gate wiring electrode (gate pad)
54 Channel impurity region 55 Source wiring electrode (source pad)
56 p type withstand voltage protective area 57 n ⁺ type source area RP1, RP2 mask pattern SW semiconductor wafer OF orientation flat (oriflat)

Claims (4)

(A) preparing a substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface and made of SiC;
(B) forming an epitaxial layer of the first conductivity type made of SiC on the first major surface of the substrate;
(C) ion implantation inclined at a first angle to the orientation flat side of the semiconductor wafer including the substrate from the normal to the substrate using the pattern serving as a mask for ion implantation formed on the epitaxial layer; An impurity diffusion layer of a second conductivity type different from the first conductivity type is formed in the epitaxial layer from the surface of the epitaxial layer by multiple implantation of ion implantation tilted at the first angle on the opposite side to the orientation flat. The process to
(D) forming a high concentration impurity diffusion layer of the first conductivity type from the surface of the epitaxial layer into the impurity diffusion layer using the pattern;
I have a,
In the surface layer portion of the epitaxial layer between the end side surface of the impurity diffusion layer and the end side surface of the high concentration impurity diffusion layer, a channel region is formed in a self-aligned manner by the step (d).
The method of manufacturing a semiconductor device, wherein the channel region is disposed in parallel with the orientation flat . (A) preparing a substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface and made of SiC;
(B) forming an epitaxial layer of the first conductivity type made of SiC on the first major surface of the substrate;
(C) using the first pattern serving as a mask for ion implantation formed on the epitaxial layer, the first impurity diffusion layer of the second conductivity type different from the first conductivity type from the surface of the epitaxial layer Forming in the epitaxial layer ;
(D) ion implantation inclined at a first angle to the orientation flat side of the semiconductor wafer including the substrate from the normal to the substrate using the second pattern serving as a mask for ion implantation, and opposite to the orientation flat A second impurity diffusion layer of the second conductivity type from the surface of the epitaxial layer on which the first impurity diffusion layer is formed by multiple implantation with ion implantation tilted at the first angle on the side. Forming the
(E) forming a high concentration impurity diffusion layer of the first conductivity type from the surface of the epitaxial layer into the first impurity diffusion layer using the second pattern;
I have a,
In the step (e), the high concentration impurity diffusion layer is formed so that the lower part thereof is covered by the first impurity diffusion layer,
A channel region is formed in a self-aligned manner in the surface layer portion of the epitaxial layer between the end side surface of the first impurity diffusion layer and the end side surface of the high concentration impurity diffusion layer by the step (e).
The method of manufacturing a semiconductor device, wherein the channel region is disposed in parallel with the orientation flat . (A) preparing a substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface and made of SiC;
(B) forming an epitaxial layer of the first conductivity type made of SiC on the first major surface of the substrate;
(C) forming an impurity diffusion layer of a second conductivity type different from the first conductivity type from the surface of the epitaxial layer into the epitaxial layer using a pattern serving as an ion implantation mask formed on the epitaxial layer The process to
(D) forming a high concentration impurity diffusion layer of the first conductivity type from the surface of the epitaxial layer into the impurity diffusion layer using the pattern;
(E) forming a Si atomic layer on the epitaxial layer;
(F) forming a gate insulating film on the Si atomic layer;
(G) forming a gate electrode on the gate insulating film;
I have a,
In the surface layer portion of the epitaxial layer between the end side surface of the impurity diffusion layer and the end side surface of the high concentration impurity diffusion layer, a channel region is formed in a self-aligned manner by the step (d).
The gate insulating film is
A first insulating film formed on the Si atomic layer and having a first relative dielectric constant;
A second insulating film formed on the first insulating film and having a second relative dielectric constant different from the first relative dielectric constant;
Including
The method of manufacturing a semiconductor device , wherein the Si atomic layer is one atomic layer . (A) preparing a substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface and made of SiC;
(B) forming an epitaxial layer of the first conductivity type made of SiC on the first major surface of the substrate;
(C) forming an impurity diffusion layer of a second conductivity type different from the first conductivity type from the surface of the epitaxial layer into the epitaxial layer using a pattern serving as an ion implantation mask formed on the epitaxial layer The process to
(D) forming a high concentration impurity diffusion layer of the first conductivity type from the surface of the epitaxial layer into the impurity diffusion layer using the pattern;
(E) forming a Si atomic layer on the epitaxial layer;
(F) forming a gate insulating film on the Si atomic layer;
(G) forming a gate electrode on the gate insulating film;
I have a,
In the surface layer portion of the epitaxial layer between the end side surface of the impurity diffusion layer and the end side surface of the high concentration impurity diffusion layer, a channel region is formed in a self-aligned manner by the step (d).
The gate insulating film is
A first insulating film formed on the Si atomic layer and having a first relative dielectric constant;
A second insulating film formed on the first insulating film and having a second relative dielectric constant different from the first relative dielectric constant;
Including
A method of manufacturing a semiconductor device , wherein the Si atomic layer is formed on the channel region .

Images