JP6353843B2 - メモリアクセス制御モジュールおよびこれに関連する方法 - Google Patents

メモリアクセス制御モジュールおよびこれに関連する方法 Download PDF

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Publication number
JP6353843B2
JP6353843B2 JP2015536847A JP2015536847A JP6353843B2 JP 6353843 B2 JP6353843 B2 JP 6353843B2 JP 2015536847 A JP2015536847 A JP 2015536847A JP 2015536847 A JP2015536847 A JP 2015536847A JP 6353843 B2 JP6353843 B2 JP 6353843B2
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data
memory
bit size
bus bit
data bus
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Japanese (ja)
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JP2015531524A5 (enExample
JP2015531524A (ja
Inventor
バオチアン リュウ
バオチアン リュウ
マット デビッドソン
マット デビッドソン
アルナ グッタ
アルナ グッタ
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
JP2015536847A 2012-10-09 2013-10-08 メモリアクセス制御モジュールおよびこれに関連する方法 Active JP6353843B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/647,971 US8984203B2 (en) 2012-10-09 2012-10-09 Memory access control module and associated methods
US13/647,971 2012-10-09
PCT/US2013/063944 WO2014058923A1 (en) 2012-10-09 2013-10-08 Memory access control module and associated methods

Publications (3)

Publication Number Publication Date
JP2015531524A JP2015531524A (ja) 2015-11-02
JP2015531524A5 JP2015531524A5 (enExample) 2016-10-13
JP6353843B2 true JP6353843B2 (ja) 2018-07-04

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JP2015536847A Active JP6353843B2 (ja) 2012-10-09 2013-10-08 メモリアクセス制御モジュールおよびこれに関連する方法

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US (1) US8984203B2 (enExample)
JP (1) JP6353843B2 (enExample)
KR (1) KR101903607B1 (enExample)
CN (1) CN104737143B (enExample)
WO (1) WO2014058923A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283854B2 (en) 2012-10-08 2019-05-07 Taoglas Group Holdings Limited Low-cost ultra wideband LTE antenna
US9014307B2 (en) 2013-02-25 2015-04-21 Itron, Inc. Radio to analog-to-digital sample rate decoupled from digital subsystem
US9252998B2 (en) 2013-02-25 2016-02-02 Itron, Inc. Radio to detect and compensate for frequency misalignment
US9426680B2 (en) 2013-02-25 2016-08-23 Itron, Inc. Real-time radio spectrum assessment engine
US8958506B2 (en) 2013-02-25 2015-02-17 Itron, Inc. FSK/MSK decoder
US8934532B2 (en) 2013-02-25 2015-01-13 Itron, Inc. Simultaneous reception of multiple modulation schemes
US8913701B2 (en) 2013-02-25 2014-12-16 Itron, Inc. Multichannel radio receiver with overlapping channel filters
TWI553483B (zh) * 2014-10-13 2016-10-11 瑞昱半導體股份有限公司 處理器及存取記憶體的方法
JP6515602B2 (ja) * 2015-03-12 2019-05-22 日本電気株式会社 データ処理装置及びデータ処理方法
US10241941B2 (en) * 2015-06-29 2019-03-26 Nxp Usa, Inc. Systems and methods for asymmetric memory access to memory banks within integrated circuit systems
US9992124B2 (en) 2015-10-09 2018-06-05 Itron, Inc. Multi-channel decoder architecture
US10691345B2 (en) * 2017-09-29 2020-06-23 Intel Corporation Systems, methods and apparatus for memory access and scheduling
JP7006166B2 (ja) * 2017-11-17 2022-01-24 富士通株式会社 データ転送装置およびデータ転送方法
CN109361882A (zh) * 2018-11-12 2019-02-19 中国科学院长春光学精密机械与物理研究所 模块化的cmos成像系统
US11102050B2 (en) * 2019-04-29 2021-08-24 Itron, Inc. Broadband digitizer used for channel assessment
US11075721B2 (en) 2019-04-29 2021-07-27 Itron, Inc. Channel plan management in a radio network
US11409671B2 (en) * 2019-09-19 2022-08-09 Facebook Technologies, Llc Artificial reality system having multi-bank, multi-port distributed shared memory
US11520707B2 (en) 2019-11-15 2022-12-06 Meta Platforms Technologies, Llc System on a chip (SoC) communications to prevent direct memory access (DMA) attacks
US11601532B2 (en) 2019-11-15 2023-03-07 Meta Platforms Technologies, Llc Wireless communication with code separation
US11190892B2 (en) 2019-11-20 2021-11-30 Facebook Technologies, Llc Audio sample phase alignment in an artificial reality system
CN115494761A (zh) * 2022-09-06 2022-12-20 深圳晟华电子有限公司 一种mcu直接存取内存的数字电路架构及方法
US12411789B2 (en) * 2023-02-14 2025-09-09 Xilinx, Inc. Data bus width configurable interconnection circuitry
TWI853647B (zh) * 2023-07-18 2024-08-21 新唐科技股份有限公司 異步橋接器與異步橋接方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0553338B1 (en) * 1991-08-16 1999-10-13 Cypress Semiconductor Corp. High-performance dynamic memory system
US7502817B2 (en) * 2001-10-26 2009-03-10 Qualcomm Incorporated Method and apparatus for partitioning memory in a telecommunication device
US20050144369A1 (en) * 2002-02-06 2005-06-30 Koninklijke Philips Electronics N.V. Address space, bus system, memory controller and device system
KR100450680B1 (ko) 2002-07-29 2004-10-01 삼성전자주식회사 버스 대역폭을 증가시키기 위한 메모리 컨트롤러, 이를이용한 데이터 전송방법 및 이를 구비하는 컴퓨터 시스템
US20100036999A1 (en) 2008-08-05 2010-02-11 Zhiqing Zhuang Novel method of flash memory connection topology in a solid state drive to improve the drive performance and capacity
US8296526B2 (en) 2009-06-17 2012-10-23 Mediatek, Inc. Shared memory having multiple access configurations

Also Published As

Publication number Publication date
US20140101354A1 (en) 2014-04-10
KR20150066588A (ko) 2015-06-16
CN104737143B (zh) 2018-07-10
US8984203B2 (en) 2015-03-17
KR101903607B1 (ko) 2018-12-05
JP2015531524A (ja) 2015-11-02
WO2014058923A1 (en) 2014-04-17
CN104737143A (zh) 2015-06-24

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