JP6303400B2 - Wiring structure manufacturing method and wiring structure - Google Patents

Description

  The present invention relates to a method for manufacturing a wiring structure and a wiring structure.

In recent years, in order to meet demands for downsizing, high performance, and low cost for electronic devices, along with miniaturization of semiconductor chips and multi-terminals, miniaturization of circuit boards on which semiconductor chips are mounted, multilayering, and circuit boards High-density mounting of electronic components is underway. Therefore, as the number of terminals of a semiconductor chip is increased and the pitch between these terminals is reduced, the multilayer circuit board is also required to have fine wiring.

  The variety and complexity of circuit boards are also increasing. A technique for forming a circuit by using a resin substrate in which a plurality of semiconductor chips having different properties are sealed with a resin, as represented by a so-called pseudo SoC (System on a Chip) technology, is also being studied. .

JP 2007-103850 A

  A method called SAP (Semi-Additive Process) method is generally used for forming wiring on a printed circuit board or pseudo SoC. When the Cu wiring is formed by the SAP method, there is a problem that Cu of the Cu wiring diffuses into the interlayer insulating film as the wiring density is increased and miniaturized, making it difficult to ensure reliability. Yes. An adhesion layer such as Ti is formed on the lower surface of the Cu wiring in order to ensure adhesion with the interlayer insulation film existing on the lower surface, and this adhesion layer prevents Cu diffusion into the interlayer insulation film. Yes. With respect to the side surface and upper surface of the Cu wiring, a Cu diffusion prevention film such as NiP is formed by an electroless plating method in order to prevent diffusion of Cu into the interlayer insulating film covering the side surface and the upper surface.

  Further, for forming wiring in an integrated circuit such as an LSI, a method called a damascene method is used in which a wiring groove is formed in an insulating film, Cu is embedded, and wiring is separated and formed by CMP or the like. Even when the wiring is formed by the damascene method, there is a problem that Cu of the Cu wiring diffuses into the interlayer insulating film, and it is difficult to ensure reliability. An adhesion layer similar to the above is formed on the side surface and the lower surface of the Cu wiring in order to ensure adhesion with the interlayer insulating film covering the side surface and the upper surface. It is intended to prevent diffusion. On the upper surface of the Cu wiring, a diffusion preventing film similar to the above is formed in order to prevent diffusion of Cu into the interlayer insulating film covering the upper surface.

  However, when the diffusion prevention film is formed on the Cu wiring on which the adhesion layer is formed as a base, NiP or the like is not formed on the exposed portion of the adhesion layer including the boundary portion with the Cu wiring, and at the boundary portion with the Cu wiring. There is a problem that the diffusion preventing film is interrupted. In this case, Cu leaks from the boundary portion into the interlayer insulating film, which is one of the main causes of deterioration of wiring reliability.

  The present invention has been made in view of the above-mentioned problems, and a diffusion prevention film is formed by a relatively simple method so as to surely cover the boundary between the adhesion layer and the Cu wiring, and into the Cu interlayer insulating film. An object of the present invention is to provide a highly reliable wiring structure manufacturing method and wiring structure that reliably prevent diffusion of the wiring.

One aspect of the method for manufacturing a wiring structure is a method for manufacturing a wiring structure including an insulating film, a wiring containing Cu as the largest component, and an adhesion layer formed between the insulating film and the wiring. Then, an exposed portion of the adhesion layer is oxidized to form an oxide film, and a diffusion prevention film is formed to cover the adhesion layer and cover the exposed portion of the wiring via the oxide film .

  One aspect of the wiring structure includes an insulating film, a wiring containing Cu as the largest component, an adhesion layer formed between the insulating film and the wiring, and a diffusion prevention film that covers the wiring and the adhesion layer The diffusion prevention film is formed through an oxide film formed on the adhesion layer.

  According to the above-described aspects, the diffusion prevention film is formed so as to surely cover the boundary between the adhesion layer and the Cu wiring by a relatively simple method, and the reliability for reliably preventing the diffusion of Cu into the interlayer insulating film is ensured. A highly reliable wiring structure is realized.

It is a schematic plan view which shows a mode that the some bare chip was reconstructed on the resin substrate. It is a schematic sectional drawing which shows the manufacturing method of the pseudo SoC semiconductor device by 1st Embodiment in order of a process. FIG. 3 is a schematic cross-sectional view illustrating the method of manufacturing the pseudo SoC semiconductor device according to the first embodiment in the order of steps, following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the method of manufacturing the pseudo SoC semiconductor device according to the first embodiment in the order of steps, following FIG. 3. It is a schematic sectional drawing which shows the comparative example of 1st Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the pseudo SoC semiconductor device by 2nd Embodiment to process order. FIG. 7 is a schematic cross-sectional view illustrating the method of manufacturing the pseudo SoC semiconductor device according to the second embodiment in order of processes subsequent to FIG. 6. FIG. 8 is a schematic cross-sectional view illustrating the method of manufacturing the pseudo SoC semiconductor device according to the second embodiment in order of processes subsequent to FIG. 7. It is a schematic sectional drawing which shows the comparative example of 2nd Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of LSI by 3rd Embodiment in order of a process. FIG. 11 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device of the LSI according to the third embodiment in order of processes following FIG. 10. FIG. 12 is a schematic cross-sectional view showing the method of manufacturing the LSI semiconductor device according to the third embodiment in the order of steps, following FIG. 11. FIG. 13 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor device of the LSI according to the third embodiment in order of processes following FIG. 12. It is a schematic sectional drawing which shows the comparative example of 3rd Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a wiring structure manufacturing method and a wiring structure will be described in detail with reference to the drawings.

(First embodiment)
In the present embodiment, the configuration of a semiconductor device using the pseudo SoC technology will be described together with the manufacturing method thereof. A case where a wiring structure is formed by a so-called SAP method will be exemplified.
FIG. 1 is a schematic plan view showing a state in which a plurality of bare chips are reconstructed on a resin substrate. 2 to 4 are schematic cross-sectional views illustrating the method of manufacturing the pseudo SoC semiconductor device according to the first embodiment in the order of steps, corresponding to the cross section at the position along the broken line II ′ in FIG. Yes. 2 (c) to 4 (c), only the configuration above the insulating film 11 is shown.

In this embodiment, as shown in FIG. 1 and FIG. 2A, a plurality of bare chips having different functions, here, bare chips 1 and 2 are reconstructed on the surface of the resin substrate 10.
Specifically, each bare chip is cut out from each semiconductor substrate on which a bare chip for each function is formed. Examples of the various bare chips include a memory chip in which a semiconductor memory is integrated, a logic chip in which a CMOS transistor or the like is integrated, a chip in which a drive function or an amplifier function is integrated, and the like. In the present embodiment, a bare chip 1 that is a memory chip and a bare chip 2 that is a logic chip are illustrated.
The bare chips cut out from the semiconductor substrate are arranged on the surface of the resin substrate 10 made of, for example, an epoxy resin so that, for example, the bare chip 1 and the bare chip 2 are adjacent to form one set.

Subsequently, as shown in FIG. 2B, an insulating film 11 having connection plugs 12 covering the resin substrate 10 is formed.
More specifically, the insulating film 11 is formed by applying a desired resin and solidifying the bare chip 1 and the bare chip 2 on the resin substrate 10.
An opening 11a that exposes the connection pads of the bare chip 1 and the bare chip 2 is formed in the insulating film 11 by, for example, a laser. For example, the connection plug 12 is formed by filling the opening 11a using a conductive paste. The connection plug 12 electrically connects the bare chip 1 and the bare chip 2 to a wiring structure described later.

Subsequently, as shown in FIG. 2C, an adhesion layer 13 and a plating seed layer 14 are formed on the insulating film 11.
Specifically, for example, Ti and then Cu are sequentially deposited on the insulating film 11 by sputtering, for example. Ti is deposited to a thickness of about 100 nm, for example, and Cu is deposited to a thickness of about 200 nm, for example. As described above, the adhesion layer 13 and the plating seed layer 14 are formed on the insulating film 11.
The adhesion layer 13 is selected from one kind of single layer selected from Ti, Ta, W, TiN, TaN, WN, TiW, TiWN, etc., Ti / W, Ti / TiN, Ta / WN, TiW / TiWN, etc. At least two types of laminated layers are formed. In the present embodiment, Ti is exemplified as the adhesion layer 13.

Subsequently, as shown in FIG. 2D, a resist mask 15 for forming wiring is formed.
Specifically, a photosensitive resist is applied on the plating seed layer 14 to a thickness of about 8 μm, for example, and the resist is processed by lithography. As described above, the resist mask 15 having the opening 15a exposing the wiring formation scheduled portion on the plating seed layer 14 is formed.

Subsequently, as shown in FIG. 3A, Cu16 is grown.
Specifically, Cu 16 is grown to a thickness of about 5 μm, for example, on the exposed portion of the plating seed layer 14 on the bottom surface of the opening 15a of the resist mask 15 by electrolytic plating. Cu16 is formed so as to fill the opening 15a up to a predetermined site. Cu16 contains Cu as the largest component, and may be an alloy such as Cu-Sn or Cu-Mn.

Subsequently, as shown in FIG. 3B, the resist mask 15 is removed.
Specifically, the resist mask 15 is subjected to wet processing using, for example, a predetermined organic solvent. Thereby, the resist mask 15 is removed.

Subsequently, as shown in FIG. 3C, a Cu wiring 16A is formed.
Specifically, the portion between the adjacent Cu 16 in the adhesion layer 13 and the plating seed layer 14 is removed by a desired wet etching. Thereby, each Cu16 is electrically separated, and Cu wiring 16A via the adhesion layer 13 is formed on the insulating film 11 by each Cu16. The distance between adjacent Cu wirings 16A is, for example, about 5 μm.

Subsequently, as shown in FIG. 3D, the exposed portion of the adhesion layer 13 is oxidized.
Specifically, the exposed portion of the adhesion layer 13, here, the side surface of the adhesion layer 13 is oxidized. As the oxidation treatment, plasma treatment in an atmosphere containing oxygen is performed. The plasma treatment is performed in a predetermined chamber in a pressure of about 5 Pa to 100 Pa, for example, in an oxygen atmosphere of about 10 Pa, with an input power of about 50 W to about 200 W, for example, about 100 W, and a processing time of about 5 seconds to about 60 seconds. For example, it is performed for about 10 seconds. By this plasma treatment, the side surface that is the exposed portion of the adhesion layer 13 and the side surface and the upper surface that are the exposed portion of the Cu wiring 16A are oxidized. In the illustrated example, a case where the thin oxide film 13a is formed on the side surface of the adhesion layer 13 and the thin oxide film 16a is formed on the side surface and the upper surface of the Cu wiring 16A is illustrated.

  In the plasma treatment, when the pressure of the oxygen atmosphere is lower than about 5 Pa, the plasma energy rises and Cu is scattered from the Cu wiring 16A, and NiP or the like described later is deposited on the surface other than the surface of the Cu wiring 16A ( Abnormal precipitation), which may cause defects such as leakage between wires. When the value is higher than about 100 Pa, the expected generation of plasma may be difficult. By setting the pressure of the oxygen atmosphere to about 5 Pa to about 100 Pa, it is possible to reliably generate desired plasma and ensure oxidation of the adhesion layer 13 while suppressing the occurrence of defects in the wiring.

  In the plasma processing, if the input power is lower than about 50 W, it may be difficult to generate the desired plasma. When the value is higher than about 200 W, the plasma energy rises and Cu is scattered from the Cu wiring 16A, which causes defects such as leakage between wirings as described above. By setting the input power to about 50 W to about 200 W, it is possible to reliably generate the desired plasma and ensure oxidation of the adhesion layer 13 while suppressing the occurrence of defects in the wiring.

  In the plasma treatment, when the treatment time is shorter than about 5 seconds, the oxidation treatment of the adhesion layer 13 may be insufficient. When the time is longer than 60 seconds, the plasma energy rises and Cu is scattered from the Cu wiring 16A, causing the occurrence of defects such as inter-wiring leakage as described above. Further, if the processing time is lengthened, the Cu wiring 16A is excessively oxidized, and there is a possibility that the wiring becomes thinner than the expected value in the subsequent acid cleaning process. By setting the processing time to about 5 seconds to about 60 seconds, it is possible to secure the oxidation of the adhesion layer 13 while maintaining the intended wiring width and suppressing the occurrence of defects in the wiring.

  In the present embodiment, the plasma treatment is exemplified as the oxidation treatment of the adhesion layer 13, but an ultraviolet light treatment or an ozone treatment may be performed instead of the plasma treatment. The UV light treatment will be described later in the second embodiment, and the ozone treatment will be described later in the third embodiment. Strictly speaking, the UV light treatment is one of ozone treatments because it is a method of generating ozone by irradiation with UV light.

Subsequently, as shown in FIG. 4A, the oxide film 16a generated on the side surface and the upper surface of the Cu wiring 16A is removed.
Specifically, the resin substrate 10 is dipped in a wet treatment, for example, 10% by weight sulfuric acid for about 1 minute. Thereby, the oxide film 16a produced | generated on the side surface and upper surface of Cu wiring 16A is removed. On the other hand, the oxide film 13a generated on the side surface of the adhesion layer 13 remains without being removed by the wet treatment.

Subsequently, as shown in FIG. 4B, a diffusion preventing film 17 is formed.
Specifically, for example, NiP is grown to a thickness of about 200 nm so as to cover the side surface of the adhesion layer 13 and the side surface and upper surface of the Cu wiring 16A by electroless plating. An oxide film 13 a is formed on the side surface of the adhesion layer 13. Therefore, NiP grows from the side surface to the side surface and the upper surface of the Cu wiring 16A so as to completely cover the side surface via the oxide film 13a without avoiding the side surface of the adhesion layer 13, and the diffusion preventing film 17 is formed. Is formed.
Thus, the wiring structure 3 having the adhesion layer 13 and the Cu wiring 16A and the diffusion prevention film 17 covering the adhesion layer 13 and the Cu wiring 16A is formed. The wiring structure 3 is electrically connected to the bare chip 1 and the bare chip 2 via the connection plug 12.

  The diffusion prevention film 17 is a film for preventing the diffusion of Cu in the Cu wiring 16A, and one kind selected from metals such as Co, Ni, W, or an alloy made of P, B and Co, Ni, W, etc. It is formed from one selected from (CoP, NiP, WP, CoB, NiB, WB, etc.). In the present embodiment, NiP is exemplified as the diffusion preventing film 17.

Subsequently, as shown in FIG. 4C, an interlayer insulating film 18 is formed.
Specifically, for example, a thermosetting resin is applied on the insulating film 11 so as to cover the wiring structure 3 and solidified. The resin is formed so that the thickness after solidification is, for example, about 10 μm. Thus, the interlayer insulating film 18 that covers the wiring structure 3 is formed on the insulating film 11.

  Thereafter, as in FIG. 2B, an opening is formed in the interlayer insulating film 18 and the diffusion prevention film 17 by a laser or the like, and a connection plug is formed in which the opening is embedded with a conductive paste or the like. Then, processes corresponding to FIGS. 2C to 4C are executed to form a wiring structure (and an interlayer insulating film). By repeating the steps corresponding to FIGS. 2B to 4C, a desired multilayer wiring structure is formed.

  Thereafter, the scribe line of the resin substrate 10 is diced to cut out a semiconductor chip composed of a pair of bare chips 1 and 2, for example. As described above, a semiconductor device based on the pseudo SoC technique of this embodiment is formed.

Here, a comparative example of the present embodiment will be described.
In this comparative example, after performing each step of FIG. 1A to FIG. 3C of this embodiment, the diffusion preventing film in FIG. 4B is performed without performing the oxidation treatment of FIG. 17 is formed. In this case, as shown in FIG. 5A, the diffusion prevention film 17 is formed only on the side surface and the upper surface of the Cu wiring 16A while avoiding the side surface of the adhesion layer 13, and the boundary portion between the adhesion layer 13 and the Cu wiring 16A. Is not formed.

  In this case, if the interlayer insulating film 18 is formed as shown in FIG. 5B, the diffusion prevention film 17 is interrupted at the boundary portion between the adhesion layer 13 and the Cu wiring 16A, so that the Cu of the Cu wiring 16A is cut from the boundary portion. Diffuses into the interlayer insulating film 18 and leaks out. As a result, the reliability of the wiring structure is deteriorated.

  On the other hand, in the present embodiment, by performing the above-described oxidation treatment, the diffusion prevention film 17 is formed so as to surely cover the boundary portion without being interrupted at the boundary portion between the adhesion layer 13 and the Cu wiring 16A. Is done. Thereby, the diffusion of Cu in the Cu wiring 16A into the interlayer insulating film 18 is surely suppressed, and a semiconductor device having a highly reliable wiring structure is realized.

(Second Embodiment)
In the present embodiment, as in the first embodiment, the configuration of the semiconductor device based on the pseudo SoC technology will be described together with the manufacturing method thereof. A case where a wiring structure is formed by a so-called damascene method will be exemplified.
6 to 8 are schematic cross-sectional views illustrating a method of manufacturing a pseudo SoC semiconductor device according to the second embodiment in the order of steps. 6B to 8B show only the configuration above the insulating film 11.

  In the present embodiment, first, similarly to the first embodiment, steps corresponding to FIGS. 2A and 2B are sequentially performed. At this time, as shown in FIG. 6A, an insulating film 11 having a connection plug 12 covering the resin substrate 10 is formed.

Subsequently, as shown in FIG. 6B, an insulating film 21 having a wiring trench 21a is formed.
Specifically, a photosensitive resin is applied on the insulating film 11, and the resin is exposed and developed. For example, a wiring groove 21a having a depth of about 5 μm is formed at a site where the resin wiring is to be formed. Thus, the insulating film 21 having the wiring trench 21a is formed. For example, the upper surface of the connection plug 12 is exposed on the bottom surface of the wiring groove 21a.

Subsequently, as shown in FIG. 6C, an adhesion layer 22 and a plating seed layer 23 are formed on the insulating film 21.
Specifically, for example, TiW and then Cu are sequentially deposited on the insulating film 21 including the inner wall surface of the wiring groove 21a by, for example, sputtering. TiW is deposited to a thickness of about 100 nm, for example, and Cu is deposited to a thickness of about 150 nm, for example. As described above, the adhesion layer 22 and the plating seed layer 23 are formed on the insulating film 21 including the inner wall surface of the wiring groove 21a.
The adhesion layer 22 is selected from one kind of single layer selected from Ti, Ta, W, TiN, TaN, WN, TiW, TiWN, etc., Ti / W, Ti / TiN, Ta / WN, TiW / TiWN, etc. At least two types of laminated layers are formed. In this embodiment, TiW is illustrated as the adhesion layer 22.

Subsequently, as shown in FIG. 6D, Cu 24 is grown.
Specifically, Cu 24 is grown on the plating seed layer 23 to a thickness of, for example, about 8 μm by electrolytic plating. Cu24 is formed so as to fill the wiring trench 21a. Cu24 has Cu as the maximum content component, and may be an alloy such as Cu-Sn or Cu-Mn.

Subsequently, as shown in FIG. 7A, a Cu wiring 24A is formed.
Specifically, the Cu 24 and the adhesion layer 22 are polished using a method such as chemical mechanical polishing (CMP), for example, with the surface of the insulating film 21 as a polishing stopper. Here, wet etching or the like may be used in combination with CMP, or only physical polishing may be performed. As described above, the adhesion layer 22 and the Cu 24 are electrically separated for each wiring groove 21a, and a Cu wiring 24A is formed in which the wiring groove 21a is filled with Cu 24 via the adhesion layer 22. The distance between adjacent Cu wirings 24A is, for example, about 5 μm.

Subsequently, as shown in FIG. 7B, the exposed portion of the adhesion layer 22 is oxidized.
Specifically, the exposed portion of the adhesion layer 22, here, the upper surface of the adhesion layer 22 is oxidized. As the oxidation treatment, ultraviolet light (UV light) treatment is performed. In the UV light treatment, for example, a low-pressure mercury lamp having a wavelength of 185 nm is used, and the adhesion layer 22 and the Cu wiring 24A are irradiated with UV light for about 1 minute to about 5 minutes, for example, about 3 minutes. Ozone is generated by this UV light treatment, and the upper surface that is the exposed portion of the adhesion layer 22 and the upper surface that is the exposed portion of the Cu wiring 24A are surface oxidized. In the example shown in the figure, a case where a thin oxide film 22a is formed on the upper surface of the adhesion layer 22 and a thin oxide film 24a is formed on the upper surface of the Cu wiring 24A is illustrated. The case where it forms in this state is also assumed.

  In the UV light treatment, when the irradiation time is shorter than about 1 minute, the oxidation treatment of the adhesion layer 22 may be insufficient. If it is longer than about 5 minutes, the Cu wiring 24A is excessively oxidized, and there is a possibility that the wiring becomes thinner than the expected value in the subsequent acid cleaning treatment. By setting the irradiation time to about 1 minute to about 5 minutes, it is possible to ensure the oxidation of the adhesion layer 22 while maintaining the intended wiring width.

  In the present embodiment, UV light treatment is exemplified as the oxidation treatment of the adhesion layer 22, but plasma treatment or ozone treatment may be performed instead of the UV light treatment. The plasma processing is performed in the same manner as in FIG. 3D of the first embodiment. The ozone treatment will be described later in the third embodiment.

Subsequently, as shown in FIG. 7C, the oxide film 24a generated on the upper surface of the Cu wiring 24A is removed.
Specifically, the resin substrate 10 is dipped in a wet treatment, for example, 10% by weight sulfuric acid for about 1 minute. Thereby, the oxide film 24a generated on the upper surface of the Cu wiring 24A is removed. On the other hand, the oxide film 22a generated on the upper surface of the adhesion layer 22 remains without being removed by the wet treatment.

Subsequently, as shown in FIG. 8A, a diffusion preventing film 25 is formed.
Specifically, for example, NiB is grown to a thickness of about 100 nm so as to cover the upper surface of the adhesion layer 22 and the upper surface of the Cu wiring 24A by an electroless plating method. An oxide film 22 a is formed on the upper surface of the adhesion layer 22. Therefore, NiB grows so as to cover the upper surface and the Cu wiring 24A so as to completely cover the upper surface via the oxide film 22a without avoiding the upper surface of the adhesion layer 22, and the diffusion prevention film 25 is formed. The
Thus, the wiring structure 4 having the adhesion layer 22 and the Cu wiring 24A and the diffusion prevention film 25 covering the adhesion layer 22 and the Cu wiring 24A is formed. The wiring structure 4 is electrically connected to the bare chip 1 and the bare chip 2 through the connection plug 12.

  The diffusion prevention film 25 is a film for preventing the diffusion of Cu in the Cu wiring 24A, and is one or at least two alloys selected from Co, Ni, W, CoP, NiP, WP, CoB, NiB, and WB. (CoWP or the like). In the present embodiment, NiB is exemplified as the diffusion preventing film 25.

Subsequently, as shown in FIG. 8B, an interlayer insulating film 26 is formed.
Specifically, for example, a thermosetting resin is applied on the insulating film 21 so as to cover the wiring structure 4 and solidified. The resin is formed so that the thickness after solidification is, for example, about 10 μm. Thus, the interlayer insulating film 26 that covers the wiring structure 4 is formed on the insulating film 21.

  Thereafter, as in FIG. 6A, an opening is formed in the interlayer insulating film 26 and the diffusion prevention film 25 by a laser or the like, and a connection plug is formed in which the opening is embedded with a conductive paste or the like. Then, various steps corresponding to FIGS. 6B to 8B are executed to form a wiring structure (and an interlayer insulating film). By repeatedly performing the steps corresponding to FIGS. 6A to 8B, an intended multilayer wiring structure is formed.

  Thereafter, the scribe line of the resin substrate 10 is diced to cut out a semiconductor chip composed of a pair of bare chips 1 and 2, for example. As described above, a semiconductor device based on the pseudo SoC technique of this embodiment is formed.

Here, a comparative example of the present embodiment will be described.
In this comparative example, after performing each process of FIG. 2 (a), (b) and FIG. 6 (a)-FIG. 7 (a) of this embodiment, without performing the oxidation process of FIG.7 (b). 8A, the diffusion preventing film 25 is formed. In this case, as shown in FIG. 9A, the diffusion prevention film 25 is formed only on the upper surface of the Cu wiring 24A, avoiding the upper surface of the adhesion layer 22, and at the boundary portion between the adhesion layer 22 and the Cu wiring 24A. Not formed.

  In this case, if the interlayer insulating film 26 is formed as shown in FIG. 9B, the diffusion preventing film 25 is interrupted at the boundary portion between the adhesion layer 22 and the Cu wiring 24A, so that the Cu of the Cu wiring 24A starts from the boundary portion. Diffuses into the interlayer insulating film 26 and leaks out. As a result, the reliability of the wiring structure is deteriorated.

  On the other hand, in the present embodiment, by performing the above oxidation treatment, the diffusion prevention film 25 is formed so as to surely cover the boundary portion without being interrupted at the boundary portion between the adhesion layer 22 and the Cu wiring 24A. Is done. Thereby, the diffusion of Cu into the interlayer insulating film 26 of the Cu wiring 24A is reliably suppressed, and a semiconductor device having a highly reliable wiring structure is realized.

(Third embodiment)
In the present embodiment, the configuration of an LSI semiconductor device will be described together with its manufacturing method. A case where a wiring structure is formed by a so-called dual damascene method will be exemplified.
10 to 13 are schematic cross-sectional views showing a method of manufacturing an LSI semiconductor device according to the third embodiment in the order of steps. 10 (c) to 13 (c), only the configuration above the interlayer insulating film 35 is shown.

  In this embodiment, first, as shown in FIG. 10A, functional elements such as a CMOS transistor, a memory, and a capacitor are formed on the Si substrate 31. Here, the MOS transistor 32 is illustrated. An interlayer insulating film 33 covering the MOS transistor 32 is formed, a contact hole 33a is formed in the interlayer insulating film 33, and a connection plug 34 for filling the contact hole 33a with W or the like is formed.

Subsequently, as shown in FIG. 10B, an interlayer insulating film 35 having an underlying wiring 35b, an etching stopper film 36, an interlayer insulating film 37, and a polishing stopper film 38 are sequentially formed on the interlayer insulating film 33.
Specifically, first, an interlayer insulating film 35 is formed on the interlayer insulating film 33, and a lower wiring 35b that fills the wiring groove 35a of the interlayer insulating film 35 with Cu via a predetermined adhesion layer by a so-called single damascene method. Form. The lower layer wiring 35b is electrically connected to the connection plug 34, for example.

Next, an etching stopper film 36 such as SiN is formed on the interlayer insulating film 35 to a thickness of about 50 nm, for example.
Next, an interlayer insulating film 37 such as a SiOC film or a SiOF film is formed on the etching stopper film 36 to a thickness of about 500 nm, for example.
Next, a polishing stopper film 38 such as SiO ₂ is formed on the interlayer insulating film 37 to a thickness of about 50 nm, for example.

Subsequently, as shown in FIG. 10C, a resist mask 39 for forming a via portion of the wiring groove is formed.
Specifically, a photosensitive resist is applied on the polishing stopper film 38, for example, and the resist is processed by lithography. As described above, the resist mask 39 having the opening 39a that exposes the portion where the via portion of the wiring groove is to be formed on the polishing stopper film 38 is formed.

Subsequently, as shown in FIG. 11A, after forming a via hole 41a in the polishing stopper film 38 and the interlayer insulating film 37, a resist mask 42 for forming a wiring portion of a wiring groove is formed.
Specifically, first, the polishing stopper film 38 and the interlayer insulating film 37 are dry-etched using the resist mask 39. As a result, a via hole 41 a that follows the opening 39 a of the resist mask 39 is formed in the polishing stopper film 38 and the interlayer insulating film 37. The resist mask 39 is removed by ashing or the like.
Next, a photosensitive resist is applied on the polishing stopper film 38, for example, and the resist is processed by lithography. As described above, the resist mask 42 having the opening 42a that exposes the formation portion of the wiring portion of the wiring groove on the polishing stopper film 38 is formed.

Subsequently, as shown in FIG. 11B, a wiring groove 43 is formed in the etching stopper film 36, the interlayer insulating film 37, and the polishing stopper film 38.
Specifically, the polishing stopper film 38, the interlayer insulating film 37, and the etching stopper film 36 are dry-etched using the resist mask 42. As a result, the etching stopper film 36, the interlayer insulating film 37, and the polishing stopper film 38 have a via portion that exposes part of the surface of the lower layer wiring 35b along the opening 42a of the resist mask 42, and the wiring thereon. A wiring groove 43 formed integrally with the portion is formed. The wiring trench 43 is formed to a depth of about 400 nm, for example. The resist mask 42 is removed by ashing or the like.

Subsequently, as shown in FIG. 11C, an adhesion layer 44 and a plating seed layer 45 are formed on the polishing stopper film 38.
Specifically, first, for example, TaN / Ta (TaN is the upper layer and Ta is the lower layer) is deposited on the polishing stopper film 38 including the inner wall surface of the wiring groove 43 by, for example, the CVD method or the PVD method. Next, Cu is deposited by, for example, the PVD method. Ta / TaN is deposited to a thickness of about 2 nm for Ta and about 5 nm for TaN, for example. Cu is deposited to a thickness of about 20 nm, for example. As described above, the adhesion layer 44 and the plating seed layer 45 are formed on the polishing stopper film 38 including the inner wall surface of the wiring groove 43.

  The adhesion layer 44 serves as a barrier metal, and one kind of single layer selected from Ti, Ta, TiN, TaN, WN, TiW, TiWN, or at least two kinds of laminated layers (TiN / Ti, TaN / Ta / Ti, TiTW / Ti, etc.) are formed. In the present embodiment, TaN / Ta is exemplified as the adhesion layer 44.

Subsequently, as shown in FIG. 12A, Cu 46 is grown.
Specifically, Cu 46 is grown on the plating seed layer 45 to a thickness of, for example, about 800 nm by electrolytic plating. Cu 46 is formed so as to fill the wiring trench 43. Cu46 has Cu as its maximum component, and may be an alloy such as Cu-Sn or Cu-Mn.

Subsequently, as shown in FIG. 12B, a Cu wiring 46A is formed.
Specifically, the Cu 24 and the adhesion layer 44 are polished using a polishing stopper film 38 using a method such as CMP. Thereby, the adhesion layer 44 and the Cu 46 are electrically separated for each wiring groove 43, and a Cu wiring 46 </ b> A in which the inside of the wiring groove 43 is filled with Cu 46 through the adhesion layer 44 is formed. The distance between adjacent Cu wirings 46A is about 200 nm to about 1000 nm, here about 500 nm.

Subsequently, as shown in FIG. 12C, the exposed portion of the adhesion layer 44 is oxidized.
Specifically, the exposed portion of the adhesion layer 44, here, the upper surface of the adhesion layer 44 is oxidized. As the oxidation treatment, ozone treatment is performed. In the ozone treatment, for example, the adhesion layer 44 and the Cu wiring 46 are exposed in an atmosphere having an ozone concentration of about 0.5 ppm to about 1% for about 2 seconds to about 10 minutes, for example, about (30 seconds). By this ozone treatment, the upper surface that is the exposed portion of the adhesion layer 44 and the upper surface that is the exposed portion of the Cu wiring 46A are surface oxidized. In the illustrated example, a case where a thin oxide film 44a is formed on the upper surface of the adhesion layer 44 and a thin oxide film 46a is formed on the upper surface of the Cu wiring 46A is illustrated.

  In the ozone treatment, if the ozone concentration is lower than about 0.5 ppm, the oxidation treatment of the adhesion layer 44 may be insufficient. When the value is higher than about 1%, the Cu wiring 46A is excessively oxidized, and the height of the wiring becomes lower than the expected value due to the subsequent oxide film removal process, or the Cu oxide film removal is insufficient. As a result, there is a possibility that the subsequent formation of a diffusion preventing film such as CoWP becomes insufficient. By setting the ozone concentration to about 0.5 ppm to about 1%, it is possible to ensure oxidation of the adhesion layer 44 while maintaining the desired wiring height and the like.

  In the ozone treatment, when the exposure time is shorter than about 2 seconds, the adhesion layer 44 may be insufficiently oxidized. If it is longer than about 10 minutes, the Cu wiring 46A is excessively oxidized, and the height of the wiring becomes lower than the expected value due to the oxide film removal treatment, or the Cu oxide film removal becomes insufficient. There is a possibility that the subsequent formation of a diffusion prevention film such as CoWP becomes insufficient. By setting the exposure time to about 2 seconds to about 10 minutes, it is possible to ensure the oxidation of the adhesion layer 44 while maintaining the desired wiring height and the like.

  In the present embodiment, ozone treatment is exemplified as the oxidation treatment of the adhesion layer 44, but plasma treatment or UV light treatment may be performed instead of the ozone treatment. The plasma processing is performed in the same manner as in FIG. 3D of the first embodiment. About UV light processing, it carries out similarly to FIG.7 (b) of 2nd Embodiment.

Subsequently, as shown in FIG. 13A, the oxide film 46a generated on the upper surface of the Cu wiring 46A is removed.
Specifically, the Si substrate 31 is subjected to a reduction treatment, for example, exposure in formic acid vapor at 150 ° C. for about 1 minute. As a result, the oxide film 46a generated on the upper surface of the Cu wiring 46A is reduced to become Cu. On the other hand, the oxide film 44a generated on the upper surface of the adhesion layer 44 remains without being reduced by the above treatment.

Subsequently, as shown in FIG. 13B, a diffusion preventing film 47 is formed.
Specifically, for example, CoWP is grown to a thickness of about 20 nm so as to cover the upper surface of the adhesion layer 44 and the upper surface of the Cu wiring 46A by electroless plating. An oxide film 44 a is formed on the upper surface of the adhesion layer 44. Therefore, the CoWP grows so as to cover the upper surface and the Cu wiring 46A so as to completely cover the upper surface via the oxide film 44a without avoiding the upper surface of the adhesion layer 44, and the diffusion prevention film 47 is formed. The
As described above, the wiring structure 5 including the adhesion layer 44 and the Cu wiring 46A and the diffusion prevention film 47 covering the adhesion layer 44 and the Cu wiring 46A is formed. The wiring structure 5 is electrically connected to the MOS transistor 32 and the like through the lower layer wiring 35b.

  The diffusion prevention film 47 is a film for preventing the diffusion of Cu in the Cu wiring 46A, and one or at least two alloys selected from Co, Ni, W, CoP, NiP, WP, CoB, NiB, and WB are used. (CoWP or the like). In the present embodiment, CoWP is exemplified as the diffusion preventing film 46.

Subsequently, as shown in FIG. 13C, an interlayer insulating film 48 is formed on the polishing stopper film 38 so as to cover the upper surface of the wiring structure 5.
Thereafter, the steps corresponding to FIG. 10B to FIG. 13C are repeatedly executed to form the desired multilayer wiring structure.

  Thereafter, the scribe line of the Si substrate 31 is diced to cut out the semiconductor chip. Thus, the LSI semiconductor device according to the present embodiment is formed.

Here, a comparative example of the present embodiment will be described.
In this comparative example, after performing each process of FIG. 10A to FIG. 12B of this embodiment, the diffusion preventing film in FIG. 13B is performed without performing the oxidation treatment of FIG. 47 is formed. In this case, as shown in FIG. 14A, the diffusion prevention film 47 is formed only on the upper surface of the Cu wiring 46A, avoiding the upper surface of the adhesion layer 44, and at the boundary portion between the adhesion layer 44 and the Cu wiring 46A. Not formed.

  In this case, if the interlayer insulating film 48 is formed as shown in FIG. 14B, the diffusion prevention film 47 is interrupted at the boundary portion between the adhesion layer 44 and the Cu wiring 46A, so that Cu of the Cu wiring 46A is cut from the boundary portion. Diffuses into the interlayer insulating film 48 and leaks out. As a result, the reliability of the wiring structure is deteriorated.

  On the other hand, in the present embodiment, by performing the above oxidation treatment, the diffusion prevention film 47 is formed so as to surely cover the boundary portion without being interrupted at the boundary portion between the adhesion layer 44 and the Cu wiring 46A. Is done. Thereby, diffusion of Cu into the interlayer insulating film 48 of the Cu wiring 46A is surely suppressed, and a semiconductor device having a highly reliable wiring structure is realized.

  Hereinafter, the manufacturing method of the wiring structure and various aspects of the wiring structure will be collectively described as additional notes.

(Appendix 1) an insulating film;
A wiring having Cu as the largest component;
A method of manufacturing a wiring structure including an adhesion layer formed between the insulating film and the wiring,
Oxidizing the exposed portion of the adhesion layer from the insulating film;
A method of manufacturing a wiring structure, comprising: forming a diffusion prevention film that covers an exposed portion of the oxidized adhesion layer from the insulating film and an exposed portion of the wiring from the insulating film.

  (Additional remark 2) The manufacturing method of the wiring structure of Additional remark 1 characterized by the distance between the said adjacent wiring being made into the range of 0.5 micrometer-5 micrometers.

  (Additional remark 3) The said oxidation process is a plasma process in the atmosphere containing oxygen, The manufacturing method of the wiring structure of Additional remark 1 or 2 characterized by the above-mentioned.

  (Additional remark 4) The said oxidation process is an irradiation process of ultraviolet light, The manufacturing method of the wiring structure of Additional remark 1 or 2 characterized by the above-mentioned.

  (Additional remark 5) The said oxidation process is an ozone process, The manufacturing method of the wiring structure of Additional remark 1 or 2 characterized by the above-mentioned.

  (Appendix 6) The diffusion preventing film is made of one or at least two alloys selected from Co, Ni, W, CoP, NiP, WP, CoB, NiB, and WB. 6. A method for manufacturing a wiring structure according to any one of 5 above.

  (Additional remark 7) The said adhesion layer is 1 type of single layer chosen from Ti, Ta, W, TiN, TaN, and WN, at least 2 types of lamination | stacking, at least 2 types of single layer of an alloy, or at least 2 types of The method for manufacturing a wiring structure according to any one of appendices 1 to 6, wherein the wiring structure is a laminated layer of alloys.

(Appendix 8) an insulating film;
A wiring having Cu as the largest component;
An adhesion layer formed between the insulating film and the wiring;
A diffusion prevention film covering the wiring and the adhesion layer,
The wiring structure, wherein the diffusion preventing film is formed through an oxide film formed on the adhesion layer.

  (Supplementary note 9) The wiring structure according to supplementary note 8, wherein the diffusion preventing film completely covers a non-covered portion of the insulating film of the adhesion layer.

  (Additional remark 10) The wiring structure of Additional remark 8 or 9 characterized by the distance between the said adjacent wiring being in the range of 0.5 micrometer-5 micrometers.

  (Appendix 11) The diffusion preventing film is made of one or at least two alloys selected from Co, Ni, W, CoP, NiP, WP, CoB, NiB, and WB. 11. The wiring structure according to any one of 10 above.

  (Supplementary Note 12) The adhesion layer may be one kind of single layer selected from Ti, Ta, W, TiN, TaN, and WN, at least two kinds of laminates, at least two kinds of alloy single layers, or at least two kinds. The wiring structure according to any one of appendices 8 to 11, wherein the wiring structure is an alloy laminate.

1, 2 Bare chips 3, 4, 5 Wiring structure 10 Resin substrates 11, 21 Insulating films 11a, 15a, 39a, 42a Openings 12, 34 Connection plugs 13, 22, 44 Adhesion layers 13a, 16a, 22a, 24a, 44a, 46a Oxide coating 14, 23, 45 Plating seed layer 15, 39, 42 Resist mask 16, 24, 46 Cu
16A, 24A, 46A Cu wiring 17, 25, 47 Diffusion prevention films 18, 26, 33, 35, 37, 48 Interlayer insulating films 21a, 35a, 43 Wiring groove 31 Si substrate 32 MOS transistor 33a Contact hole 35b Lower layer wiring 36 Etching Stopper film 38 Polishing stopper film 41a Via hole

Claims (10)

An insulating film;
A wiring having Cu as the largest component;
A method of manufacturing a wiring structure including an adhesion layer formed between the insulating film and the wiring,
Oxidizing the exposed part of the adhesion layer to form an oxide film ;
A method for manufacturing a wiring structure , comprising: forming a diffusion prevention film that covers the adhesion layer through the oxide film and covers an exposed portion of the wiring.   The method for manufacturing a wiring structure according to claim 1, wherein a distance between the adjacent wirings is in a range of 0.5 μm to 5 μm.   3. The method for manufacturing a wiring structure according to claim 1, wherein the oxidation treatment is a plasma treatment in an atmosphere containing oxygen.   The method for manufacturing a wiring structure according to claim 1, wherein the oxidation treatment is an ultraviolet light irradiation treatment.   The method for manufacturing a wiring structure according to claim 1, wherein the oxidation treatment is an ozone treatment.   The diffusion preventing film is made of one or at least two alloys selected from Co, Ni, W, CoP, NiP, WP, CoB, NiB, and WB. A method for manufacturing the wiring structure according to claim 1. An insulating film;
A wiring having Cu as the largest component;
An adhesion layer formed between the insulating film and the wiring;
A diffusion prevention film covering the wiring and the adhesion layer,
The wiring structure, wherein the diffusion preventing film is formed through an oxide film formed on the adhesion layer.   The wiring structure according to claim 7, wherein the diffusion preventing film completely covers an uncovered portion of the insulating film of the adhesion layer.   The wiring structure according to claim 7 or 8, wherein a distance between adjacent wirings is in a range of 0.5 µm to 5 µm.   The diffusion preventing film is made of one or at least two alloys selected from Co, Ni, W, CoP, NiP, WP, CoB, NiB, and WB. 2. The wiring structure according to item 1.

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