JP2016213254A - Wiring structure and manufacturing method thereof, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a highly reliable interposer and a semiconductor device capable of maintaining satisfactory wiring function after a long period of use by preventing oxidation of a wiring which contains copper with a simple structure.SOLUTION: The interposer is constituted of including: a first layer which has Cu wirings 16 and 17 and a first resin 19 covering a side faces of Cu wirings 16 and 17; a second layer which is in contact with the first resin 19 of a principal plane of the first layer, and which has second resins 11 and 22 the density of which is lower than that of the first resin 19; and third layers 18 and 21 formed between the Cu wiring 16, 17 and second resin 11, 22, which has oxidizability easier than the copper and forms a passive state.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a wiring structure, a manufacturing method thereof, and a semiconductor device.

  In recent years, along with demands for downsizing and high performance of electronic devices, along with miniaturization and multi-terminals of semiconductor chips, miniaturization and multilayering of circuit boards on which semiconductor chips are mounted, and further on circuit boards High-density mounting of electronic components is underway. As a technique for realizing such a demand for miniaturization, a high integration technique called a so-called 2.1D-IC or 2.5D-IC has attracted attention. In such a technique, a semiconductor device is configured by planarly integrating a plurality of LSI chips and different kinds of device chips on a printed circuit board via an interposer that is a wiring structure.

JP 2004-349729 A JP-A-2005-116660 JP-A-7-115255

  In general, the wiring layer of the interposer is formed by a semi-additive process (SAP). For example, as shown in FIG. 1, the wiring layer formed by SAP is formed so that wiring (Cu wiring) 101 containing copper (Cu) is embedded in a resin 102. A barrier layer 103 such as Ti or Ta is formed between the lower surface of the Cu wiring 101 and the resin 102.

  The lower surface of the Cu wiring 101 is protected from the resin 102 by the barrier layer 103, but the side surface and the upper surface are not protected and are in direct contact with the resin 102. Therefore, the contact portion of the Cu wiring 101 with the resin 102 is oxidized by the moisture absorption moisture of the resin 102 and moisture or oxygen that permeate the resin 102. Due to the oxidation of the contact portion, there is a problem in that the wiring shape is impaired, the effective area is reduced, and the wiring resistance is remarkably changed, leading to a significant reduction in wiring reliability.

  The present invention has been made in view of the above-described problems, and prevents the oxidation of wiring containing copper with a simple configuration, maintains an excellent wiring function even after repeated use, and improves the reliability of the wiring. It is an object of the present invention to provide a wiring structure, a manufacturing method thereof, and a semiconductor device that realize improvement.

  In one aspect of the wiring structure, the first layer having a first resin that covers a wiring made of a material containing copper and a side surface of the wiring, and the first resin on the main surface of the first layer is in contact with the first resin. A second layer having a second resin having a lower density than one resin, and a third layer formed between the wiring and the second resin, which is more oxidizable than copper and forms a passive state. Including.

  One aspect of a semiconductor device includes a substrate, a plurality of semiconductor chips, and a wiring structure that is disposed between the substrate and the plurality of semiconductor chips and electrically connects the substrate and the plurality of semiconductor chips. The wiring structure includes a first layer having a first resin covering a wiring made of a material containing copper and a side surface of the wiring, and a first layer in contact with a main surface of the first layer. A second layer having a second resin with a low density, and a third layer formed between the wiring and the second resin, which is more oxidizable than copper and forms a passive state.

  One aspect of a method for manufacturing a wiring structure includes a step of forming a first layer having a wiring made of a material containing copper and a first resin covering a side surface of the wiring, and the first layer on the main surface of the first layer. Forming a second layer having a second resin having a density lower than that of the first resin, which is in contact with the resin, and is more easily oxidizable than copper between the wiring and the second resin. A third layer is formed which forms a passivity.

  According to the above aspects, a highly reliable wiring structure and semiconductor device capable of preventing oxidation of a wiring containing copper and maintaining an excellent wiring function even after repeated use are realized with a simple configuration. To do.

It is a schematic sectional drawing which shows a part of conventional wiring structure formed by SAP. It is a schematic sectional drawing which shows the manufacturing method of the wiring structure by this embodiment in order of a process. FIG. 3 is a schematic cross-sectional view illustrating the method for manufacturing the wiring structure according to the present embodiment in order of processes following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the manufacturing method of the wiring structure according to the present embodiment in the order of steps, following FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating the method for manufacturing the wiring structure according to the present embodiment in the order of steps, following FIG. FIG. 6 is a schematic cross-sectional view illustrating the manufacturing method of the wiring structure according to the present embodiment in order of processes following FIG. 5. 1 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment. It is a schematic diagram which shows the apparatus structure for performing the HAST test in this embodiment. It is a schematic sectional drawing which shows the structure of the various wiring patterns used as the object of the HAST test in this embodiment. It is a table | surface which shows the result of a HAST test. It is a table | surface which shows the result of a HAST test.

Hereinafter, specific embodiments of a wiring structure, a manufacturing method thereof, and a semiconductor device including the wiring structure will be described in detail with reference to the drawings.
In the present embodiment, first, the configuration of the wiring structure will be described together with its manufacturing method. The wiring structure according to the present embodiment is an interposer of a semiconductor device. 2 to 6 are schematic cross-sectional views illustrating the manufacturing method of the wiring structure according to the present embodiment in the order of steps.

First, as shown in FIG. 2A, the second resin 11 is formed.
The second resin 11 is a resin having a lower density than the first resin described later, or a porous resin. In the present embodiment, as the second resin 11, an epoxy-based, phenol-based, or polyimide-based resin, or an organic porous material obtained by making a resin selected from these porous, porous silica, or the like is used. Here, the film is formed to a thickness of, for example, 3 μm using a phenolic resin. Thus, the second resin 11 is formed. The second resin 11 is not particularly limited as long as the density measured by, for example, the X-ray diffraction method is lower than the first resin described later.

Subsequently, as shown in FIG. 2B, an opening 11 a is formed in the second resin 11.
If the second resin 11 is a photosensitive resin, the opening 11a can be formed by utilizing an exposure phenomenon. When the second resin 11 is not a photosensitive resin, a resist is applied on the second resin 11, and a resist mask having an intended opening, for example, an opening with a diameter of about 10 μm is formed by lithography. With this resist mask, the second resin 11 is dry-etched using an etching gas such as CF ₄ . As a result, the opening 11 a is formed in the second resin 11.

Subsequently, a metal 12 is formed as shown in FIG.
Specifically, a predetermined metal is deposited on the second resin 11 to a thickness of, for example, about 20 nm to about 200 nm, here about 30 nm, so as to cover the inner wall surface of the opening 11a by sputtering or the like. Thus, the metal 12 is formed. If the predetermined metal is thinner than about 20 nm, sufficient passivation is not formed and the barrier property cannot be exhibited. If it is thicker than about 200 nm, it is difficult to form a Cu wiring with a desired width. The predetermined metal is a metal that is more oxidizable than Cu and forms a passive state, and is, for example, one metal selected from Ni, Sn, Al, Cr, and Co. Ni, Sn, Al, Cr, and Co are bases (easily oxidizable) than Cu, are oxides that form oxides in a water environment, and the oxides are stable and passivated. NiP, CoP, or CoWP may be used as the material instead of the predetermined metal.

Subsequently, as shown in FIG. 2D, a Cu seed film 13 is formed.
Specifically, Cu is deposited on the metal 12 to a thickness of, for example, about 30 nm to about 300 nm, here about 50 nm so as to cover the inner wall surface of the opening 11a with the metal 12 by sputtering or the like. Thus, the Cu seed film 13 is formed. The Cu seed film 13 is used as a conductive layer in subsequent electrolytic plating.

Subsequently, as shown in FIG. 3A, a resist 14A is applied.
Specifically, for example, a liquid photosensitive resist is applied on the Cu seed film 13 to a thickness of about 3 μm. Thus, the resist 14A is formed.

Subsequently, as shown in FIG. 3B, a resist mask 14 is formed.
Specifically, the resist 14A is processed by lithography to form openings 14a and 14b. The plurality of openings 14a are formed to have a diameter of about 2 μm at intervals of about 2 μm, and the opening 14b is formed to have a diameter of about 30 μm, for example, on the opening 11a. Thus, the resist mask 14 having the openings 14a and 14b is formed.

Subsequently, Cu15 is deposited as shown in FIG.
Specifically, Cu 15 is deposited so as to fill the openings 14a and 14b of the resist mask 14 by electrolytic plating using a sulfuric acid copper sulfate plating solution. Cu15 is deposited to a thickness of about 2 μm, for example.

Subsequently, as shown in FIG. 4A, the resist mask 14 is removed and Cu wirings 16 and 17 are formed.
Specifically, the resist mask 14 is wet-treated using a chemical solution such as acetone or NMP and removed. Thus, Cu wirings 16 and 17 are formed from the remaining Cu 15.

Subsequently, as shown in FIG. 4B, the unnecessary Cu seed film 13 is removed.
Specifically, the portions of the Cu seed film 13 exposed between the Cu wirings 16 and 17 and between the adjacent Cu wirings 17 are removed by wet treatment using a chemical solution such as potassium sulfate or sulfuric acid / hydrogen peroxide. As a result, the Cu wirings 16 and 17 are individually separated. Since the Cu seed film 13 is of the same quality as Cu 15, the illustration of the Cu seed film 13 is omitted in FIG.

Subsequently, as shown in FIG. 4C, the unnecessary metal 12 is removed to form a metal layer 18.
Specifically, the portions of the metal 12 exposed between the Cu wirings 16 and 17 and between the adjacent Cu wirings 17 are removed by dry etching using an etching gas such as CF ₄ . Instead of this dry etching, an aqueous wet etching using hydrochloric acid or sulfuric acid may be performed to remove the unnecessary metal 12. The metal 12 remains only on the lower surface of the Cu wiring 16 and the lower surface of the Cu wiring 17 (including the inner wall surface of the opening 11a), and the metal layer 18 is formed.

Subsequently, as shown in FIG. 5A, a first resin 19 is formed.
Specifically, for example, an olefin resin is used, and the resin is formed to a thickness of about 5 μm so that the Cu wirings 16 and 17 on the second resin 11 are embedded. Thus, the first resin 19 is formed.

  The first resin 19 and the second resin 11 have a relationship that the second resin 11 is a resin having a lower density than the first resin 19. As the first resin 19, an epoxy resin or a phenol resin may be used instead of the olefin resin. In this case, it is possible to form a film with a higher density than that of the second resin 11 by using a resin having a curing temperature different from that of the second resin 11 as the first resin 19. For example, when the first resin 19 and the second resin 11 are fired simultaneously, the second resin 11 is fired at a curing temperature of the first resin 19 using a resin having a higher curing temperature than the first resin 19. At this time, the first resin 19 is sufficiently cured, while the second resin 11 is incompletely baked and does not proceed with curing, and the density of the second resin 11 decreases.

Subsequently, as shown in FIG. 5B, the surface of the Cu wirings 16 and 17 is exposed by polishing the surface of the first resin 19.
Specifically, the surface of the first resin 19 is polished (ground) by chemical mechanical polishing (CMP) or mechanical grinding until the surfaces of the Cu wirings 16 and 17 are exposed. When CMP is performed, an aqueous solution containing abrasive grains such as silica or alumina is used as a slurry.

Subsequently, as shown in FIG. 5C, the metal layer 21 is formed only on the upper surfaces of the Cu wirings 16 and 17.
The predetermined metal for forming the metal layer 21 is a metal that is more oxidizable than Cu and forms a passive state, like the metal layer 18, for example, among Ni, Sn, Al, Cr, and Co. One kind of metal selected from Ni, Sn, Al, Cr, and Co are bases (easily oxidizable) than Cu, are oxides that form oxides in a water environment, and the oxides are stable and passivated.

When Ni, Sn, or Co is used as the predetermined metal, the metal is directly formed on the upper surfaces of the Cu wirings 16 and 17 to a thickness of about 20 nm to 100 nm using an electroless plating method.
When Al or Cr is used as the predetermined metal, the metal is formed to a thickness of about 20 nm to 100 nm by sputtering or the like, and the metal is subjected to lithography and dry etching.
As described above, the metal layer 21 is formed only on the upper surfaces of the Cu wirings 16 and 17.

Subsequently, as shown in FIG. 6A, a second resin 22 is formed.
Similar to the second resin 11, the second resin 22 is a resin having a lower density than the first resin 19 or a porous resin. In the present embodiment, as the second resin 22, an epoxy-based, phenol-based, or polyimide-based resin, or an organic porous material obtained by making a resin selected from these porous, porous silica, or the like is used. Here, the film is formed to a thickness of, for example, 3 μm using a phenolic resin. Thus, the second resin 22 is formed on the first resin 19 so as to cover the metal layer 21.

  Thereafter, a series of steps shown in FIGS. 2B to 4C or a series of steps shown in FIGS. 2B to 5C are performed. The latter state is shown in FIG. In the case of FIG. 6B, the series of steps of FIGS. 2A to 4C are further performed. In the case of FIG. 6 (b), the series of steps of FIG. 2 (b) to FIG. 4 (c) are performed, or the series of steps of FIG. 2 (a) to FIG. In some cases, the process is repeated as appropriate, and finally the series of steps shown in FIGS. 2 (a) to 4 (c) is performed. The land portion of the uppermost Cu wiring 17 serves as a connection pad for connection to a semiconductor chip or the like.

  Thereafter, a connection pad for connecting to a printed circuit board or the like is formed so as to be connected to the via portion of the lowermost Cu wiring 17. Thus, the interposer according to the present embodiment is formed.

  A semiconductor device using the interposer according to the present embodiment is shown in FIG. This semiconductor device includes an interposer 30 that electrically connects the printed circuit board 10 and the semiconductor chips 20A and 20B between the printed circuit board 10 and the semiconductor chips 20A and 20B. In FIG. 7, the portion inside the broken line frame A corresponds to the configuration of FIG. The printed circuit board 10 and the connection pads 32 on the back surface of the interposer 30 are connected by bumps 42 such as solder. Semiconductor chips 20A and 20B are arranged in parallel on the surface of the interposer 30, and the semiconductor chips 20A and 20B and the connection pads 31 on the surface of the interposer 30 are connected by bumps 41 such as solder. The connection pad 31 is a land portion of the uppermost Cu wiring 17.

  The interposer according to the present embodiment includes a first layer, a second layer, and a third layer, and is configured by sandwiching a main surface (front surface and back surface in this case) of the first layer with a set of second layers. . The first layer includes land portions of the Cu wiring 16 and the Cu wiring 17, and a first resin 19 that covers the side surface of the Cu wiring 16 and the side surface of the land portion of the Cu wiring 17. The second layer has via portions of the Cu wiring 17 and second resins 11 and 22 having a lower density than the first resin 19 and covering the side surfaces of the via portions. The third layer is metal layers 18 and 21 that are more oxidizable than Cu and form a passive state, and are arranged between the Cu wirings 16 and 17 and the second resins 11 and 22.

  In this interposer, since the second resin has a lower density than the first resin, it contains a lot of moisture and oxygen. The first layer having the Cu wiring and the land portion of the Cu wiring is sandwiched between the second layer having the second resin containing much moisture and oxygen. As a result, the side surface and the upper and lower surfaces (the third layer) of the Cu wiring are respectively exposed to the first resin and the second resin having different concentrations of moisture and oxygen contained therein. When this interposer is used repeatedly, a potential difference is generated between the upper and lower surfaces and side surfaces of the Cu wiring due to the difference in the concentration of moisture and oxygen, and a battery circuit is formed inside the Cu wiring. Accordingly, in the Cu wiring, the corrosion is accelerated on the upper and lower surfaces in contact with the second resin (in the third layer), so that the corrosion is suppressed on the side surface in contact with the first resin. If the third layer does not exist on the upper and lower surfaces of the Cu wiring, the Cu wiring is oxidized and corroded, and a non-conductive state is formed by arranging the third layer (an oxide stable in an aqueous environment). The oxidation / corrosion of the Cu wiring stops. By making the metal of the third layer base metal (easily oxidizable) than Cu, the battery circuit is more emphasized, and the corrosion of the side surface of the Cu wiring can be further suppressed.

Hereinafter, the experimental results obtained by examining the effect of suppressing the corrosion of the Cu wiring in the interposer according to the present embodiment based on the comparison with the conventional structure will be described. Here, a comb-like Cu wiring pattern 40 was formed, connected as shown in FIG. 8, and a reliability test (Highly Accelerated temperature and humidity Stress Test: HAST test) was performed. The HAST test was performed by applying a voltage of 5 V to the wiring pattern 40 in an environment of 130 ° C. and 85% RH. The time required for the leakage current value to reach 1.0 × 10 ⁶ A or more was defined as the insulation deterioration occurrence time, and the insulation maintenance effect of various wiring patterns 40 shown below was examined.

As a conventional structure, as shown in FIG. 9A, a wiring structure in which a Cu wiring 16 having a Ti barrier layer 41 formed on the lower surface is embedded in the first resin 19 is formed as a wiring pattern 40.
As Example 1, as shown in FIG. 9B, a wiring structure in which Cu wiring 16 in which third layers 18 and 21 of Ni are formed on the lower surface and the upper surface is embedded in the first resin 19 is wired. A pattern 40 was formed.
As Example 2, as shown in FIG. 9C, the first layer in which the side surfaces of the Cu wiring 16 having the Ni metal layers 18 and 21 formed on the lower surface and the upper surface are covered with the first resin 19 is used as the second layer. A wiring structure sandwiched between the resins 11 and 22 was formed as a wiring pattern 40. The wiring structure of Example 2 corresponds to the main configuration of the interposer of this embodiment.
As Example 3, as shown in FIG. 9D, the first layer covering the side surface of the Cu wiring 16 having the Ti barrier layer 41 formed on the lower surface with the first resin 19 is used as the second layers 11 and 22. A wiring structure sandwiched between the two was formed as a wiring pattern 40.
As Example 4, as shown in FIG. 9 (e), a set of a first layer covering the side surface of the Cu wiring 16 with the Ni metal layers 18 and 21 formed on the lower surface and the upper surface with the second resin 11 is provided. A wiring structure sandwiched by the first resin 19 was formed as a wiring pattern 40. The wiring structure of the fourth embodiment corresponds to a configuration in which the first resin and the second resin are replaced with the wiring structure of the second embodiment.

  The results of this HAST test are shown in the table of FIG. In Examples 1 and 3, the insulation maintaining effect about twice or more that of the conventional structure was obtained. In Example 2, the insulation maintaining effect about twice that of Examples 1 and 3 (about 4 times that of the conventional structure) was obtained. It was confirmed that Example 2 corresponding to this embodiment shows the most excellent insulating effect.

  Next, with respect to the wiring structure of Example 2, the material of the metal layer as the third layer was changed to form a wiring pattern 40, and a HAST test was conducted in the same manner as described above to examine the insulating effect. As the material of the metal layer, in addition to Ni, Sn, Al, Cr, Co, NiP, CoP, and CoWP mentioned as the material of the third layer in this embodiment, Cu, Zn, Fe, Au, and Ti were also examined. .

  The results of this HAST test are shown in the table of FIG. Compared to Cu, Zn, Fe, Au, and Ti, an insulation maintaining effect of about 1.5 to 2 times or more is obtained with Al and Cr, and about 2 or more times with Ni, Sn, Co, NiP, CoP, and CoWP. It was. It was confirmed that Ni, Sn, Al, Cr, Co, NiP, CoP, and CoWP corresponding to the third layer of this embodiment exhibit the most excellent insulating effect.

  As described above, according to the present embodiment, a highly reliable interposer and semiconductor device that can prevent oxidation of Cu wiring and maintain excellent wiring function even after repeated use with a simple configuration. Realize.

  In the present embodiment, the above-described interposer including the first to third layers has been disclosed. However, the present embodiment is applied to a multilayer wiring layer of a semiconductor device, and the multilayer wiring layer includes the first to third layers. It is also possible to have a structure with layers.

  Hereinafter, various aspects of the wiring structure, the manufacturing method thereof, and the semiconductor device will be collectively described as appendices.

(Additional remark 1) The 1st layer which has the 1st resin which covers the wiring which consists of material containing copper, and the side of the wiring,
A second layer having a second resin with a lower density than the first resin, which is in contact with the first resin on the main surface of the first layer;
A wiring structure comprising: a third layer formed between the wiring and the second resin, which is easier to oxidize than copper and forms a passive state.

  (Supplementary note 2) The wiring structure according to supplementary note 1, wherein the second layer is provided so as to sandwich the first layer.

  (Supplementary note 3) The wiring structure according to Supplementary note 1 or 2, wherein the second layer has a via portion of the wiring whose side surface is covered with the second resin.

  (Supplementary note 4) In any one of supplementary notes 1 to 3, the third layer is made of one selected from Ni, Sn, Al, Cr, Co, NiP, CoP, and CoWP. The wiring structure described.

(Appendix 5) a substrate;
A plurality of semiconductor chips;
A wiring structure that is disposed between the substrate and the plurality of semiconductor chips, and that electrically connects the substrate and the plurality of semiconductor chips;
The wiring structure is
A first layer having a wiring made of a material containing copper and a first resin covering a side surface of the wiring;
A second layer having a second resin having a density lower than that of the first resin, which is in contact with the main surface of the first layer;
And a third layer formed between the wiring and the second resin, which is easier to oxidize than copper and forms a passive state.

  (Additional remark 6) The said 2nd layer is provided so that the said 1st layer may be pinched | interposed, The semiconductor device of Additional remark 5 characterized by the above-mentioned.

  (Supplementary note 7) The semiconductor device according to Supplementary note 5 or 6, wherein the second layer includes a via portion of the wiring whose side surface is covered with the second resin.

  (Appendix 8) In any one of appendices 5 to 7, the third layer is made of one selected from Ni, Sn, Al, Cr, Co, NiP, CoP, and CoWP. The semiconductor device described.

(Additional remark 9) The process of forming the 1st layer which has the 1st resin which covers the wiring which consists of material containing copper, and the side of the wiring,
Forming a second layer having a second resin having a lower density than the first resin, which is in contact with the first resin on the main surface of the first layer.
A method for manufacturing a wiring structure, comprising: forming a third layer that is more oxidizable than copper and forms a passive state between the wiring and the second resin.

  (Additional remark 10) The said 2nd layer is provided so that the said 1st layer may be pinched | interposed, The manufacturing method of the wiring structure of Additional remark 9 characterized by the above-mentioned.

  (Additional remark 11) The said 2nd layer has a via part of the said wiring with which the side surface was covered with the said 2nd resin, The manufacturing method of the wiring structure of Additional remark 9 or 10 characterized by the above-mentioned.

  (Additional remark 12) Said 3rd layer consists of 1 type chosen from Ni, Sn, Al, Cr, Co, NiP, CoP, CoWP. Any one of Additional remarks 9-11 characterized by the above-mentioned. The manufacturing method of the wiring structure as described.

DESCRIPTION OF SYMBOLS 10 Printed circuit boards 11 and 22 2nd resin 11a, 14a, 22a Opening 12 Metal 13 Cu seed layer 14 Resist mask 14A Resist 15 Cu
16, 17, 101 Cu wiring 18, 21 Metal layer 19 First resin 20A, 20B Semiconductor chip 30 Interposer 31, 32 Connection pad 40 Wiring pattern 41, 42 Bump 102 Resin 103 Barrier layer

Claims (8)

A first layer having a wiring made of a material containing copper and a first resin covering a side surface of the wiring;
A second layer having a second resin with a lower density than the first resin, which is in contact with the first resin on the main surface of the first layer;
A wiring structure comprising: a third layer formed between the wiring and the second resin, which is easier to oxidize than copper and forms a passive state.   The wiring structure according to claim 1, wherein the second layer is provided so as to sandwich the first layer.   3. The wiring structure according to claim 1, wherein the second layer has a via portion of the wiring whose side surface is covered with the second resin. 4.   The wiring according to claim 1, wherein the third layer is made of one selected from Ni, Sn, Al, Cr, Co, NiP, CoP, and CoWP. Construction. A substrate,
A plurality of semiconductor chips;
A wiring structure that is disposed between the substrate and the plurality of semiconductor chips, and that electrically connects the substrate and the plurality of semiconductor chips;
The wiring structure is
A first layer having a wiring made of a material containing copper and a first resin covering a side surface of the wiring;
A second layer having a second resin having a density lower than that of the first resin, which is in contact with the main surface of the first layer;
And a third layer formed between the wiring and the second resin, which is easier to oxidize than copper and forms a passive state.   The semiconductor device according to claim 5, wherein the second layer is provided so as to sandwich the first layer. Forming a first layer having a wiring made of a material containing copper and a first resin covering a side surface of the wiring;
Forming a second layer having a second resin having a lower density than the first resin, which is in contact with the first resin on the main surface of the first layer.
A method for manufacturing a wiring structure, comprising: forming a third layer that is more oxidizable than copper and forms a passive state between the wiring and the second resin.   The method for manufacturing a wiring structure according to claim 7, wherein the second layer is provided so as to sandwich the first layer.

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