JP6278874B2 - Control circuit - Google Patents

Description

  The present invention relates to a control circuit for a cascode element.

  When a normally-on type semiconductor switch is used in a switching circuit, a normally-off voltage-driven semiconductor switch and a normally-on-voltage-driven semiconductor switch are configured as a normally-off type composite semiconductor element (hereinafter referred to as a cascode element) that is cascode-connected. Often (see Patent Document 1).

  Here, the configuration and operation of a switching circuit using the conventional control circuit 200 will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a configuration of the switching circuit 2 using the conventional control circuit 200. FIG. 7 is an operation waveform diagram of each part of the switching circuit 2 of FIG.

  In FIG. 7, in order from the top, the first gate terminal voltage VGS (Q1), the connection point voltage V (C), the switching current I (C), the second gate terminal voltage VGS (Q2), and the second drain terminal The voltage VDS (Q2) is shown.

  The first gate terminal voltage VGS (Q1) indicates a voltage between the first gate terminal G1 and the first source terminal S1 of the switch Q1 in FIG. A connection point voltage V (C) indicates a voltage between the connection point 11 and the reference point 12 (a point having the same potential as the source terminal S1 of the switch Q1) in FIG.

  The switching current I (C) indicates a switching current flowing through the second drain terminal D2 and the second source terminal S2 of the switch Q2 and the first drain terminal D1 and the first source terminal S1 of the switch Q1.

  The second gate terminal voltage VGS (Q2) indicates a voltage between the second gate terminal G2 and the second source terminal S2 of the switch Q2. The second drain terminal voltage VDS (Q2) indicates a voltage between the second drain terminal D2 and the second source terminal S2 of the switch Q2.

  As shown in FIG. 6, the switching circuit 2 includes a DC power supply 3, a resistor 4, a resistor 5, a DC power supply 7, a cascode element 10, and a control circuit 200. When the switching circuit 2 is actually configured, the circuit pattern includes a parasitic inductor 8, a parasitic capacitor (not shown), and a parasitic resistance.

  The cascode element 10 includes a normally-off voltage-driven semiconductor first switch Q1 having a first drain terminal D1, a first source terminal S1, and a first gate terminal G1.

  Further, the cascode element 10 includes a normally-on voltage-driven semiconductor second switch Q2 having a second drain terminal D2, a second source terminal S2, and a second gate terminal G2.

  The second source terminal S2 and the first drain terminal D1 are connected at the connection point 11, and the cascode element 10 is a normally-off type in which the first switch Q1 and the second switch Q2 are cascode-connected at the connection point 11. It is configured as a composite semiconductor element.

  The control circuit 200 includes a first control unit 210 and a control power supply unit 250. The first control unit 210 generates a first control signal that performs switching control of the first switch Q1, and performs switching control of the first switch Q1 based on the first control signal.

  The control power supply unit 250 is connected to the DC power supply 7 via the terminal 207 and supplies power necessary for performing switching control to the first control unit 210.

  In the switching circuit 2, the second gate terminal voltage VGS (Q2) is biased to a negative voltage during a period in which the first gate terminal voltage VGS (Q1) is at a low level (period t1 to t2 in FIG. 7). It is necessary to control so that the cascode element 10 is turned off and the switching current I (C) of the cascode element 10 does not flow.

  In the switching circuit 2, the second gate terminal voltage VGS (Q2) is about 0 [V] during a period when the first gate terminal voltage VGS (Q1) is at a high level (period t2 to t3 in FIG. 7). The cascode element 10 is turned on.

  In this way, in the switching circuit 2, the switching current I (C) of the cascode element 10 flows during the period from time t2 to time t3 in FIG.

JP 2011-10487 A

  However, in the conventional control circuit 200, the potential at the connection point 11 is not controlled, and the connection point voltage V (C) may become unstable.

  Therefore, as shown in a portion surrounded by a broken line in FIG. 7, the second gate terminal voltage VGS (Q2) and the like become unstable during the off period of the cascode element 10 (during the period from time t1 to t2 in FIG. 7). As a result, the switching control of the cascode element 10 may become unstable.

  In addition, the second gate terminal voltage VGS (Q2) may become excessively large, and the second gate terminal voltage VGS (Q2) exceeds the absolute maximum rated voltage, and the cascode element 10 can be operated safely. There was a risk that it would be impossible.

  In particular, when a parasitic inductor or the like having a large inductance value exists in the switching circuit 2, a voltage having a frequency higher than that of the first control signal is easily superimposed on the second gate terminal voltage VGS (Q2). Therefore, there is a possibility that stable operation and safe operation of the switching control of the cascode element 10 may be further difficult to ensure.

  FIG. 7 shows a simulation waveform by a circuit simulator. In FIG. 7, although a voltage having a frequency higher than that of the first control signal is not superimposed on the first gate terminal voltage VGS (Q1), FIG. It can be seen that a voltage having a frequency higher than that of the first control signal is superimposed on the second gate terminal voltage VGS (Q2) and the like.

  The present invention has been made in view of the above problems, and an object thereof is to provide a control circuit capable of stably and safely controlling switching of a cascode element.

  The present invention proposes the following matters in order to solve the above problems.

A normally-off semiconductor first switch having a first drain terminal, a first source terminal, and a first gate terminal; a second drain terminal, a second source terminal, and a second gate terminal; In a control circuit that controls switching of a cascode element including a normally-on semiconductor second switch that is cascode-connected to the first switch by being connected to the first drain terminal,
A first control unit that generates a first control signal that performs switching control of the first switch, and that performs switching control of the first switch based on the first control signal;
The second source terminal voltage, which is provided between the second source terminal and the first gate terminal and is a voltage between the second source terminal and the first source terminal, is equal to or higher than the first set voltage set to the positive side. The first switch is operated in a linear region so that the second source terminal voltage is less than the first set voltage, and the second gate terminal voltage of the second gate terminal relative to the second source terminal is negative. A second control unit that performs control so as not to bias further to the negative side than the second set voltage set on the side;
A control circuit characterized by comprising:

  A control comprising: a third control unit for assisting biasing of the second source terminal voltage in synchronization with the first control signal during the OFF period of the first switch controlled by the first control unit. A circuit is proposed.

  The second switch proposes a control circuit characterized by being a high electron mobility transistor.

  A high electron mobility transistor has been proposed which uses gallium nitride or silicon carbide for the channel.

  A high-electron mobility transistor has been proposed which uses an oxide semiconductor for a channel.

  A control circuit is proposed in which the oxide semiconductor is tin oxide, zinc oxide, indium oxide, or a composite oxide semiconductor in which these are combined.

  The second set voltage is set to be lower than a second gate terminal absolute maximum rated voltage which is an absolute maximum rated voltage between the second gate terminal and the second source terminal of the second switch. A control circuit is proposed.

  The second control unit is obtained by subtracting the voltage between the second source terminal and the first gate terminal from the second gate terminal absolute maximum rated voltage and the first switch threshold voltage at which the first switch is turned on. A control circuit has been proposed that is controlled so as to be lower than the subtraction value.

The second control unit includes a third switch having a third drain terminal, a third source terminal, and a third gate terminal, a first diode, and a first Zener diode,
The third switch is connected to short-circuit or open the second source terminal and the first gate terminal,
The anode terminal of the first diode is directly or indirectly connected to the second source terminal, the cathode terminal of the first diode is directly or indirectly connected to the third gate terminal,
The anode terminal of the first Zener diode is directly or indirectly connected to the third gate terminal, and the cathode terminal of the first Zener diode is directly or indirectly connected to the second source terminal. A control circuit is proposed.

The second control unit includes a second diode and a second Zener diode,
The anode terminal of the second diode is directly or indirectly connected to the second source terminal, and the cathode terminal of the second diode is directly or indirectly connected to the first gate terminal;
The anode terminal of the second Zener diode is directly or indirectly connected to the first gate terminal, and the cathode terminal of the second Zener diode is directly or indirectly connected to the second source terminal. A control circuit is proposed.

  The first control unit, the second control unit, and the third control unit propose a control circuit that is formed on a common semiconductor substrate.

According to the present invention, a normally-off semiconductor first switch having a first drain terminal, a first source terminal, and a first gate terminal, a second drain terminal, a second source terminal, and a second gate terminal are provided. A control circuit for controlling switching of a cascode element including a normally-on semiconductor second switch that is cascode-connected to the first switch by connecting the second source terminal and the first drain terminal;
The first control unit generates a first control signal for performing switching control of the first switch, performs switching control of the first switch based on the first control signal,
The second control unit is provided between the second source terminal and the first gate terminal, and the second source terminal voltage, which is a voltage between the second source terminal and the first source terminal, is set to the positive side. The first switch is operated in a linear region so that the second source terminal voltage is less than the first set voltage when the voltage exceeds the first set voltage. Control is performed so that the two-gate terminal voltage is not biased further to the negative side than the second set voltage set to the negative side. Thereby, switching of a cascode element can be controlled stably and safely.

  According to the present invention, the third control unit supplementarily biases the second source terminal voltage in synchronization with the first control signal during the OFF period of the first switch that is switching-controlled by the first control unit. Thereby, switching of a cascode element can be controlled stably.

  According to the present invention, since the second switch is a high electron mobility transistor, the cascode element having characteristics such as high-speed switching, low on-resistance, high withstand voltage, and high-temperature operation can be operated stably and safely, and high efficiency. A switching circuit can be configured.

  According to the present invention, since the high electron mobility transistor uses gallium nitride or silicon carbide as a channel, a cascode element having features such as high-speed switching, low on-resistance, high breakdown voltage, and high-temperature operation can be stably provided. In addition, it can be operated safely and a highly efficient switching circuit can be configured.

  A high electron mobility transistor uses an oxide semiconductor for a channel, and thus operates a cascode element having features such as high-speed switching, low on-resistance, high breakdown voltage, and high-temperature operation stably and safely, and is highly efficient. A switching circuit can be configured.

  Since the oxide semiconductor is tin oxide, zinc oxide, indium oxide or a composite oxide semiconductor in which these are combined, a cascode element having features such as high-speed switching, low on-resistance, high breakdown voltage, and high-temperature operation can be stably and safely. A highly efficient switching circuit can be configured by operating.

  Since the second set voltage is set to be lower than the second gate terminal absolute maximum rated voltage, which is the absolute maximum rated voltage between the second gate terminal and the second source terminal of the second switch, Furthermore, a control circuit capable of safe operation can be provided.

  The second control unit subtracts the voltage between the second source terminal and the first gate terminal by subtracting the first switch threshold voltage at which the first switch is turned on from the absolute maximum rated voltage of the second gate terminal. Control to a lower value. Therefore, a control circuit capable of further safe operation can be provided.

The second control unit includes a third switch having a third drain terminal, a third source terminal, and a third gate terminal, a first diode, and a first Zener diode,
The third switch is connected to short-circuit or open the second source terminal and the first gate terminal,
The anode terminal of the first diode is directly or indirectly connected to the second source terminal, the cathode terminal of the first diode is directly or indirectly connected to the third gate terminal,
The anode terminal of the first Zener diode is directly or indirectly connected to the third gate terminal, and the cathode terminal of the first Zener diode is directly or indirectly connected to the second source terminal.
Therefore, it is possible to provide a control circuit that can be operated stably and safely with a simple configuration.

The second control unit includes a second diode and a second Zener diode,
The anode terminal of the second diode is directly or indirectly connected to the second source terminal, and the cathode terminal of the second diode is directly or indirectly connected to the first gate terminal;
The anode terminal of the second Zener diode is directly or indirectly connected to the first gate terminal, and the cathode terminal of the second Zener diode is directly or indirectly connected to the second source terminal.
Therefore, it is possible to provide a control circuit that can be operated stably and safely with a simple configuration.

  Since the first control unit, the second control unit, and the third control unit are formed on a common semiconductor substrate, a control circuit having a simple configuration can be configured.

It is a circuit diagram which shows the structure of the switching circuit 1 using the control circuit 100 which concerns on embodiment of this invention. FIG. 3 is a circuit diagram illustrating a first configuration example of a configuration of a second control unit illustrated in FIG. 1. FIG. 3 is a circuit diagram illustrating a second configuration example of the configuration of the second control unit illustrated in FIG. 1. FIG. 4 is a circuit diagram illustrating an example of a configuration of a third control unit illustrated in FIG. 1. FIG. 2 is an operation waveform diagram of each part of the switching circuit 1 shown in FIG. 1. It is a circuit diagram which shows the structure of the switching circuit 2 using the conventional control circuit 200. FIG. 7 is an operation waveform diagram of each part of the switching circuit 2 of FIG. 6.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the constituent elements in the present embodiment can be appropriately replaced with existing constituent elements and the like, and various variations in combination with other existing constituent elements are possible. Therefore, the description of the present embodiment does not limit the contents of the invention described in the claims.

  A configuration of a control circuit according to an embodiment of the present invention and a switching circuit using the control circuit will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a switching circuit 1 using a control circuit 100 according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a first configuration example of the configuration of the second control unit shown in FIG. FIG. 3 is a circuit diagram illustrating a second configuration example of the configuration of the second control unit illustrated in FIG. 1. FIG. 4 is a circuit diagram showing an example of the configuration of the third control unit shown in FIG.

  The switching circuit 1 includes a DC power supply 3, a resistor 4, a resistor 5, a cascode element 10, and a control circuit 100. The DC power supply 3, the resistor 4, the cascode element 10, and the resistor 5 are connected in series to constitute the switching circuit 1.

  When the circuit of the switching circuit 1 is actually configured, the circuit pattern includes a parasitic inductor 8, a parasitic capacitor (not shown), and a parasitic resistance.

  The cascode element 10 includes a normally-off type semiconductor first switch Q1 and a normally-on type semiconductor second switch Q2.

  The first switch Q1 has a first drain terminal D1, a first source terminal S1, and a first gate terminal G1. The second switch Q2 has a second drain terminal D2, a second source terminal S2, and a second gate terminal G2.

  The second source terminal S2 and the first drain terminal D1 are connected at the connection point 11, and the first switch Q1 and the second switch Q2 are cascode-connected.

  For example, a MOSFET is used as the first switch Q1. For the second switch Q2, for example, a high electron mobility transistor using gallium nitride or silicon carbide as a channel is used.

  The second switch Q2 may be a high electron mobility transistor using, for example, tin oxide, zinc oxide, indium oxide, or a composite oxide semiconductor in which these are combined as a channel.

  When a high electron mobility transistor is used for the second switch Q2, a cascode element 10 having features such as high-speed switching, low on-resistance, high breakdown voltage, and high-temperature operation can be configured, and a highly efficient switching circuit 1 can be configured.

  The control circuit 100 is a control circuit that controls switching of the cascode element 10. The control circuit 100 includes a first control unit 110, a second control unit 120, a third control unit 130, and a control power supply unit 150.

  The first control unit 110 generates a first control signal for performing switching control of the first switch, and performs switching control of the first switch based on the first control signal. The first control signal is generated as a pulse rectangular wave, for example.

  The control circuit 100 supplies a first control signal between the first gate terminal G1 and the first source terminal S1 of the first switch Q1. The cascode element 10 is subjected to switching control by the first control signal.

  The first control unit 110 includes a drive unit 111, an oscillation unit 112, and a drive control unit 113.

  The drive unit 111 is connected to the first gate terminal G1 of the switch Q1 via the terminal 103 of the control circuit 100 and the terminal 13 of the cascode element 10, and sends a first control signal for driving switching of the switch Q1 to the terminal 103. For example as a pulse rectangular wave. The drive unit 111 is connected to the drive control unit 113 and is controlled by the drive control unit 113.

  The oscillation unit 112 is connected to the drive control unit 113, generates an oscillation signal that determines the switching frequency and duty of the switch Q1, and outputs the oscillation signal to the drive control unit 113. The drive control unit 113 controls the drive unit 111 based on the oscillation signal output from the oscillation unit 112.

  The drive control unit 113 is connected to the first source terminal S1 of the first switch Q1 via the terminal 104 of the control circuit 100 and the terminal 14 of the cascode element 10, and the switching current ID (C ) Becomes an overcurrent, the drive unit 111 is controlled to suppress an excessive increase in the switching current I (C).

  The second control unit 120 is connected between the second source terminal S2 and the first gate terminal G1 via the terminals 105 and 103 of the control circuit 100 and the terminals 15 and 13 of the cascode element 10.

  When the second source terminal voltage V (C), which is the voltage between the second source terminal S2 and the first source terminal S1, becomes equal to or higher than the first set voltage V1, the second control unit 120 The first switch Q1 is operated in the linear region so that the terminal voltage V (C) is less than the first set voltage V1.

  The second controller 120 controls the second gate terminal voltage of the second gate terminal G2 relative to the second source terminal S2 so as not to be biased further to the negative side than the second set voltage V2.

  The second setting voltage V2 is set to be lower than the second gate terminal absolute maximum rated voltage, which is the absolute maximum rated voltage between the second gate terminal G2 and the second source terminal S2 of the second switch Q2. Then, the cascode element 10 can be controlled more safely.

  For example, when the second set terminal voltage V2 is set to 20 [V] lower than 30 [V] when the second gate terminal absolute maximum rated voltage is 30 [V], further safe operation is possible. It becomes.

  In this case, for example, the second control unit 120 changes the voltage between the second source terminal S2 and the first gate terminal G1 from the second gate terminal absolute maximum rated voltage (for example, 30 [V]) to the first switch. A lower value (for example, 20 V) than a subtraction value (for example, 27 V (= 30 [V] −3 [V])) obtained by subtracting the first switch threshold voltage (for example, 3 [V]) at which Q1 is turned on. [V]). With such a configuration, the cascode element 10 can be operated more stably and safely.

  When the second control unit 120 is configured with the third switch Q3, the first diode 121, and the first Zener diode 122, for example, as in the first configuration example shown in FIG. Can be controlled.

  In the first configuration example, the third switch Q3 uses a MOSFET having a third drain terminal D3, a third source terminal S3, and a third gate terminal G3. The third switch Q3 connects the second source terminal S2 and the first gate terminal G1 so as to be short-circuited or opened.

  In the operation of short-circuiting the second source terminal S2 and the first gate terminal G1 by the third switch Q3, when the second source terminal voltage V (C) is equal to or higher than the first set voltage V1, The first switch Q1 is operated in the linear region so that the two-source terminal voltage V (C) is less than the first set voltage V1.

  In this case, the anode terminal of the first diode 121 is connected to the second source terminal S2 via the resistor 123, and the cathode terminal of the first diode 121 is connected to the third gate terminal G3 via the first Zener diode 122. To do.

  The anode terminal of the first Zener diode 122 is directly or indirectly connected to the third gate terminal G3, and the cathode terminal of the first Zener diode 122 is directly or indirectly connected to the second source terminal S2. In FIG. 2, the anode terminal of the first Zener diode 122 is directly connected to the third gate terminal G 3, and the cathode terminal of the first Zener diode 122 is connected to the second source via the first diode 121 and the resistor 123. An example of indirectly connecting to the terminal S2 is shown.

  The connection order of the first diode 121, the first Zener diode 122, and the resistor 123 is not limited. For example, the cathode terminal of the first Zener diode 122 is connected to the second source terminal S2, the anode terminal of the first Zener diode 122 is connected to the anode terminal of the first diode 121, and the cathode terminal of the first diode 121 is connected to the resistor It may be connected to the third gate terminal G3 via 123.

  In the configuration example 1, the first set voltage V1 can be set by constant adjustment of the first diode 121, the first Zener diode 122, and the resistor 123.

  Further, the second control unit 120 may be configured by the second diode 124 and the second Zener diode 125 as in the second configuration example illustrated in FIG. 3, for example. This also allows the cascode element 10 to be controlled more safely with a simple configuration.

  In this case, the anode terminal of the second diode 124 is connected to the second source terminal S2, and the cathode terminal of the second diode 124 is connected to the first gate terminal G1 via the second Zener diode 125 and the resistor 127.

  The anode terminal of the second Zener diode 125 is connected to the first gate terminal G1 via the resistor 127, and the cathode terminal of the second Zener diode 125 is connected to the second source terminal S2 via the second diode 124.

  Note that the connection order of the second diode 124 and the second Zener diode 125 is not limited. For example, the second diode 124 and the second Zener diode 125 may be connected in reverse.

  In the configuration example 2, the first setting voltage V1 can be set by adjusting the constants of the second diode 124, the second Zener diode 125, and the resistor 127.

  The third controller 130 supplementarily biases the second source terminal voltage in synchronization with the first control signal during the OFF period of the first switch Q1 that is switching-controlled by the first controller 110.

  The third control unit 130 includes, for example, a diode 136, a MOSFET 137, and a resistor 138. The cathode terminal of the diode 136 is connected to the terminal 105 of the control circuit 100, and is connected to the connection point 11 via the terminal 105 of the control circuit 100 and the terminal 15 of the cascode element 10. The anode terminal of the diode 136 is connected to the source terminal of the MOSFET 137.

  The drain terminal of the MOSFET 137 is connected to the output unit of the control power supply unit 150. The gate terminal of the MOSFET 137 is connected to one end of the resistor 138. The source terminal of the MOSFET 137 is connected to the anode terminal of the diode 136. The other end of the resistor 138 is connected to the output unit of the drive control unit 113.

  The control power supply unit 150 supplies control power necessary for the control circuit 100 to control switching of the cascode element 10 to the first control unit 110, the third control unit 130, and the like. The control power supply unit 150 is connected to the DC power supply 7 via the terminal 107 of the control circuit 100 and receives power supply from the DC power supply 7.

  When the first control unit 110, the second control unit 120, and the third control unit 130 are formed on a common semiconductor substrate, for example, the control circuit 100 having a simple configuration can be configured.

  Next, operations and effects of the control circuit 100 according to the present embodiment will be described with reference to FIG. FIG. 5 is an operation waveform diagram of each part of the switching circuit 1 of FIG.

  In FIG. 5, in order from the top, the first gate terminal voltage VGS (Q1), the connection point voltage V (C), the switching current I (C), the second gate terminal voltage VGS (Q2), and the second drain terminal. The voltage VDS (Q2) is shown.

  The first gate terminal voltage VGS (Q1) indicates a voltage between the first gate terminal G1 and the first source terminal S1 of the switch Q1 in FIG. The connection point voltage V (C) indicates a voltage between the connection point 11 and the reference point 12 (a point having the same potential as the source terminal S1 of the switch Q1) in FIG.

  The switching current I (C) indicates a switching current flowing through the second drain terminal D2 and the second source terminal S2 of the switch Q2 and the first drain terminal D1 and the first source terminal S1 of the switch Q1.

  The second gate terminal voltage VGS (Q2) indicates a voltage between the second gate terminal G2 and the second source terminal S2 of the switch Q2. The second drain terminal voltage VDS (Q2) indicates a voltage between the second drain terminal D2 and the second source terminal S2 of the switch Q2.

  In the switching circuit 1, the second gate terminal voltage VGS (Q2) becomes about 0 [V] during a period in which the first gate terminal voltage VGS (Q1) is at a high level (period t2 to t3 in FIG. 5). The cascode element 10 is turned on. As a result, the switching current I (C) of the cascode element 10 flows during the period from time t2 to t3 in FIG.

  Further, the second gate terminal voltage VGS (Q2) is biased to a negative voltage during a period in which the first gate terminal voltage VGS (Q1) is at the low level (period t1 to t2 in FIG. 5).

  Further, during the period from time t1 to time t2 in FIG. 5, the cascode element 10 is turned off, and the switching current I (C) of the cascode element 10 does not flow.

  The switching operation of the cascode element 10 is performed based on a first control signal generated by the control circuit 100.

  Here, in the switching circuit 1 using the cascode element 10 according to the present embodiment, the second control unit 120 performs the second source terminal S2 and the first source terminal S1 during the period from time t1 to time t2 in FIG. The second source terminal voltage (V (C) in FIG. 5) when the second source terminal voltage (V (C) in FIG. 5), which is a voltage between the first and second voltages, becomes equal to or higher than the first set voltage V1. The first switch Q1 is operated in the linear region so that becomes less than the first set voltage V1.

  The second controller 120 controls the second gate terminal voltage VGS (Q2) so as not to be biased further to the negative side than the second set voltage V2.

  Specifically, in the case of the first configuration example, when the second source terminal voltage (V (C) in FIG. 5) becomes equal to or higher than the first set voltage V1, the voltage of the gate G3-source S3 of the third switch Q3. Reaches the threshold value of the third switch Q3, and the third switch Q3 is turned on.

  As a result, the potentials of the terminal 103 of the control circuit 100 and the terminal 13 of the cascode element 10 rise, and the voltage VGS (Q1) between the gate G1 and the source S1 of the first switch Q1 reaches the threshold value of the first switch Q1. Switch Q1 is turned on.

  When the first switch Q1 is turned on, the potential at the connection point 11 decreases, the second source terminal voltage (V (C) in FIG. 5) becomes less than the first set voltage V1, and the third switch Q3 is turned off. Become. The on / off operation of the third switch Q3 as described above causes the first switch Q1 to operate in the linear region.

  In this case, the waveform of VGS (Q1) shown in FIG. 5 is a waveform in which a voltage having a higher frequency than the first control signal is superimposed during the period from time t1 to time t2, which is linear with the first switch Q1. This is because the switching operation is performed in the region, and this operation can suppress the amplitude of the voltage having a frequency higher than that of the first control signal, which is superimposed on the second gate terminal voltage VGS (Q2) and the like.

  In the case of the second configuration example, when the second source terminal voltage (V (C) in FIG. 5) becomes equal to or higher than the first set voltage V1, the second diode 124, the second Zener diode 125, and the resistor 127 Current flows.

  Then, the potentials of the terminal 103 of the control circuit 100 and the terminal 13 of the cascode element 10 rise, the voltage VGS (Q1) of the gate G1-source S1 of the first switch Q1 reaches the threshold value of the first switch Q1, and the first switch Q1 turns on.

  When the first switch Q1 is turned on, the potential at the connection point 11 decreases, the second source terminal voltage (V (C) in FIG. 5) becomes less than the first set voltage V1, and the second diode 124 and the second Zener diode. No current flows through 125 and the resistor 127.

  The operation of passing the current through or not passing through the second diode 124, the second Zener diode 125, and the resistor 127 as described above causes the first switch Q1 to operate in the linear region.

  Also in this case, as in the case of the first configuration example, the amplitude of the voltage having a frequency higher than that of the first control signal superimposed on the second gate terminal voltage VGS (Q2) or the like can be suppressed to be small. .

  In this way, in the case of the first configuration example and the second configuration example, the second source terminal voltage (V (C) in FIG. 5) is the second during the period from time t1 to t2 in FIG. The first switch Q1 is operated in the linear region so that the second source terminal voltage (V (C) in FIG. 5) is less than the first set voltage V1 when the set voltage becomes equal to or higher than the set voltage V1. Then, the second gate terminal voltage (VGS (Q2) in FIG. 5) is controlled not to be biased further to the negative side than the second set voltage V2.

  Therefore, according to the control circuit 100 according to the present embodiment, the second gate terminal voltage VGS (Q2) may exceed the absolute maximum rated voltage, and the cascode element 10 cannot be operated safely. Is eliminated, and the cascode element 10 can be operated stably and safely.

  In the switching circuit 1 using the cascode element 10 according to the present embodiment, the third control unit 130 is in the off period of the first switch Q1 that is controlled by the first control unit 110 (in FIG. 5). During the period from time t1 to t2, the second source terminal voltage is supplementarily biased in synchronization with the first control signal.

  Specifically, in the example shown in FIG. 4, the first control signal synchronized with the oscillation signal generated by the oscillating unit 112 is LOW, that is, during the OFF period of the first switch Q1 (in FIG. 5). During the period of time t1 to t2, the MOSFET 137 is turned on, the potential of the connection point 11 is increased from the control power supply unit 150 via the terminal 105 and the terminal 15, and the second source terminal voltage is supplementarily biased.

  A drive signal synchronized with the first control signal is input to the gate terminal of the MOSFET 137, and the MOSFET 137 switches in synchronization with the first control signal. Accordingly, the third control unit 130 supplementarily biases the second source terminal voltage in synchronization with the first control signal during the period of time t1 to t2 in FIG.

  With the above operation, the control circuit 100 causes the second gate to operate during the period from immediately after the cascode element 10 transitions from the on state to the off state until the cascode element 10 is turned on (during time t1 to t2 in FIG. 5). The fluctuation of the terminal voltage (VGS (Q2) in FIG. 5) is suppressed, and the switching control of the cascode element 10 is stabilized.

  As described above, according to the control circuit 100 according to the present embodiment, the first control unit 110 generates the first control signal for performing the switching control of the first switch Q1, and based on the first control signal. The second control unit 120 performs switching control of the first switch Q1, and the second control unit 120 determines that the second source terminal voltage V (C), which is a voltage between the second source terminal S2 and the first source terminal S1, is the first set voltage V1. In such a case, the first switch Q1 is operated in the linear region so that the second source terminal voltage V (C) is less than the first set voltage V1, and the second gate with the second source terminal S2 as a reference. Control is performed so that the second gate terminal voltage of the terminal G2 is not biased further to the negative side than the second set voltage V2. Thereby, switching of the cascode element 10 can be controlled stably and safely.

  According to the control circuit 100 according to the present embodiment, the third control unit 130 synchronizes with the first control signal during the OFF period of the first switch Q1 that is switched by the first control unit 110. The source terminal voltage V (C) is supplementarily biased. Thereby, switching of the cascode element 10 can be stably controlled.

  In the present embodiment, when the second switch Q2 of the cascode element 10 is a high electron mobility transistor, the cascode element 10 having characteristics such as high-speed switching, low on-resistance, high withstand voltage, and high-temperature operation is operated stably and safely. A highly efficient switching circuit 1 can be configured.

  In the present embodiment, when the high electron mobility transistor used for the second switch Q2 of the cascode element 10 uses gallium nitride or silicon carbide for the channel, high-speed switching, low on-resistance, high breakdown voltage, and high-temperature operation Thus, the cascode element having the above characteristics can be operated stably and safely, and a highly efficient switching circuit can be configured.

  In the present embodiment, when the high electron mobility transistor used for the second switch Q2 of the cascode element 10 uses an oxide semiconductor for the channel, it is characterized by high-speed switching, low on-resistance, high breakdown voltage, and high-temperature operation. The cascode element having the above can be operated stably and safely, and a highly efficient switching circuit can be configured.

  In the present embodiment, when the high electron mobility transistor used for the second switch Q2 of the cascode element 10 is tin oxide, zinc oxide, indium oxide, or a composite oxide semiconductor in which these are combined, high-speed switching, low on-resistance A cascode element having features such as high breakdown voltage and high temperature operation can be operated stably and safely, and a highly efficient switching circuit can be configured.

  In the present embodiment, the second set voltage V2 is lower than the second gate terminal absolute maximum rated voltage which is the absolute maximum rated voltage between the second gate terminal G2 and the second source terminal S2 of the second switch Q2. When set to be a value, the cascode element 10 can be controlled more safely.

  In the present embodiment, the second control unit 120 turns on the voltage between the second source terminal S2 and the first gate terminal G1, for example, from the second gate terminal absolute maximum rated voltage, and the first switch Q1 turns on. If the first switch threshold voltage is controlled to be lower than the subtraction value obtained by subtraction, the cascode element 10 can be operated more stably and safely.

In the present embodiment, the second control unit 120 includes a third switch Q3 having a third drain terminal D3, a third source terminal S3, and a third gate terminal G3, a first diode 121, and a first Zener diode 122. The third switch Q3 is connected so as to short-circuit or open the second source terminal S2 and the first gate terminal G1, and the anode terminal of the first diode 121 is connected directly to the second source terminal S2. Indirectly connected, the cathode terminal of the first diode 121 is directly or indirectly connected to the third gate terminal G3, and the anode terminal of the first Zener diode 122 is directly or indirectly connected to the third gate terminal G3. The cathode terminal of the first Zener diode 122 is connected directly or indirectly to the second source terminal.
Therefore, it is possible to provide a control circuit that can be operated stably and safely with a simple configuration.

In the present embodiment, the second control unit 120 includes a second diode 124 and a second Zener diode 125, and an anode terminal of the second diode 124 is directly or indirectly connected to the second source terminal S2. The cathode terminal of the second diode 124 is directly or indirectly connected to the first gate terminal G1, the anode terminal of the second Zener diode 125 is directly or indirectly connected to the first gate terminal G1, and the second The cathode terminal of the Zener diode 125 is directly or indirectly connected to the second source terminal S2.
Therefore, it is possible to provide a control circuit that can be operated stably and safely with a simple configuration.

  In the present embodiment, when the first control unit 110, the second control unit 120, and the third control unit 130 are formed on a common semiconductor substrate, the control circuit 100 having a simple configuration can be configured.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to embodiment mentioned above. Various modifications and applications are possible without departing from the scope of the present invention.

1: switching circuit 3, 7: DC power supply 4, 5: resistor 8: parasitic inductor 10: cascode element 11: connection point 13, 14, 15, 16: terminal 100: control circuit 103, 104, 105, 106, 107 109: terminal 110: first control unit 111: drive unit 112: oscillation unit 113: drive control unit 120: second control unit 121: first diode 122: first Zener diode 123: resistor 124: second diode 125: Second Zener Diode 127: Resistor 130: Third Controller Q1: First Switch Q2: Second Switch Q3: Third Switch

Claims (11)

A normally-off semiconductor first switch having a first drain terminal, a first source terminal, and a first gate terminal; a second drain terminal, a second source terminal, and a second gate terminal; A control circuit for controlling switching of a cascode element including a normally-on semiconductor second switch cascode-connected to the first switch by being connected to the first drain terminal;
A first control unit that generates a first control signal that performs switching control of the first switch, and that performs switching control of the first switch based on the first control signal;
A first source terminal is provided between the second source terminal and the first gate terminal, and a second source terminal voltage which is a voltage between the second source terminal and the first source terminal is set to a positive side. The second gate with the second source terminal as a reference by operating the first switch in a linear region so that the second source terminal voltage becomes less than the first set voltage when the voltage becomes equal to or higher than a set voltage. A second control unit for controlling the second gate terminal voltage of the terminal so as not to be biased further to the negative side than the second set voltage set to the negative side;
Equipped with a,
A third control unit configured to supplementarily bias the second source terminal voltage in synchronization with the first control signal during an off period of the first switch controlled by the first control unit ; Characteristic control circuit. The second control unit includes a third switch having a third drain terminal, a third source terminal, and a third gate terminal, a first diode, and a first Zener diode,
The third switch is connected to short-circuit or open the second source terminal and the first gate terminal;
An anode terminal of the first diode is directly or indirectly connected to the second source terminal; a cathode terminal of the first diode is directly or indirectly connected to the third gate terminal;
The anode terminal of the first Zener diode is directly or indirectly connected to the third gate terminal, and the cathode terminal of the first Zener diode is directly or indirectly connected to the second source terminal. The control circuit according to claim 1. The second control unit includes a second diode and a second Zener diode,
The anode terminal of the second diode is directly or indirectly connected to the second source terminal, and the cathode terminal of the second diode is directly or indirectly connected to the first gate terminal;
The anode terminal of the second Zener diode is directly or indirectly connected to the first gate terminal, and the cathode terminal of the second Zener diode is directly or indirectly connected to the second source terminal. The control circuit according to claim 1. A normally-off semiconductor first switch having a first drain terminal, a first source terminal, and a first gate terminal; a second drain terminal, a second source terminal, and a second gate terminal; A control circuit for controlling switching of a cascode element including a normally-on semiconductor second switch cascode-connected to the first switch by being connected to the first drain terminal;
A first control unit that generates a first control signal that performs switching control of the first switch, and that performs switching control of the first switch based on the first control signal;
A first source terminal is provided between the second source terminal and the first gate terminal, and a second source terminal voltage which is a voltage between the second source terminal and the first source terminal is set to a positive side. The second gate with the second source terminal as a reference by operating the first switch in a linear region so that the second source terminal voltage becomes less than the first set voltage when the voltage becomes equal to or higher than a set voltage. A second control unit for controlling the second gate terminal voltage of the terminal so as not to be biased further to the negative side than the second set voltage set to the negative side;
With
The second control unit includes a third switch having a third drain terminal, a third source terminal, and a third gate terminal, a first diode, and a first Zener diode,
The third switch is connected to short-circuit or open the second source terminal and the first gate terminal;
An anode terminal of the first diode is directly or indirectly connected to the second source terminal; a cathode terminal of the first diode is directly or indirectly connected to the third gate terminal;
The anode terminal of the first Zener diode is directly or indirectly connected to the third gate terminal, and the cathode terminal of the first Zener diode is directly or indirectly connected to the second source terminal. A control circuit characterized by. It said second switch, the control circuit according to any one of claims 1 to 4, characterized in that a high electron mobility transistor. 6. The control circuit according to claim 5 , wherein the high electron mobility transistor is one using gallium nitride or silicon carbide as a channel. 6. The control circuit according to claim 5 , wherein the high electron mobility transistor is one using an oxide semiconductor for a channel. The control circuit according to claim 7 , wherein the oxide semiconductor is tin oxide, zinc oxide, indium oxide, or a composite oxide semiconductor in which these are combined. The second set voltage is set to be lower than a second gate terminal absolute maximum rated voltage which is an absolute maximum rated voltage between the second gate terminal and the second source terminal of the second switch. control circuit according to any one of claims 1 to 8, characterized in that it is. The second control unit subtracts a voltage between the second source terminal and the first gate terminal from a first switch threshold voltage at which the first switch is turned on from the absolute maximum rated voltage of the second gate terminal. The control circuit according to claim 9 , wherein the control circuit is controlled so as to have a value lower than a subtraction value obtained. The first control unit, the second control unit and the third control unit, the control circuit according to any one of claims 1 to 10, characterized by being formed on a common semiconductor substrate.

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