JP2013059189A - Gate drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit in which the switching characteristics at the time of turn-on do not vary and is capable of stably turning on a switching element without generating power loss at the time of current regeneration.SOLUTION: A gate drive circuit turns on/off a normally-off-type switching element Q1, which has a drain, a source, and a gate, and is composed of a wide band-gap semiconductor, by applying a control signal from a control circuit to the gate of the switching element Q1. A normally-on-type switching element Q2 is connected in parallel to a series circuit that is connected between a control circuit and the gate of the switching element and is composed of a capacitor C1 and a resistor R1, and a gate of the switching element Q2 is connected to GND. The switching element Q2 supplies a gate bias current according to a gate voltage of the switching element Q1 and short-circuits between the gate and the source at the time of off of the switching element Q1.

Description

  The present invention relates to a gate drive circuit that drives a gate of a switching element.

  Since the GaN device has a potential far surpassing that of the existing Si device, its practical application is awaited. However, since a normal GaNFET is normally on, a negative power source is required.

  On the other hand, normally-off type GaNFETs are very difficult to manufacture. Further, the normally-off GaNFET has a threshold voltage of about +1 V, and the threshold voltage is very low compared to the existing SiMOSFET (Problem 1).

  Also, normally-off GaNFETs have a diode characteristic in which a large current flows when a large voltage is applied, instead of an insulating structure like a SiMOSFET between the gate and the source. For this reason, when a large voltage is applied to the gate, the normally-off GaNFET is easily broken (Problem 2).

  That is, normally-off GaNFETs cannot use the existing gate drive circuit for an SiMOSFET (IGBT (insulated gate bipolar transistor)) as they are, and need a drive circuit dedicated to normally-off GaNFETs.

  As for problem 1, it is necessary to apply a voltage sufficiently lower than the threshold voltage in order to shorten the turn-off time. It is necessary to apply a voltage sufficiently lower than the threshold voltage (+ 1V), that is, a negative voltage lower than 0V. However, it is not preferable that a negative power source is required even if the device can be normally off.

  In order to shorten the turn-on time for Problem 2, it is necessary to apply a voltage sufficiently higher than the threshold voltage (essentially, an instantaneous large current is required instead of a voltage value. It ’s better to have a higher voltage to earn). However, a high voltage of 10 V or more like SiMOSFET cannot be applied to the gate of normally-off GaNFET.

  Therefore, as a proposal for simultaneously solving the problem 1 and the problem 2, as shown in FIGS. 8A to 8C, a capacitor is inserted at a place where a gate resistance in a normal MOSFET drive circuit is inserted. There is a method of applying a CR parallel circuit of C1 and resistor R1.

2010-511165 gazette

  However, in this method, as shown in FIG. 8, when the switching frequency or duty ratio changes, the negative voltage values P1, P2, and P3 immediately before the switching element turns on also change at the same time. Switching time) will fluctuate.

  On the other hand, a negative voltage is applied to the gate during the turn-off period and a stable turn-off state can be expected. On the other hand, a GaN FET without a built-in diode has a large voltage drop during regenerative operation (third quadrant) as shown in FIG. , Generate power loss (conduction loss).

  Further, if the frequency and duty can be limited within a certain range, the above two problems can be avoided by selecting the values of the resistor and the capacitor well, returning the gate voltage to zero volts, and performing the regenerative operation or turn-on. However, the conditions are limited and the device is vulnerable to malfunction caused by noise due to the low threshold voltage.

  It is an object of the present invention to provide a gate drive circuit that can stably turn on a switching element without causing switching characteristics at the time of turn-on and without generating power loss.

The present invention is a gate drive circuit that drives a switching element on and off by applying a control signal from a control circuit to the gate of a normally-off type switching element that has a drain, a source, and a gate and is made of a wide band gap semiconductor. A series circuit of a first capacitor and a first resistor connected between the control circuit and the gate of the switching element, and a normally-on type switching element connected in parallel with the series circuit,
The drain of the normally-on type switching element is connected to the control circuit, the source is connected to the gate of the normally-off type switching element, and the gate is a connection point between the source of the normally-off type switching element and the GND of the control circuit. It is characterized by being connected to.

According to the present invention, the normally-on type switching element is delayed with respect to the OFF signal of the control signal and short-circuits between the gate and the source of the switching element, so that the charge stored in the first capacitor is Since the discharge is also made through the short-circuit means via the first resistor and the normally-on type switching element, the switching characteristics at the time of turn-on do not fluctuate, and the switching element can be stably turned on without generating power loss. Can do.
When an ON signal of the control signal is input, an instantaneous large current flows from the series circuit of the first capacitor and the first resistor, and the normally-on type switching element normally switches off the normally-off type. Since the gate bias current is decreased in accordance with the increase in the gate voltage of the element, the optimum bias drive can be performed without flowing an excessive bias current.

FIG. 3 is a circuit configuration diagram of a gate drive circuit according to the first embodiment and a gate characteristic diagram of each switching element. FIG. 3 is a sequence diagram of the gate drive circuit according to the first embodiment. FIG. 6 is a circuit configuration diagram of a gate drive circuit according to a second embodiment and a gate characteristic diagram of each switching element. 6 is a sequence diagram of a gate drive circuit according to Embodiment 2. FIG. FIG. 7 is a circuit configuration diagram of a gate drive circuit according to a third embodiment and a gate characteristic diagram of each switching element. FIG. 10 is a sequence diagram of the gate drive circuit according to the third embodiment. It is a circuit block diagram of the conventional gate drive circuit. It is a figure which shows a mode that a turn-on characteristic fluctuates with the change of the frequency of a conventional gate drive circuit, or a duty. It is a figure which shows the characteristic of the voltage versus current of GaNFET.

  Hereinafter, a gate drive circuit according to an embodiment of the present invention will be described.

FIG. 1A is a circuit configuration diagram of the gate drive circuit according to the first embodiment of the present invention. In the gate drive circuit 1 shown in FIG. 1A, a pulse signal circuit V1 corresponding to a control circuit is connected to both ends of the gate drive circuit.
FIG. 1B is a gate characteristic diagram of each switching element of the gate drive circuit according to the first embodiment of the present invention. In the first embodiment, the absolute value of the gate voltage threshold value of the switching element Q2 is set higher than that of the switching element Q1.

  The switching element Q1 is made of a normally-off type GaNFET and has a gate, a drain, and a source. A CR series circuit of a capacitor C1 and a resistor R1 is connected between the gate of the switching element Q1 and the connection point of the pulse signal circuit V1.

  A pulse signal Vin is output from the pulse signal circuit V1, and is applied to the gate of the switching element Q1 through a CR series circuit of a capacitor C1 and a resistor R1.

  Moreover, the gate drive circuit 1 of Example 1 has connected the switching element Q2 in parallel with CR series circuit. The switching element Q2 is a normally-on type switching element, the drain is connected to the gate drive circuit 1, and the source is connected to the gate of the switching element Q1. The gate of the switching element Q2 is connected to the connection point between the GND of the gate drive circuit 1 and the source of the switching element Q1.

The switching element Q2 pulls out the charge of the capacitor C1 in the CR series circuit of the capacitor C1 and the resistor R1, and at the same time, shorts between the gate and the source of the switching element Q1. Does the switching element Q2 have an impedance during the ON period of the switching element Q1? Or although it is an OFF state, it transfers to an ON state in the timing which switched off the switching element Q1.
Furthermore, the source-gate voltage −Vg2 of the switching element Q2 during the period in which the switching element Q1 is on is the same voltage as the gate voltage Vg1 of the switching element Q1.
Therefore, as shown in the gate voltage vs. drain current characteristic of FIG. 1B, the source-gate voltage −Vg2 approaches the threshold voltage | Vg2 (th) | that becomes the cut-off current as the gate voltage Vg1 rises. Element Q2 will reduce the current that biases the gate of switching element Q1. That is, an excessive drive current of a bias current flowing through the gate of the switching element Q1 is limited.

FIG. 2 is a sequence diagram of the gate drive circuit 1 according to the first embodiment of the present invention. FIG. 2 shows the pulse signal Vin output from the pulse signal circuit V1, the gate voltage Vg1 of the switching element Q1 (= the source-gate voltage of the switching element Q2−Vg2), the drain voltage Vds of the switching element Q1, and the switching element. The drain current Ids2 of Q2 is shown.
The pulse signal Vin from the pulse signal circuit V1 is input to the gate drive circuit 1 during the time t0 to t2 in FIG.

Here, the source-gate voltage -Vg2 between times t0 and t1 has an absolute value higher than the threshold voltage Vg2 (th) of the switching element Q2, and therefore the drain current Ids2 does not flow.
During the period between the times t1 and t2, the absolute value voltage is lower than the threshold voltage Vg2 (th), so that the drain current Ids2 flows, becomes the gate current of the switching element Q1, and is biased.
Therefore, the gate current of the switching element Q1, that is, the bias current can be set by selecting the threshold voltage of the source-gate voltage of the switching element Q2 higher than the gate voltage of the switching element Q1.
Since the gate voltage of switching element Q1 at time t0 does not reach the threshold voltage of the source-gate voltage of switching element Q2, the drain current of switching element Q2 flows only at the moment of time t0.
Further, even when there is an external noise biased to a negative potential during the time t0 to t2, which is the ON period of the switching element Q1, the absolute value of the source-gate voltage of the switching element Q2 tends to decrease. The element Q1 can be stably kept on.

Next, during the period from time t2 to t4 in FIG. 2, the pulse signal Vin from the pulse signal circuit V1 is supplied with 0V voltage to the gate drive circuit 1 and with the off signal.
The charge of the first capacitor C1 in the CR series circuit of the first capacitor C1 and the first resistor R1 is discharged during the period of time t2 to t3. Here, since the gate voltage Vgs2 of the switching element Q2 is applied to the positive electrode to 0V in the period of time t2 to t3, the switching element Q2 is turned on, and the charge of the first capacitor C1 is passed through the first resistor R1. To discharge.
Therefore, the drain current Ids2 flows during the period from time t2 to time t3.
Further, at time t2, since the gate voltage of the switching element Q1 is biased to a negative potential by the charging voltage of the first capacitor C1, it can be seen that the drain voltage Vds1 is instantaneously turned off.

During the period from time t3 to time t4, since the voltage of the gate voltage Vgs2 of the switching element Q2 is 0 V, the switching element Q2 is turned on, and the gate and the source of the switching element Q1 are short-circuited.
For this reason, although not shown, when the regenerative current is about to flow between the source and drain of the switching element in the period from time t3 to time t4, the voltage between the gate and source of the switching element Q1 is 0 V. The regenerative current can be flowed by the diode operation of the third phenomenon shown. Therefore, the loss can be reduced as compared with a state where the gate-source voltage of the switching element Q1 is biased to a negative potential.
In addition, during the period from time t2 to t4 when the switching element Q1 is in the OFF state, the switching element Q1 is either biased to a negative potential or the gate and the source are short-circuited. An off state can be maintained.

  According to the above configuration, when the switching element Q1 is turned on, the gate overcurrent protection of the switching element Q2 is realized at the time of high-speed switching and the subsequent on-operation due to the effect of the CR series circuit.

  When the switching element Q1 is turned off, a negative voltage due to the charge (voltage) stored in the capacitor C1 is applied to the gate of the switching element Q1, thereby realizing a fast turn-off of the switching element Q1.

In addition, the switching element Q2 is turned on at time t3 after the switching element Q1 is turned off (time t2). For this reason, the electric charge stored in the capacitor C1 is discharged through the switching element Q2 in addition to the resistor R1.
If the switching element Q2 has a sufficiently low impedance compared to the resistor R1, the charge of the capacitor C1 is completely discharged during a very short time during the turn-off period. The switching element Q1 can be stably turned on regardless of the frequency and duty ratio by bringing the capacitor C1 into a completely discharged state immediately before the start of turn-on.

  Further, since the switching element Q2 is in the ON state even during the regenerative operation period, the regenerative operation that is resistant to noise and has little power loss can be achieved by stably setting the gate-source voltage of the switching element Q1 to zero volts. realizable.

  Further, by configuring the switching element Q1 and the switching element Q2 with an integrated circuit on the same substrate, variations between elements can be stabilized and integrated.

FIG. 3 is a circuit configuration diagram of the gate drive circuit according to the second embodiment of the present invention and a gate characteristic diagram of each switching element. In the gate drive circuit 1a shown in FIG. 3A, a pulse signal circuit V1 corresponding to a control circuit is connected to both ends of the gate drive circuit.
FIG. 3B is a gate characteristic diagram of each switching element of the gate drive circuit according to the first embodiment of the present invention. In the second embodiment, it is preferable that the absolute value of the gate voltage threshold value of the switching element Q2 is set to be equal to or lower than that of the switching element Q1.

  The circuit configuration of the second embodiment is different from that of the first embodiment in that the gate threshold condition of the switching element is changed, a resistor R2 is added, and the resistor R2 is connected in parallel with the CR series circuit.

FIG. 4 is a sequence diagram of the gate drive circuit 1a according to the second embodiment of the present invention.
In the second embodiment, the gate current waveform of the switching element Q1 is substantially the same as the sequence of the first embodiment. However, unlike the first embodiment, the drain current of the switching element Q2 does not flow during the time t1 to t2 in FIG. .
Although not shown in FIG. 4, a current for biasing the gate of the switching element Q1 flows through the resistor R2 during the period from time t1 to time t2.

  As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained.

FIG. 5 is a circuit configuration diagram of a gate drive circuit according to a third embodiment of the present invention and a gate characteristic diagram of each switching element. In the gate drive circuit 1b shown in FIG. 5A, a pulse signal circuit V1 corresponding to a control circuit is connected to both ends of the gate drive circuit.
FIG. 5B is a gate characteristic diagram of each switching element of the gate drive circuit according to the first embodiment of the present invention. In the third embodiment, as in the first embodiment, the absolute value of the gate voltage threshold value of the switching element Q2 is set higher than that of the switching element Q1, and is preferably higher than the forward voltage VF of the diode D1.

In the gate drive circuit 1b according to the third embodiment of the present invention, a capacitor C2 and diodes D1 and D2 are added to the first embodiment. In detail, the diode D2 is connected in parallel with the CR series circuit. The source of the switching element Q2 is connected to the gate of the switching element Q1 through the anode and cathode of the diode D1, and one terminal of the added capacitor C2 is connected. The other terminal of the capacitor C2 is connected to the gate of the switching element Q2.
The diodes D1 and D2 are preferably low forward voltage diodes such as Schottky barrier diodes.

FIG. 6 is a sequence diagram of the gate drive circuit 1b according to the third embodiment of the present invention.
In the third embodiment, the gate current waveform when the switching element Q1 is on is substantially the same as the sequence of the first embodiment.
However, at time t2 in FIG. 6 when the switching element Q1 is OFF, the drain current of the switching element Q2 flows with a slight delay unlike the first embodiment. This is because the pulse signal Vin becomes 0 V at time t2, and a negative bias voltage due to the charging voltage of the capacitor C1 is applied to the source of the switching element Q2 via the diode D1, but the capacitor C2 charged before time t2 The voltage between the gate and source of the switching element Q2 is applied with a delay due to the discharge of the electric charge. For this reason, the discharge operation of the capacitor C1 of the CR series circuit due to the ON operation of the switching element Q2 is started with a delay, and the turn-off operation of the switching element Q1 becomes faster.

However, the discharge voltage of the capacitor C1 of the CR series circuit in the period of time t2 to t3 remains for the forward voltage VF of the diode D1, but the discharge time constant of the capacitor C1 of the CR series circuit that can sufficiently obtain the period of t3 to t4. By setting, it is possible to stabilize the turn-on operation at the next time t5.
Further, the off period of the switching element Q1 during the period from the time t2 to the time t3 is also connected by the forward voltage of the diode D2.

  As described above, in Example 3, the same operation waveform is obtained during the ON period of the switching element Q1, but the turn-off speed can be further increased when the switching element Q1 is OFF, and the loss at the time of turn-off is reduced. Can do.

  Further, the switching element applied to the present invention may be not only GaNFET but also SiC. The present invention is also applicable to a device having a low threshold voltage and a JFET (junction FET) behavior that is not an insulated gate.

DESCRIPTION OF SYMBOLS 1 Gate drive circuit Q1 Normally-off type switching element Q2 Normally-on type switching element C1, C2 Capacitor D1, D2 Diode V1 Pulse signal circuit R1 Resistance

Claims (5)

A gate driving circuit for driving the switching element on and off by applying a control signal from a control circuit to the gate of a normally-off type switching element having a drain, a source, and a gate and made of a wide band gap semiconductor;
Connected between the control circuit and the gate of the switching element, a series circuit of a first capacitor and a first resistor;
Furthermore, a normally-on type switching element connected in parallel with the series circuit,
The drain of the normally-on type switching element is connected to the control circuit, the source is connected to the gate of the normally-off type switching element, and the gate is a connection between the source of the normally-off type switching element and the GND of the control circuit. A gate driving circuit characterized by being connected to a point. 2. The gate drive circuit according to claim 1, wherein an absolute value of a gate threshold voltage of the normally-on switching element is higher than an absolute value of a gate threshold voltage of the normally-off switching element. A gate driving circuit for driving the switching element on and off by applying a control signal from a control circuit to the gate of a normally-off type switching element having a drain, a source, and a gate and made of a wide band gap semiconductor;
A series circuit connected between the control circuit and the gate of the switching element, and comprising a first capacitor and a first resistor;
A normally-on type switching element connected in parallel to the series circuit and a parallel circuit in which a second resistor is connected in parallel;
The drain of the normally-on type switching element is connected to the control circuit, the source is connected to the gate of the normally-off type switching element, and the gate is a connection between the source of the normally-off type switching element and the GND of the control circuit. Connected to the point
The gate drive circuit according to claim 1, wherein an absolute value of a gate threshold voltage of the normally-on switching element is lower than an absolute value of a gate threshold voltage of the normally-off switching element.   4. The gate driving circuit according to claim 1, wherein the normally-on type switching element is made of a wide band gap semiconductor.   5. The gate driving circuit according to claim 4, wherein the normally-off type switching element and the normally-on type switching element are constituted by an integrated circuit on the same substrate.

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