JP2009153315A - Power conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power conversion apparatus that prevents the drop of its power conversion efficiency by controlling a surge voltage due to the recovery of a diode, and also prevents an increase in loss at turn on of a semiconductor switching element. <P>SOLUTION: The apparatus includes a first gate driving circuit 7, which determines the switching speed of the first semiconductor switching element with a gate resistor and drives the first semiconductor switching element, and a second gate driving circuit 8, in which a parallel circuit, which is composed of a p-channel type MOS-FET 15, being a switching element being switched on after a predetermined time since start of charge of the gate of the second semiconductor switching element, and a Zener diode 16, is connected in series to the output end of a control pulse generating circuit 12, which supplies control pulses to the semiconductor switching element, and further the output end of the parallel circuit is connected to the gate terminal of the second semiconductor switching element via a gate resistor 17, thereby it drives the second semiconductor switching element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power conversion device using a semiconductor switching element, and more particularly to a gate drive circuit for the semiconductor switching element.

  In a power conversion device configured using a semiconductor switching element, a surge voltage is generated when the semiconductor switching element is switched. When the current increases / decreases at the rate of change di / dt during switching, an induced voltage (L · di / dt) is generated in a spike shape with respect to the floating inductance L of the wiring itself. When the switching speed of the semiconductor switching element is increased, the rate of current change increases, so that the generated surge voltage increases and may be destroyed. For this reason, various snubber technologies, inductance reduction technologies, and gate driving methods for semiconductor switching elements have been devised to suppress surge voltage (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 3-63457

  A power converter such as a pulse width modulation (PWM) inverter has a bridge circuit in which two semiconductor switching elements are connected in series, and when load current flows in a continuous mode, it is in antiparallel to the semiconductor switching elements. Very often it is operated in reflux mode with connected diodes. However, when the reverse-side semiconductor switching element is turned on when returning from the reflux mode, an excessive surge voltage having a high voltage change rate is generated by diode recovery generated by a diode connected in antiparallel to the semiconductor switching element. There is a method of reducing the wiring inductance to suppress the surge voltage, but there is a limit depending on the circuit configuration. Therefore, to suppress the surge voltage due to diode recovery, the surge can be suppressed by slowing the turn-on speed of the semiconductor element to be turned on and suppressing the recovery current. However, in the method of simply increasing the gate resistance value and slowing the switching, Loss during switching increases.

  The present invention provides a power conversion device capable of suppressing a decrease in power conversion efficiency by suppressing a surge voltage due to diode recovery and minimizing an increase in loss when the semiconductor switching element is turned on. It is the purpose.

  The present invention includes a pair of first semiconductor switching elements connected in reverse parallel to each other in series, an output polarity fixing arm that switches the first semiconductor switching element when the output polarity is switched, and a diode in reverse parallel. A power conversion comprising a single-phase full-bridge inverter comprising a pair of connected second semiconductor switching elements connected in series, and a PWM switching arm that constantly PWM-switches the second semiconductor switching elements to adjust the output value In the apparatus, a gate resistance determines a switching speed of the first semiconductor switching element, a first gate driving circuit for driving the first semiconductor switching element, and a control for supplying a gate control pulse to the second semiconductor switching element The second semiconductor switch is connected to the output terminal of the pulse generation circuit. A parallel circuit of a switching element and a Zener diode or a resistor that is turned on after a predetermined time from the start of charging the gate of the element is connected in series, and the output terminal of the parallel circuit is connected to the second semiconductor switching element via a gate resistor. A second gate drive circuit connected to a gate terminal and driving the second semiconductor switching element.

  According to the power conversion device of the present invention, it is possible to reduce the recovery current by reducing the recovery current, and after the recovery is completed, the on-speed is increased, so that the loss of the semiconductor switching element caused by the turn-on is increased. In addition, since the turn-off loss does not change because the turn-off speed is determined only by the gate resistance, it is possible to suppress a decrease in power conversion efficiency.

Embodiment 1.
Hereinafter, the power conversion device according to the first embodiment of the present invention will be described.
FIG. 1 is a block circuit diagram showing a basic configuration of a power converter according to the present invention. This power conversion device is composed of a pair of first semiconductor switching elements Qa and Qb controlled by a gate drive circuit (first gate drive circuit) 7, and an output that switches only when the output of the power conversion device is switched. It has a fixed polarity arm 5 and a PWM switching arm 6 which is composed of a pair of second semiconductor switching elements Qc and Qd controlled by a gate drive circuit (second gate drive circuit) 8 and is always PWM-switched. The DC power obtained from the DC power source 1 is converted to AC power, and the output power is supplied to an AC load 10 represented by a power system through an output filter 9. The PWM switching arm 6 performs PWM switching to adjust the output value of voltage or current.

Each of the semiconductor switching elements Qa to Qd used in the present power converter is an N-channel type MOS-FET, and a free wheel diode (hereinafter referred to as FWD) is connected in antiparallel to the MOS-FET.
Moreover, in this power converter, as shown in FIG. 1, there are floating inductances 3 and 4 due to the wiring between the capacitor 2 of the DC bus and each arm. Actually, inductance exists also in other wiring portions, but since the magnitude of the floating inductance is sufficiently smaller than the above-described floating inductances 3 and 4, the description thereof is omitted.

The power converter according to the present invention operates as follows.
When the inverter 100 outputs positive AC to the AC load 10, the semiconductor switching element Qb of the output polarity fixing arm 5 is turned on, the semiconductor switching elements Qc and Qd are switched by PWM, and a predetermined voltage is output. To do. Similarly, when outputting a negative voltage, the semiconductor switching element Qa is turned on, the semiconductor switching elements Qc and Qd are switched by PWM, and a predetermined voltage is output. With this operation, the inverter converts DC power into AC power.

Next, a surge voltage generated in the switching element due to diode recovery will be described.
When outputting positive alternating current, the semiconductor switching element Qc passes through the semiconductor switching element Qd or a free wheel diode (hereinafter referred to as FWD) connected in antiparallel and the semiconductor switching element Qb in the on state while the semiconductor switching element Qc is off. Current flows in reflux mode. A short-circuit prevention period called dead time is provided between the pair of semiconductor switching elements of each arm that is bridged so that a short circuit does not occur during switching, and both elements of each arm are turned off during that period. Therefore, current always flows through the FWD before the semiconductor switching element Qc is turned on. Therefore, diode recovery occurs in the FWD of the semiconductor switching element Qd, and the recovery current becomes a short-circuit current that flows along a path in which the DC bus is short-circuited by the semiconductor switching element Qc and FWD. A surge voltage Vsg1 as shown in FIG. 2 is generated between the drain and source terminals of the semiconductor switching element Qd, and this surge voltage often has a very high voltage change rate (dV / dt) and peak value.
Similarly, when the inverter 100 outputs negative AC, a current flows in the reflux mode through the semiconductor switching element Qc or FWD and the semiconductor switching element Qa while the semiconductor switching element Qd is off. Therefore, a surge voltage Vsg1 due to diode recovery as shown in FIG. 2 is generated in the semiconductor switching element Qc.

The surge voltage Vsg1 generated by the diode recovery shown in FIG. 2 is obtained by the following equation (1).
Vsg1 ＝ L ・ d (irr) / dt (1)
Here, irr is a recovery current.
L in the equation (1) is an inductance value that is the sum of the floating inductances 3 and 4 inside the module.
When the floating inductances 3 and 4 are very large and the generated surge voltage is not negligible with respect to the bus voltage Vdd, the surge voltage exceeds the element rating and results in destruction. In particular, in the case of a MOS-FET, even if the MOS-FET is an avalanche-resistant product, the avalanche resistance is guaranteed for surges that occur due to turn-off that is normally switched, but it occurs for reasons other than its own turn-off. Therefore, it is difficult to guarantee the voltage fluctuation between the drain and the source due to the avalanche resistance, and the breakdown is likely to occur. Therefore, it is necessary to suppress the diode recovery surge.
From equation (1), in order to reduce the surge voltage, it is necessary to reduce the stray inductance L or decrease the current change rate d (irr) / dt. However, there is a limit to reducing the stray inductance depending on the circuit configuration. Therefore, in order to suppress the surge voltage due to diode recovery, the surge can be suppressed by slowing the turn-on speed of the semiconductor element to be turned on and suppressing the recovery current. However, in the method of increasing the gate resistance value and slowing the switching, The total charging time is increased, and the switching loss increases.

In order to solve such a problem, the power conversion device according to the first embodiment includes a gate drive circuit as shown in FIG. 3 as the gate drive circuit 8 of the semiconductor switching elements Qc and Qd forming the PWM switching arm 6. It is a thing.
This gate drive circuit 8 has complementary transistors 13 and 14 connected in reverse series to a DC power supply 11 for gate drive, and the gate control pulse from the control pulse generation circuit 12 is applied to the gates of these transistors 13 and 14. The gate drive voltage Vs is output between the emitter and collector of the transistor 13, and this gate drive voltage Vs is used for a parallel circuit and a main circuit of a P-channel type MOS-FET 15 and a Zener diode 16 which are switching elements. The semiconductor element 200 (for example, the semiconductor switching element Qc) is supplied to the gate of the main circuit semiconductor element 200 through the gate resistor 17 that determines the switching speed of the gate.
Further, resistors 18 and 19 are connected between the emitter and collector of the transistor 13, and the midpoint thereof is connected to the gate of the MOS-FET 15, and in series with the resistor 19 and between the gate and source of the MOS-FET 15. A capacitor 20 is connected.

When the main circuit semiconductor element 200 is turned on, the gate drive circuit 8 first turns on the transistor 14 to supply the gate drive voltage Vs to the main circuit semiconductor element 200, but the P-channel type MOS-FET 15 Since the current is passed through the Zener diode 16 because it is off, the gate of the main circuit semiconductor element 200 is driven by a voltage obtained by subtracting the Zener voltage of the Zener diode 16 from the gate drive voltage Vs.
In the meantime, the capacitor 20 is charged through the resistor 19. Since the P-channel type MOS-FET 15 is turned on when the voltage difference between the source and gate exceeds the gate threshold voltage of the element, the MOS-FET 15 is turned on after the transistor 14 is turned on by the resistor 19 and the capacitor 20. It is possible to set a delay time until turning on. As for the delay time to be set, it is sufficient if the sum of the time from the start of charging the gate of the main circuit semiconductor element 200 to the gate threshold voltage Vth and the recovery period of the diode is sufficient.
When the MOS-FET 15 is turned on, it is charged at a speed determined by the gate drive voltage Vs and the gate resistance 17, so that the turn-on of the main circuit semiconductor element 200 can be accelerated, and the loss generated during switching increases. Can be suppressed. Actually, the charging speed is determined by the total value of the on-resistance of the gate resistor 17 and the MOS-FET 15, but the on-resistance of the MOS-FET 15 is sufficiently smaller than the other resistances and will not be described.

FIG. 4 shows that the gate voltage rising waveform 32 in the case of using the above-described gate drive circuit 8 in the first embodiment and the gate resistance having the same value as the gate resistance 17 of the above-described gate drive circuit 8 are used. In this case, the rising waveform 30 of the gate voltage and the rising waveform 31 of the gate voltage when driven by only a resistor having a value larger than the gate resistor 17 capable of suppressing the recovery surge to the same extent as when the gate drive circuit 8 is used. Is shown.
As for turn-off, the gate of the main circuit semiconductor element 200 is discharged in the current loop flowing through the gate resistor 17, the Zener diode 16 or the MOS-FET 15, and the transistor 13, so that the switching speed does not change, and the loss at turn-off is It does not change.

  Here, the resistor 18 in FIG. 3 is a gate-source capacitive discharge resistor of the MOS-FET 15 and has a value sufficiently larger than the resistor 19. Further, although the capacitor 20 is inserted in the circuit of FIG. 3, since the MOS-FET 15 has a gate-source capacitance, the delay time can be set only by the capacitance and the resistor 19. -Whether or not the capacitor 20 is inserted may be determined depending on the gate-source capacitance of the FET 15. In an electronic circuit, noise is likely to be superimposed if the resistance becomes too large. Therefore, in this embodiment, the delay time is determined by inserting a separate capacitor 20 so that the value of the resistance 19 does not increase.

  On the other hand, the gate drive circuit 7 of the semiconductor switching elements Qa and Qb of the output polarity fixing arm 5 can be handled only by increasing the value of the gate resistance without using the circuit of FIG. Since the output polarity fixed arm 5 switches only when the positive / negative output polarity of the power converter is switched, the switching loss generated in this arm is neglected compared to the switching loss of the PWM switching arm 6 that performs PWM switching at a high frequency. This is a size that can be achieved, and its influence on power conversion efficiency is very small. Therefore, in the gate drive circuit 7, the component that determines the switching speed of the semiconductor switching elements Qa and Qb is only the gate resistance, and the number of components is reduced, so that the power converter can be reduced in size and cost can be reduced.

  As described above, in the power conversion device according to Embodiment 1 of the present invention, the pair of first semiconductor switching elements Qa and Qb connected in antiparallel to each other are connected in series, and the semiconductor switching element is switched when the output polarity is switched. Output polarity fixed arm 5 for switching between and a pair of second semiconductor switching elements Qc, Qd connected in reverse parallel to each other in series, and a PWM switching arm for adjusting the output value by constantly PWM switching the semiconductor switching elements In the power conversion apparatus including the single-phase full-bridge inverter 100 configured by 6, a first gate drive for driving the first semiconductor switching element by determining a switching speed of the first semiconductor switching element by a gate resistance A control pulse generator for supplying a control pulse to the circuit 7 and the semiconductor switching element; A parallel circuit of a P-channel type MOS-FET 15 and a Zener diode 16 that is a switching element that is turned on after a predetermined time has elapsed from the start of charging of the gate of the second semiconductor switching element is connected in series to the output terminal of the circuit 12. Since the output terminal of the parallel circuit is connected to the gate terminal of the second semiconductor switching element via the gate resistor 17 and the second gate driving circuit 8 drives the second semiconductor switching element, the recovery current is During the flow period, the gate voltage of the semiconductor switching element that is turned on is lowered and the drain current is limited, so that the recovery current that is a short-circuit path can be kept small. Minimize the increase in generated semiconductor switching element loss, and turn-off speed Since the turn-off loss does not change because it is determined only by the over sheet resistance, it is possible to suppress a reduction in power conversion efficiency.

Embodiment 2.
Hereinafter, a power converter according to Embodiment 2 of the present invention will be described.
In the second embodiment, the gate drive circuit 8 of the PWM switching arm 6 is improved in the same manner as the first embodiment in the power conversion device of FIG.
FIG. 5 is a circuit diagram of the gate drive circuit 8 according to the second embodiment. The complementary transistors 13 and 14 which are output stages of the gate drive voltage Vs are connected to the emitters of the P-channel type MOS-FET 15 and the resistor 21, respectively. The gate resistor 17 of the main circuit semiconductor element 200 (for example, the semiconductor switching element Qc) is connected through the parallel circuit.

When the main circuit semiconductor element 200 is turned on, the gate drive circuit 8 first tries to supply the gate drive voltage Vs to the gate by turning on the transistor 14, but since the MOS-FET 15 is turned off, the current flows through the resistor 21. Therefore, the resistance value for determining the charging current of the gate is the total value of the gate resistance 17 and the added resistance 21.
In the meantime, the capacitor 20 is charged through the resistor 19. Since the P-channel type MOS-FET 15 is turned on when the voltage difference between the source and gate exceeds the gate threshold voltage of the element, the MOS-FET 15 is turned on after the transistor 14 is turned on by the resistor 19 and the capacitor 20. It is possible to set a delay time until turning on. As for the delay time to be set, it is sufficient if the sum of the time from the start of charging the gate of the main circuit semiconductor element 200 to the gate threshold voltage Vth and the recovery period of the diode is sufficient.
When the MOS-FET 15 is turned on, the charging current of the gate flows through the MOS-FET 15 and is charged at a speed determined by the gate resistor 17, so that the turn-on of the main circuit semiconductor element 200 can be accelerated. It is possible to suppress an increase in loss that occurs during switching. Actually, the charging speed is determined by the total value of the on-resistance of the gate resistor 17 and the MOS-FET 15, but the on-resistance of the MOS-FET 15 is sufficiently smaller than the gate resistance and will not be described.

FIG. 6 shows the rising waveform 33 of the gate voltage of the main circuit semiconductor element 200 when the above-described gate drive circuit 8 in the second embodiment is used, and the same value as the gate resistance 17 of the above-described gate drive circuit 8. When the gate voltage rises when driven by only the gate resistor 30 and when driven by only a resistor having a value larger than that of the gate resistor 17 capable of suppressing the recovery surge to the same extent as when the gate drive circuit 8 is used. The rising waveform 31 of the gate voltage is shown.
As for the turn-off, the gate of the main circuit semiconductor element 200 is discharged in the current loop passing through the gate resistor 17, the diode built in the MOS-FET 15, and the transistor 13, so that the switching speed does not change and the loss at turn-off does not change.

  If the gate driving circuit 8 according to the second embodiment is used, the gate current of the element that is turned on can be lowered and the drain current can be limited during the period in which the recovery current flows, as in the first embodiment. Therefore, the current change rate can be reduced, and the surge voltage can be reduced.

Embodiment 3.
FIG. 7 shows the gate drive circuit 8 according to the third embodiment, in which a capacitor 22 is inserted in parallel with the resistor 21 in the second embodiment.
In the second embodiment, only the gate resistance is increased, and the time until the gate is charged up to the gate threshold voltage Vth of the semiconductor element for main circuit 200 becomes longer, and the time required for total switching becomes longer. In the third embodiment, since the capacitor 22 is inserted in parallel with the resistor 21, a current is passed through the capacitor 22 to let the resistor 21 pass through during the period when the gate of the main circuit semiconductor element 200 is equal to or lower than the gate threshold voltage Vth. be able to.
When the capacitor 22 is charged to a predetermined voltage, no current flows through the capacitor 22 and thereafter the gate is charged with a charging current determined by the resistor 21 and the gate resistor 17. Therefore, the total charging time of the gate is shortened.

If the resistor 21 is sufficiently large, the main charge as represented by the approximate expression (2) can be obtained from the ratio of the capacitance C27 of the capacitor 22 and the gate-source capacitance CGS of the main circuit semiconductor element 200 during initial charging. Since the gate-source voltage value VGSa of the circuit semiconductor element 200 is charged, the capacitance of the capacitor 22 may be determined so that this voltage value is at least the gate threshold voltage Vth of the element. The gate drive voltage is Vs [V].
VGSa ≒ Vs × {C27 ÷ (C27 + CGS)} [V] ・ ・ ・ ・ ・ (2)
If the MOS-FET 15 is turned on as in the second embodiment, the gate is driven only by the gate resistor 17 as in the second embodiment. Therefore, in the third embodiment, the same effect as in the second embodiment is achieved. It is possible to obtain

FIG. 8 shows the rising waveform 34 of the gate voltage of the semiconductor element 200 for the main circuit and the same value as the gate resistance 17 of the gate drive circuit 8 described above when the above-described gate drive circuit 8 in the third embodiment is used. When the gate voltage rises when driven by only the gate resistor 30 and when driven by only a resistor having a value larger than that of the gate resistor 17 capable of suppressing the recovery surge to the same extent as when the gate drive circuit 8 is used. The rising waveform 31 of the gate voltage is shown.
If the resistor 21 is made sufficiently large, the rise of the gate voltage can be suppressed and kept at a substantially constant value in the recovery period as shown by the waveform 34 in FIG. This is higher than in the second embodiment.
Since the capacitor 22 is short-circuited when the MOS-FET 15 is turned on, the gate resistance value is divided into a resistor 23 and a gate resistor 17 as shown in FIG. You may make it suppress so that an electric current may not become excessive. At this time, after the MOS-FET 15 is turned on, the charge rate of the gate of the main circuit semiconductor element 200 is determined by the total value of the parallel resistance value of the resistors 21 and 23 and the gate resistor 17.

Embodiment 4.
In the fourth embodiment, the gate drive circuit 8 of the PWM switching arm 6 uses an N-channel MOS-FET 24 as a switching element instead of the P-channel MOS-FET 15 used in the first embodiment. It is.
FIG. 10 shows a gate drive circuit 8 according to the fourth embodiment. Since the MOS-FET 24 used is an N-channel type, the potential difference between the gate and the source needs to be equal to or higher than the gate threshold voltage in order to be turned on. The switching is performed by placing the capacitor 26 and charging the capacitor 26 to raise the gate potential. Immediately after the transistor 14 is turned on, the source potential of the MOS-FET 24 is higher than the gate by the voltage obtained by subtracting the Zener voltage of the Zener diode 16 from the gate drive voltage Vs. Considering this potential difference, it is necessary to make the value smaller than the resistance 23 used in the first embodiment. The resistor 27 is a gate-source capacitance discharge resistor of the MOS-FET 24.

  In the gate drive circuit 8 of the fourth embodiment, when the MOS-FET 24 is turned on, the source potential rises to the potential of the gate drive voltage, so that the MOS-FET 24 is turned off. Since the source potential is lowered again by turning it off, the MOS-FET 24 is repeatedly switched so that it is turned on again. In the period of repeating the switching, a large charging current due to the gate driving voltage Vs flows for each switching, although the time is short. The gate-source voltage increases. However, since the large current is intermittent as described above, the rise of the gate voltage is slower than in the first embodiment in which charging can be continuously performed at a high voltage.

FIG. 11 shows only the rising waveform 35 of the gate voltage of the main circuit semiconductor element 200 and the gate resistor 17 having the same value as that of the above gate drive circuit 8 when the above gate drive circuit 8 in the fourth embodiment is used. Waveform of the gate voltage when driven by a gate voltage, and the gate voltage when driven by only a resistor having a value larger than the gate resistor 17 capable of suppressing the recovery surge to the same extent as when using the gate drive circuit 8 A rising waveform 31 is shown.
There is no problem in reducing the gate voltage until the MOS-FET is first turned on, and the effect of suppressing the surge by the recovery of the diode can be obtained in the fourth embodiment as well as the first embodiment. It is.
In addition, it is possible to reduce the loss associated with switching at turn-on rather than driving with a gate resistor having only a large resistor that can suppress the surge voltage to the same extent.

Embodiment 5.
FIG. 12 is a circuit diagram showing the gate drive circuit 8 according to the fifth embodiment, in which the Zener diode 16 shown in the fourth embodiment is changed to a resistor 21.
Until the MOS-FET 24 is first turned on after the transistor 14 is turned on, the gate of the main circuit semiconductor element 200 can be charged at a charging rate determined by the gate resistor 17 and the resistor 21, and a surge voltage due to diode recovery is suppressed. The effect is the same as that of the second embodiment. As for the behavior of the circuit after the MOS-FET 24 is first turned on, the switching of the MOS-FET 24 is repeated in the fifth embodiment as in the fourth embodiment.
Since a large charging current due to the low gate resistance flows for each switching in a period in which switching is repeated, the main circuit semiconductor element 200 is faster than driving with only a large resistor capable of suppressing the surge voltage to the same extent. The gate-source voltage increases. However, since the large current is intermittent as described above, the rise of the gate voltage is slower than in the second embodiment in which charging can be continuously performed at a high voltage.

FIG. 13 shows only the rising waveform 36 of the gate voltage of the semiconductor element 200 for the main circuit and the gate resistor 17 having the same value as that of the above gate drive circuit 8 when the above gate drive circuit 8 in the fifth embodiment is used. Waveform of the gate voltage when driven by a gate voltage, and the gate voltage when driven by only a resistor having a value larger than the gate resistor 17 capable of suppressing the recovery surge to the same extent as when using the gate drive circuit 8 A rising waveform 31 is shown.
Also in the fifth embodiment, similarly to the fourth embodiment, it is possible to reduce the loss at the time of switching as compared with the case of driving with only a large gate resistance that can suppress the surge voltage to the same extent.

Embodiment 6.
FIG. 14 is a circuit diagram showing the gate drive circuit 8 according to the sixth embodiment, which is a circuit in which a capacitor 22 is connected in parallel to the resistor 21 shown in the fifth embodiment.
Since the operation from when the transistor 14 is turned on to when the MOS-FET 24 is first turned on is the same as the operation of the gate drive circuit shown in the third embodiment, the effect of suppressing the surge voltage due to diode recovery is described in the embodiment. The same effect as 3 is obtained.
As for the behavior of the circuit after the MOS-FET 24 is first turned on, the MOS-FET 24 repeats switching in the sixth embodiment as in the fourth embodiment.
Since the capacitor 22 is discharged every time the MOS-FET 24 is turned on in the period of repeated switching, the resistor 21 is passed through until the capacitor 22 is charged even if the MOS-FET 24 is turned off. Thus, the charging speed is determined, so that charging is faster than in the fifth embodiment.

FIG. 15 shows the rising waveform 37 of the gate voltage when the above-described gate drive circuit 8 in the sixth embodiment is used, and the gate when driven only by the gate resistor 17 having the same value as that of the above-described gate drive circuit 8. A voltage rising waveform 30 and a gate voltage rising waveform 31 when driven by only a resistor having a value larger than the gate resistor 17 capable of suppressing the recovery surge to the same extent as when the gate driving circuit 8 is used are shown. Yes.
In the sixth embodiment, as in the fourth and fifth embodiments, the switching loss can be reduced as compared with the case of driving with only a large resistance gate resistor capable of suppressing the surge voltage to the same extent. Is possible.

  As in the third embodiment, since the short-circuit current flows from the capacitor 22 when the MOS-FET 24 is turned on, the gate resistance value is divided and the resistor 23 and the gate resistor 17 are arranged as shown in FIG. You may make it restrain so that it may not become excessive. At this time, since the discharge current of the capacitor 22 is limited, the amount of decrease in the voltage of the capacitor 22 in a short ON period is reduced, so that the gate of the main circuit semiconductor element 200 for each switching is charged. The amount decreases. However, since the source potential of the MOS-FET 24 is also difficult to rise, the number of times the MOS-FET 24 is switched increases, and the total charging time is about the same as when short-circuited.

It is a block circuit diagram which shows the basic composition of the power converter device of this invention. It is a wave form diagram which shows the example of the surge voltage and recovery current which generate | occur | produce at the time of diode recovery in the power converter device of FIG. It is a circuit diagram which shows the gate drive circuit in Embodiment 1 of this invention. 6 is a diagram illustrating a rising waveform of a gate voltage when the gate drive circuit according to the first embodiment is used. FIG. It is a circuit diagram which shows the gate drive circuit in Embodiment 2 of this invention. It is a figure which shows the rising waveform of the gate voltage at the time of using the gate drive circuit in Embodiment 2. FIG. It is a circuit diagram which shows the gate drive circuit in Embodiment 3 of this invention. It is a figure which shows the rising waveform of the gate voltage at the time of using the gate drive circuit in Embodiment 3. FIG. FIG. 10 is a circuit diagram showing another example of a gate drive circuit in the third embodiment. It is a circuit diagram which shows the gate drive circuit in Embodiment 4 of this invention. FIG. 10 is a diagram illustrating a rising waveform of a gate voltage when the gate drive circuit according to the fourth embodiment is used. It is a circuit diagram which shows the gate drive circuit in Embodiment 5 of this invention. FIG. 10 is a diagram illustrating a rising waveform of a gate voltage when the gate drive circuit according to the fifth embodiment is used. It is a circuit diagram which shows the gate drive circuit in Embodiment 6 of this invention. FIG. 20 is a diagram illustrating a rising waveform of a gate voltage when the gate drive circuit according to the sixth embodiment is used. FIG. 20 is a circuit diagram showing another example of a gate drive circuit in the sixth embodiment.

Explanation of symbols

1 DC power supply, 2 capacitor, 3, 4 stray inductance, 5 output polarity fixed arm, 6 PWM switching arm, 7, 8 gate drive circuit, 9 output filter, 10 AC load, 11 gate drive DC power supply, 12 control pulse generation Circuit, 13, 14 transistor, 15 P channel type MOS-FET, 16 Zener diode, 17 Gate resistance, 18, 19 resistance, 20 capacitor, 21 resistance, 22 capacitor, 23 resistance, 24 N channel type MOS-FET, 25 resistors, 26 capacitors, 27 resistors, 100 single-phase full-bridge inverter, 200 semiconductor elements for main circuit.

Claims (5)

A pair of first semiconductor switching elements connected in reverse parallel with a diode are connected in series, and an output polarity fixing arm that switches the first semiconductor switching element when the output polarity is switched, and a pair of diodes connected in reverse parallel In a power conversion device comprising a single-phase full-bridge inverter composed of a second semiconductor switching element connected in series, a PWM switching arm that constantly PWM-switches the second semiconductor switching element and adjusts an output value,
A first gate driving circuit for determining a switching speed of the first semiconductor switching element by a gate resistance and driving the first semiconductor switching element;
A switching element that is turned on after a predetermined time from the start of charging of the gate of the second semiconductor switching element and a Zener diode or a resistor are connected in parallel to an output terminal of a control pulse generating circuit that supplies a gate control pulse to the second semiconductor switching element. A second gate drive circuit for connecting the circuit in series, further connecting an output terminal of the parallel circuit to a gate terminal of the second semiconductor switching element via a gate resistor, and driving the second semiconductor switching element; A power conversion device comprising:   2. The power conversion device according to claim 1, wherein the second gate drive circuit further includes a capacitor connected in parallel to a parallel circuit of a switch element and a resistor.   The power conversion device according to claim 2, wherein the second gate drive circuit has a resistor connected in series to a switch element forming a parallel circuit.   The switch element constituting the second gate drive circuit is a P-channel type MOS-FET, and the second gate drive circuit includes a capacitor connected between the gate and source of the switch element and a second semiconductor switching element. The delay time until the switch element is turned on is determined by a resistor connected between the source of the switch and the gate of the switch element, and the second semiconductor switching element is driven. 4. The power conversion device according to any one of 3.   The switch element constituting the second gate drive circuit is an N-channel MOS-FET, and the second gate drive circuit includes a resistor connected between the gate and drain of the switch element and a second semiconductor switching element. A delay time until the switch element is turned on is determined by a capacitor connected between the source of the switch and a gate of the switch element, and the second semiconductor switching element is driven. 4. The power conversion device according to any one of 3.

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