JP6270027B2 - Semiconductor device manufacturing equipment - Google Patents

Semiconductor device manufacturing equipment Download PDF

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JP6270027B2
JP6270027B2 JP2013263176A JP2013263176A JP6270027B2 JP 6270027 B2 JP6270027 B2 JP 6270027B2 JP 2013263176 A JP2013263176 A JP 2013263176A JP 2013263176 A JP2013263176 A JP 2013263176A JP 6270027 B2 JP6270027 B2 JP 6270027B2
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semiconductor chip
semiconductor device
wiring metal
bonding
manufacturing apparatus
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JP2015119117A (en
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修二 足立
修二 足立
西村 公男
公男 西村
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Nissan Motor Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features

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  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Description

本発明は、半導体チップと配線金属とを接合して成る半導体装置の製造装置に関するものである。   The present invention relates to a semiconductor device manufacturing apparatus formed by bonding a semiconductor chip and a wiring metal.

近年の半導体装置、特に、大電流密度の所謂ハイパワーモジュールと称する半導体装置においては、高温環境下でも使用可能であることが要求されている。そのため、半導体装置の実装構造においては、高温に保持されたり、高温熱サイクルを受けたりした場合の高温耐久性に優れた接合部が強く望まれている。また、環境保全の観点からすると、Pb(鉛)フリーの接合技術が必須となっている。   2. Description of the Related Art Recent semiconductor devices, particularly semiconductor devices called high power modules having a large current density, are required to be usable even in a high temperature environment. Therefore, in a mounting structure of a semiconductor device, a joint having excellent high temperature durability when held at a high temperature or subjected to a high temperature thermal cycle is strongly desired. From the viewpoint of environmental protection, a Pb (lead) -free joining technique is essential.

このような半導体装置の実装のための接合には、現状では、Sn(錫)−Ag(銀)−Cu(銅)系のはんだが広く使われているが、使用温度がはんだの融点(例えば200℃程度)以下に制限される。また、例えば、電極がCuである接合部においては、界面にCu−Sn系の脆い金属間化合物層が生成し、高温耐久性に乏しいものとなる。そのため、接合部の高温耐久性を確保するために、いろいろな試みがなされている。   Currently, Sn (tin) -Ag (silver) -Cu (copper) based solder is widely used for bonding for mounting such semiconductor devices, but the operating temperature is the melting point of the solder (for example, It is limited to about 200 ° C. or less. Further, for example, in a joint where the electrode is Cu, a Cu-Sn brittle intermetallic compound layer is generated at the interface, resulting in poor high-temperature durability. Therefore, various attempts have been made to ensure the high temperature durability of the joint.

例えば、金属ナノ粒子の活性な表面エネルギーを利用して、低温にて凝集、接合する低温接合工法が提案されている(特許文献1参照)。この接合工法を用いれば、凝集した後の接合界面はバルク金属となるため、高い、高温耐久性を有する。   For example, a low-temperature bonding method has been proposed in which active surface energy of metal nanoparticles is used to aggregate and bond at a low temperature (see Patent Document 1). If this joining method is used, the joining interface after agglomeration becomes a bulk metal, and thus has high durability at high temperatures.

特開2004−128357号公報JP 2004-128357 A

しかしながら、特許文献1に記載の低温接合工法では、金属ナノ粒子として、Au(金)、Ag(銀)といった貴金属を用い、このような金属ナノ粒子の表面に有機物を修飾したような構造をとるため、非常に高コストなものとなり、実際に適用するには現実的ではない。また、粒子が凝集した構造となり、しかも有機物が接合プロセス時にガス化して、残存することから接合部にはボイドが存在するため、継手強度のバラツキの大きいものとなるという問題がある。   However, in the low-temperature bonding method described in Patent Document 1, noble metals such as Au (gold) and Ag (silver) are used as metal nanoparticles, and the surface of such metal nanoparticles is modified with an organic substance. Therefore, it becomes very expensive and not practical to apply. In addition, there is a problem that the structure has a structure in which particles are agglomerated, and the organic matter is gasified during the joining process and remains, so that voids exist in the joint, resulting in large variations in joint strength.

なお、高温はんだとしてはこの他に、Au系の組成を有するものとして、Au−Ge(ゲルマニウム)系はんだや、Au−Sn系はんだがあるが、これらも、貴金属であるAuを用いているため、非常に高コストなものとなり、上記同様、現実的ではない。   Other high-temperature solders include Au-Ge (germanium) solders and Au-Sn solders that have an Au-based composition, but these also use precious metal Au. It becomes very expensive and is not realistic as described above.

本発明は、上記従来の状況に鑑みてなされたものであって、その目的とするところは、低コストで高温耐久性に優れた接合を可能にすると共に、その接合の際に、接合部の酸化を阻止して充分な接合強度を確保しつつ、半導体チップの上下にある電極間の沿面絶縁距離を適切に維持することができる半導体装置の製造装置を提供することにある。また、上記の製造装置を用いて製造した高温耐久性に優れた半導体装置を提供することにある。   The present invention has been made in view of the above-described conventional situation. The object of the present invention is to enable bonding with low temperature and excellent high-temperature durability, and at the time of the bonding, An object of the present invention is to provide a semiconductor device manufacturing apparatus capable of appropriately maintaining a creeping insulation distance between electrodes above and below a semiconductor chip while preventing oxidation and securing a sufficient bonding strength. Moreover, it is providing the semiconductor device excellent in the high temperature durability manufactured using said manufacturing apparatus.

本発明に係わる半導体装置の製造装置は、半導体チップの接合面と、配線金属の少なくとも接合面との間に、各接合面の金属と共晶反応を生じる金属を含むインサート材を介在させると共に、上記接合面の酸化皮膜を破壊するための凹凸を上記接合面及びインサート材表面の少なくとも一部に設け、接合界面の少なくとも一部において半導体チップと配線金属とを直接接合して成る半導体装置を製造するものである。   In the semiconductor device manufacturing apparatus according to the present invention, an insert material containing a metal that causes a eutectic reaction with the metal of each bonding surface is interposed between the bonding surface of the semiconductor chip and at least the bonding surface of the wiring metal, Produces a semiconductor device in which irregularities for breaking the oxide film on the bonding surface are provided on at least a part of the bonding surface and the surface of the insert material, and the semiconductor chip and the wiring metal are directly bonded at at least a part of the bonding interface. To do.

そして、半導体装置の製造装置は、半導体チップ及び配線金属を相対的に加圧する加圧手段と、半導体チップ及び配線金属を加熱する加熱手段とを備えている。また、半導体装置の製造装置は、加圧手段が、半導体チップ又は配線金属の主面に接触する加圧体と、半導体チップと配線金属との接合界面から半導体チップの外側へ排出された共晶反応溶融物及び酸化皮膜から成る排出物を所定の厚さに押圧する押圧部と、半導体チップの外周部とこれに相対向する押圧部の側部との隙間に排出物が進入するのを抑制する排出物抑制手段とを備えていることを特徴としている。   The semiconductor device manufacturing apparatus includes a pressurizing unit that relatively pressurizes the semiconductor chip and the wiring metal, and a heating unit that heats the semiconductor chip and the wiring metal. Further, in the semiconductor device manufacturing apparatus, the pressurizing means is a eutectic discharged from the bonding interface between the semiconductor chip and the wiring metal to the outside of the semiconductor chip, and the pressing body that contacts the main surface of the semiconductor chip or the wiring metal. Suppresses entry of the exhaust into the gap between the pressing part that presses the discharge consisting of the reaction melt and oxide film to a predetermined thickness, and the outer peripheral part of the semiconductor chip and the side part of the pressing part opposite to this. It is characterized by having emission control means.

本発明に係わる半導体装置は、上記製造装置を用いて製造したものであって、半導体チップと配線金属を備え、半導体チップ及び配線金属が、双方の接合界面の少なくとも一部において直接接合され、この直接接合部の周囲において、共晶反応溶融物及び酸化皮膜から成る排出物が所定の厚さに押圧された状態で存在していることを特徴としている。   A semiconductor device according to the present invention is manufactured using the manufacturing apparatus described above, and includes a semiconductor chip and a wiring metal, and the semiconductor chip and the wiring metal are directly bonded at at least a part of both bonding interfaces. Around the directly joined portion, the eutectic reaction melt and the effluent composed of the oxide film are present in a pressed state with a predetermined thickness.

本発明に係る半導体装置の製造装置では、加圧手段の加圧体及び加熱手段により、インサート材を介して半導体チップ及び配線金属を相対的に加圧しながら加熱する。これにより、配線金属の接合面やインサート材表面に設けた凹凸によって接合面の酸化皮膜を破壊すると共に、接合面とインサート材との間に共晶反応を生じさせ、低温、低加圧で酸化皮膜を除去して、半導体チップと配線金属とを強固に接合する。ここで、半導体チップや配線金属の接合面には、アルミニウム系金属を採用することができると共に、インサート材には、アルミニウム系金属と共晶反応を生じるものとして、Zu(亜鉛)を主成分とする金属を採用することができる。   In the semiconductor device manufacturing apparatus according to the present invention, the semiconductor chip and the wiring metal are heated while being relatively pressurized by the pressurizing body and the heating means of the pressurizing means via the insert material. As a result, the oxide film on the joint surface is destroyed by the unevenness provided on the joint surface of the wiring metal and the surface of the insert material, and a eutectic reaction is caused between the joint surface and the insert material, which is oxidized at low temperature and low pressure. The film is removed to firmly bond the semiconductor chip and the wiring metal. Here, an aluminum-based metal can be used for the bonding surface of the semiconductor chip or the wiring metal, and the insert material is mainly composed of Zu (zinc), which causes a eutectic reaction with the aluminum-based metal. The metal to be used can be adopted.

また、上記の製造装置では、半導体チップと配線金属との接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出物として半導体チップの外側へ排出すると共に、加圧手段の押圧部により、排出物を所定の厚さに押圧する。よって、インサート材は、上記の接合界面に生じた共晶反応溶融物及び酸化皮膜を排出物として半導体チップの外側へ排出し得る大きさ(体積)であり、このような大きさにすることで接合部が大気に接触してないようにする。   Further, in the above manufacturing apparatus, the eutectic reaction melt generated at the bonding interface between the semiconductor chip and the wiring metal is discharged to the outside of the semiconductor chip as the discharge together with the oxide film, and by the pressing portion of the pressing means, Press the discharge to a predetermined thickness. Therefore, the insert material has a size (volume) that can discharge the eutectic reaction melt and the oxide film generated at the bonding interface to the outside of the semiconductor chip as discharged materials. Ensure that the joint is not in contact with the atmosphere.

このとき、上記の製造装置では、押圧部による排出物の押圧に加えて、排出物抑制手段により、半導体チップの外周部とこれに相対向する押圧部の側部との隙間に排出物の一部が進入するのを抑制して、半導体チップの外側の排出物を平坦なものにし、これにより、半導体チップの上下にある電極間の沿面絶縁距離が上記排出物によって短くなるのを防止する。   At this time, in the manufacturing apparatus described above, in addition to the pressing of the discharged matter by the pressing portion, the discharged matter suppressing means causes a discharge of the discharged material into the gap between the outer peripheral portion of the semiconductor chip and the side portion of the pressing portion facing the semiconductor chip. By suppressing the intrusion of the portion, the discharge outside the semiconductor chip is made flat, thereby preventing the creeping insulation distance between the electrodes above and below the semiconductor chip from being shortened by the discharge.

このようにして、半導体装置の製造装置によれば、貴金属やPbを用いることなく、低コストで高温耐久性に優れた接合を可能にすると共に、その接合の際に、接合部の酸化を阻止して充分な接合強度を確保しつつ、半導体チップの上下にある電極間の沿面絶縁距離を適切に維持することができる。   As described above, according to the semiconductor device manufacturing apparatus, it is possible to perform bonding with low temperature and excellent high-temperature durability without using noble metal or Pb, and at the time of bonding, oxidation of the bonded portion is prevented. Thus, it is possible to appropriately maintain the creeping insulation distance between the electrodes on the upper and lower sides of the semiconductor chip while ensuring sufficient bonding strength.

本発明に係わる半導体装置の製造装置の第1実施形態を示す平面図である。1 is a plan view showing a first embodiment of a semiconductor device manufacturing apparatus according to the present invention. 図1中のA−A線に基づく半導体装置接合前の製造装置の断面図である。It is sectional drawing of the manufacturing apparatus before the semiconductor device joining based on the AA line in FIG. 図2に続いて加圧体が半導体チップに当接した状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state in which the pressure body is in contact with the semiconductor chip following FIG. 2. 図3に続いて押圧部が排出物を押圧している状態を示す断面図(A)及び要部の拡大断面図(B)である。It is sectional drawing (A) which shows the state which the press part is pressing the discharge following FIG. 3, and the expanded sectional view (B) of the principal part. 半導体装置の製造における接合面温度及び圧力の変化を示すグラフである。It is a graph which shows the change of junction surface temperature and pressure in manufacture of a semiconductor device. 製造後の半導体装置を説明する断面図である。It is sectional drawing explaining the semiconductor device after manufacture. 半導体装置の製造装置の第2実施形態を示す要部の断面図である。It is sectional drawing of the principal part which shows 2nd Embodiment of the manufacturing apparatus of a semiconductor device. 半導体装置の製造装置の第3実施形態を示す要部の断面図であるIt is sectional drawing of the principal part which shows 3rd Embodiment of the manufacturing apparatus of a semiconductor device. 半導体装置の製造装置の第4実施形態を示す要部の断面図であるIt is sectional drawing of the principal part which shows 4th Embodiment of the manufacturing apparatus of a semiconductor device.

〈第1実施形態〉
図1及び図2に示す半導体装置の製造装置は、以下に述べる構造を備えた半導体装置1を製造するものである。半導体装置1は、半導体チップ2の接合面と、配線金属3の少なくとも接合面との間に、各接合面の金属と共晶反応を生じる金属を含むインサート材4を介在させている。さらに、半導体装置1は、上記接合面の酸化皮膜を破壊するための微細な凹凸5を上記接合面及びインサート材4の表面の少なくとも一部に設け、接合界面の少なくとも一部において半導体チップ2と配線金属3とを直接接合した構造である。
<First Embodiment>
The semiconductor device manufacturing apparatus shown in FIGS. 1 and 2 manufactures a semiconductor device 1 having a structure described below. In the semiconductor device 1, an insert material 4 containing a metal that causes a eutectic reaction with the metal of each bonding surface is interposed between the bonding surface of the semiconductor chip 2 and at least the bonding surface of the wiring metal 3. Further, the semiconductor device 1 is provided with fine irregularities 5 for breaking the oxide film on the bonding surface on at least a part of the bonding surface and the surface of the insert material 4, and at least a part of the bonding interface with the semiconductor chip 2. In this structure, the wiring metal 3 is directly joined.

図示例の半導体チップ2は、平面視で正方形状を成し、基板2Aの上下に上側電極2B及び下側電極2Cを夫々設けた三層構造である。この実施形態の半導体チップ2は、少なくとも下側電極2Cがアルミニウム系金属から成り、この下側電極2Cの下面が配線金属3との接合面である。   The semiconductor chip 2 in the illustrated example has a square shape in plan view, and has a three-layer structure in which an upper electrode 2B and a lower electrode 2C are provided above and below a substrate 2A, respectively. In the semiconductor chip 2 of this embodiment, at least the lower electrode 2C is made of an aluminum-based metal, and the lower surface of the lower electrode 2C is a joint surface with the wiring metal 3.

配線金属3は、平面視で半導体チップ1よりも充分に大きい正方形状を成すと共に、アルミニウム系合金から成るものであって、その上面に凹凸5が形成してあり、凹凸5の表面が半導体チップ2との接合面である。この凹凸5は、応力を集中させて酸化皮膜の破壊を促進させる機能さえあれば、その形状や数に制限はなく、例えば、断面三角形状や断面台形状の突条を並列に配置したものや、四角錐状の突部を縦横に配列したものを採用することができる。   The wiring metal 3 has a square shape that is sufficiently larger than the semiconductor chip 1 in plan view and is made of an aluminum-based alloy. The wiring 5 is formed with unevenness 5 on its upper surface, and the surface of the unevenness 5 is the semiconductor chip. 2 is a joint surface. As long as the unevenness 5 has the function of concentrating stress and promoting the destruction of the oxide film, the shape and number thereof are not limited. For example, the protrusions having a triangular cross section or a trapezoidal cross section are arranged in parallel. In addition, it is possible to employ a structure in which quadrangular pyramidal protrusions are arranged vertically and horizontally.

上記した半導体チップ2の下側電極2Cや配線金属3の素材であるアルミニウム系金属としては、純アルミニウム材(工業用純アルミニウム)やAlを主成分として80%以上含有する合金材を用いることができる。これらアルミニウム系金属から成る下側電極2Cや配線金属3の表面には、Alを主成分とする強固な酸化皮膜が生成している。 As the aluminum-based metal that is the material of the lower electrode 2C and the wiring metal 3 of the semiconductor chip 2 described above, a pure aluminum material (industrial pure aluminum) or an alloy material containing 80% or more of Al as a main component is used. it can. A strong oxide film mainly composed of Al 2 O 3 is formed on the surfaces of the lower electrode 2C and the wiring metal 3 made of these aluminum-based metals.

インサート材4は、Alと共晶反応を生じる金属を含むものであって、具体的には、Zn(亜鉛)を主成分とする金属(純亜鉛、亜鉛合金)や、Znと共晶反応を生じる金属とZnとの合金、例えばZnとAlを主成分とする合金、ZnとMg(マグネシウム)を主成分とする合金、ZnとCu(銅)を主成分とする合金、ZnとSn(錫)を主成分とする合金、ZnとAg(銀)を主成分とする合金、ZnとMgとAlを主成分とする合金、ZnとCu(銅)とAlを主成分とする合金、ZnとSn(錫)とAlを主成分とする合金、ZnとAg(銀)とAlを主成分とする合金の薄板や箔を用いることができる。なお、本発明において、「主成分」とは、上記金属の含有量の合計が80%以上であることを意味するものとする。   The insert material 4 includes a metal that causes a eutectic reaction with Al. Specifically, the insert material 4 has a metal (pure zinc, zinc alloy) containing Zn (zinc) as a main component, or a eutectic reaction with Zn. Alloys of the resulting metal and Zn, for example, alloys containing Zn and Al as main components, alloys containing Zn and Mg (magnesium) as main components, alloys containing Zn and Cu (copper) as main components, Zn and Sn (tin) ), An alloy mainly composed of Zn and Ag (silver), an alloy mainly composed of Zn, Mg and Al, an alloy mainly composed of Zn, Cu (copper) and Al, and Zn An alloy mainly composed of Sn (tin) and Al, or a thin plate or foil of an alloy mainly composed of Zn, Ag (silver), and Al can be used. In the present invention, the “main component” means that the total content of the metals is 80% or more.

また、インサート材4は、半導体チップ2と配線金属3との接合界面に生じた共晶反応溶融物及び酸化皮膜を排出物(B)として半導体チップ1の外側へ排出し得る大きさ(体積)を有する板状の部材である。図示例のインサート材4は、半導体チップ2と配線金属3との接合部を大気に接触させないように、平面視で半導体チップ1よりもやや大きい正方形状である。   Further, the insert material 4 has a size (volume) that can be discharged to the outside of the semiconductor chip 1 as a discharge (B) from the eutectic reaction melt and oxide film generated at the bonding interface between the semiconductor chip 2 and the wiring metal 3. It is a plate-shaped member which has. The insert material 4 in the illustrated example has a square shape slightly larger than the semiconductor chip 1 in plan view so as not to bring the joint between the semiconductor chip 2 and the wiring metal 3 into contact with the atmosphere.

上記の半導体装置1を製造するための製造装置は、上記半導体チップ2及び配線金属3を相対的に加圧する加圧手段11と、上記半導体チップ2及び配線金属3を加熱する加熱手段12を備えている。   A manufacturing apparatus for manufacturing the semiconductor device 1 includes a pressurizing unit 11 that relatively pressurizes the semiconductor chip 2 and the wiring metal 3, and a heating unit 12 that heats the semiconductor chip 2 and the wiring metal 3. ing.

加圧手段11は、半導体チップ2の上面側に相対向する加圧体13や、加圧体13を昇降させる昇降駆動機構(図示せず)などで構成されている。他方、加熱手段12は、半導体装置1を載置する基盤に周知の加熱源を内蔵したものである。これにより、先の加圧手段11は、加熱手段12との間で半導体チップ2及び配線金属3を相対的に加圧することとなる。   The pressurizing unit 11 includes a pressurizing body 13 facing the upper surface side of the semiconductor chip 2, an elevating drive mechanism (not shown) that moves the pressurizing body 13 up and down, and the like. On the other hand, the heating means 12 has a well-known heating source built in a base on which the semiconductor device 1 is placed. As a result, the previous pressurizing unit 11 pressurizes the semiconductor chip 2 and the wiring metal 3 relatively with the heating unit 12.

そして、製造装置は、加圧手段11が、上記の加圧体13と、加圧体13の外周側に配置した押圧部14と、排出物抑制手段(15,16)を備えている。加圧体13は、半導体チップ1又は配線金属3の主面に接触するもので、図示例では半導体チップ1の主面である上面に接触してこれを加圧する。押圧部14は、半導体チップ2と配線金属3との接合界面から半導体チップ1の外側へ排出された共晶反応溶融物及び酸化皮膜から成る排出物(B)を所定の厚さに押圧するもので、図示例では加圧体13に一体化されている。この押圧部14は、加圧体13の下面(半導体チップ2への接触面)よりも下方に突出しており、加圧体13の下面との間に側部としての段差面14Aを有している。   In the manufacturing apparatus, the pressurizing unit 11 includes the above-described pressurizing body 13, a pressing portion 14 disposed on the outer peripheral side of the pressurizing body 13, and discharged matter suppressing means (15, 16). The pressing body 13 is in contact with the main surface of the semiconductor chip 1 or the wiring metal 3, and in contact with the upper surface which is the main surface of the semiconductor chip 1 in the illustrated example, pressurizes the pressing body 13. The pressing part 14 presses the discharge (B) made of the eutectic reaction melt and the oxide film discharged from the bonding interface between the semiconductor chip 2 and the wiring metal 3 to the outside of the semiconductor chip 1 to a predetermined thickness. Thus, in the illustrated example, the pressure body 13 is integrated. The pressing portion 14 projects downward from the lower surface of the pressurizing body 13 (contact surface to the semiconductor chip 2), and has a step surface 14 </ b> A as a side portion between the pressing portion 14 and the lower surface of the pressurizing body 13. Yes.

排出物抑制手段は、半導体チップ2の外周部とこれに相対向する押圧部14の側部(以下、「段差面14A」とする)との隙間(S)に排出物(B)が進入するのを抑制するものである。この実施形態の排出物抑制手段15は、加圧体13の内部を経て半導体チップ2の外周部と押圧部14の段差面14Aとの隙間(S)に連通するガス供給路15と、加圧体13の外部からガス供給路15に排出物加圧用のガスを供給するガス供給源16を備えている。なお、排出物加圧用のガスは、とくに限定されないが、半導体チップ2の各構成部材を酸化させないものが好ましく、例えば、窒素ガス等の不活性ガスである。 The discharged matter suppressing means allows the discharged matter (B) to enter the gap (S) between the outer peripheral portion of the semiconductor chip 2 and the side portion of the pressing portion 14 (hereinafter referred to as “step surface 14A”) opposite to the outer peripheral portion. It is what suppresses. The discharge suppression means 15 of this embodiment includes a gas supply path 15 that communicates with the gap (S) between the outer peripheral portion of the semiconductor chip 2 and the stepped surface 14A of the pressing portion 14 through the inside of the pressurizing body 13, and pressurization. A gas supply source 16 is provided to supply gas for pressurizing the exhaust gas from the outside of the body 13 to the gas supply path 15. The exhaust pressurizing gas is not particularly limited, but is preferably a gas that does not oxidize each component of the semiconductor chip 2 and is, for example, an inert gas such as nitrogen gas.

上記構成を備えた半導体装置1の製造装置は、半導体チップ2を配線金属3に接合するに際し、図2に示すように、半導体チップ2の接合面と、配線金属3の少なくとも接合面との間に、インサート材4を介在させる。   As shown in FIG. 2, the manufacturing apparatus of the semiconductor device 1 having the above-described configuration, when bonding the semiconductor chip 2 to the wiring metal 3, places the bonding surface between the semiconductor chip 2 and at least the bonding surface of the wiring metal 3. The insert material 4 is interposed.

次に、上記の製造装置は、加圧手段11の加圧体13を下降させて、図3に示すように、半導体チップ2及び配線金属3の加圧を開始し、その後、図5(1)に示すように一定の加圧力を所定時間保持する。また、製造装置は、加熱手段12により半導体チップ2及び配線金属3を加熱し、図5(2)に示すように、一定の温度を所定時間保持する。このとき、半導体装置1は、アルミニウム系金属から成る半導体チップ(下側電極2C)2及び配線金属3の表面に形成されている酸化皮膜が凹凸5により破壊されて、アルミニウム系金属とインサート材4とが接触し、半導体チップ2と配線金属3との接合界面に、Alとインサート材4に含まれる金属との共晶反応が生じることとなる。   Next, the manufacturing apparatus lowers the pressurizing body 13 of the pressurizing means 11 and starts pressurizing the semiconductor chip 2 and the wiring metal 3 as shown in FIG. As shown in (), a constant pressure is maintained for a predetermined time. Further, the manufacturing apparatus heats the semiconductor chip 2 and the wiring metal 3 by the heating means 12, and maintains a constant temperature for a predetermined time as shown in FIG. 5 (2). At this time, in the semiconductor device 1, the oxide film formed on the surfaces of the semiconductor chip (lower electrode 2 </ b> C) 2 and the wiring metal 3 made of an aluminum-based metal is broken by the unevenness 5, and the aluminum-based metal and the insert 4 And a eutectic reaction between Al and the metal contained in the insert material 4 occurs at the bonding interface between the semiconductor chip 2 and the wiring metal 3.

すなわち、上記の半導体装置1では、製造過程において、凹凸5の先端に応力が集中するため、比較的低い加圧力によって、チップへのダメージを与えることなく酸化皮膜を破壊することができる。そして、この破壊部分を介してアルミニウム系金属とインサート材4とが接触し、この接触部を起点として生じた共晶反応が接合面全体に拡大することによって、接合面の酸化皮膜が低温度(共晶温度)で除去されるので、アルミニウム系金属同士のダイレクトな接合が可能となる。   That is, in the semiconductor device 1 described above, stress concentrates on the tips of the irregularities 5 during the manufacturing process, so that the oxide film can be destroyed without damaging the chip with a relatively low applied pressure. Then, the aluminum-based metal and the insert material 4 come into contact with each other through the fracture portion, and the eutectic reaction generated from the contact portion expands to the entire joint surface, so that the oxide film on the joint surface has a low temperature ( Since it is removed at the eutectic temperature), it becomes possible to directly join aluminum-based metals.

また、上記の半導体装置1及び製造装置は、図4に示すように、共晶反応溶融物を酸化皮膜と共に排出物Bとして半導体チップ2の外側に排出し、接合界面の少なくとも一部において半導体チップ2と配線金属3のアルミニウム系金属同士を直接接合する。   Further, as shown in FIG. 4, the semiconductor device 1 and the manufacturing apparatus described above discharge the eutectic reaction melt together with the oxide film as the discharge B to the outside of the semiconductor chip 2 and at least part of the bonding interface. 2 and the aluminum metal of the wiring metal 3 are joined directly.

このとき、上記の製造装置では、加圧体13が下降限に達するのに伴って、半導体チップ2の外側に排出された排出物Bを押圧部14により所定の厚さに押圧すると共に、排出物抑制手段において、ガス供給源16からガス供給路15に排出物加圧用のガスを供給する。このガスは、図4(B)に示すように、ガス供給路15から半導体チップ2の外周部と押圧部14の段差面14Aとの間の隙間Sに供給され、この際、隙間Sの下端部が排出物Bにより塞がれているので、隙間S内に閉じ込められた状態になる。これにより、排出物抑制手段は、供給したガスの圧力を保持し、その圧力によって排出物Bの一部が上記隙間Sに進入するのを抑制する。その後、製造装置は、図5(3)に示すように、加圧手段11による加圧及び加熱手段12による加熱を終了し、ガスの供給も終了する。   At this time, in the manufacturing apparatus described above, as the pressurizing body 13 reaches the lower limit, the discharge B discharged to the outside of the semiconductor chip 2 is pressed to a predetermined thickness by the pressing portion 14 and discharged. In the object suppressing means, a gas for pressurizing the exhaust is supplied from the gas supply source 16 to the gas supply path 15. As shown in FIG. 4B, this gas is supplied from the gas supply path 15 to the gap S between the outer peripheral portion of the semiconductor chip 2 and the stepped surface 14A of the pressing portion 14, and at this time, the lower end of the gap S Since the portion is blocked by the discharge B, the state is confined in the gap S. Thereby, the emission control means maintains the pressure of the supplied gas, and suppresses a part of the emission B from entering the gap S by the pressure. Thereafter, as shown in FIG. 5 (3), the manufacturing apparatus finishes the pressurization by the pressurizing means 11 and the heating by the heating means 12, and the gas supply is also terminated.

上記のように製造された半導体装置1は、図6に示すように、半導体チップ2と配線金属3を備え、半導体チップ2及び配線金属3が、双方の接合界面の少なくとも一部において直接接合され、この直接接合部の周囲において、共晶反応溶融物及び酸化皮膜から成る排出物Bが所定の厚さに押圧された状態で存在している構造となる。   As shown in FIG. 6, the semiconductor device 1 manufactured as described above includes a semiconductor chip 2 and a wiring metal 3, and the semiconductor chip 2 and the wiring metal 3 are directly bonded at at least a part of both bonding interfaces. In the periphery of the direct joint, the discharge B composed of the eutectic reaction melt and the oxide film is present in a pressed state with a predetermined thickness.

本発明の半導体装置1の製造装置では、インサート材4を介して半導体チップ2及び配線金属3を相対的に加圧しながら加熱することで、凹凸5による酸化皮膜の破壊と、接合面及びインサート材4の間の共晶反応とを生じさせ、低温、低加圧で半導体チップ2と配線金属3とを強固に接合する。この際、上記の製造装置では、半導体チップ2や配線金属3の接合面には、アルミニウム系金属を採用し、インサート材4には、Zuを主成分とする金属を採用しているので、貴金属やPbを用いることなく、低コストで高温耐久性に優れた接合が可能になる。   In the manufacturing apparatus of the semiconductor device 1 according to the present invention, the semiconductor chip 2 and the wiring metal 3 are heated while being relatively pressed through the insert material 4, thereby destroying the oxide film due to the unevenness 5, the bonding surface, and the insert material. 4 is generated, and the semiconductor chip 2 and the wiring metal 3 are firmly bonded at low temperature and low pressure. At this time, in the manufacturing apparatus described above, an aluminum-based metal is used for the joining surface of the semiconductor chip 2 and the wiring metal 3, and a metal whose main component is Zu is used for the insert material 4. Without using Pb and Pb, it is possible to perform bonding with low temperature and excellent high-temperature durability.

また、上記の製造装置では、押圧部14により、排出物Bを所定の厚さに押圧すると共に、排出物抑制手段(15,16)により、半導体チップ2の外周部と押圧部14の段差面14Aとの隙間Sに排出物Bの一部が進入するのを抑制するので、半導体チップ2の外側の排出物Bが、バリなどの無い平坦なものになり、半導体チップ2の上下にある電極2B,2C間の沿面絶縁距離R(図6参照)が排出物Bによって短くなるのを防止する。   Moreover, in said manufacturing apparatus, while the discharge part B is pressed to predetermined thickness by the press part 14, the level | step difference surface of the outer peripheral part of the semiconductor chip 2 and the press part 14 by discharge | emission suppression means (15, 16). Since a part of the discharge B enters the gap S with respect to 14A, the discharge B on the outside of the semiconductor chip 2 becomes flat without burrs, and the electrodes above and below the semiconductor chip 2 The creeping insulation distance R (see FIG. 6) between 2B and 2C is prevented from being shortened by the discharge B.

このようにして、半導体装置1の製造装置によれば、貴金属やPbを用いることなく、低コストで高温耐久性に優れた接合を可能にすると共に、その接合の際に、接合部の酸化を阻止して充分な接合強度を確保しつつ、半導体チップ2の上下にある電極2B,2C間の沿面絶縁距離Rを適切に維持することができる。   In this way, according to the manufacturing apparatus of the semiconductor device 1, it is possible to perform bonding with low temperature and excellent high-temperature durability without using noble metal or Pb, and at the time of bonding, oxidation of the bonding portion is possible. The creeping insulation distance R between the electrodes 2B and 2C on the upper and lower sides of the semiconductor chip 2 can be appropriately maintained while preventing and securing sufficient bonding strength.

なお、上記の如くインサート材4を用いて半導体チップ2と配線金属3とを接合する場合、インサート材4の供給が少ないと、半導体チップ2と配線金属3との間に隙間が形成されて接合中の大気遮断が不充分になり、接合部が酸化されて接合強度が低下するおそれがある。他方、インサート材4の供給が多いと、半導体チップ2の外側において、排出物Bが、半導体チップ2の上面に近づくように厚くはみ出した状態になる。その結果、排出物Bを介して半導体チップ2の上下の電極2B,2C間の沿面絶縁距離Rが小さくなる。この沿面絶縁距離Rの減少は電極間の短絡を防止するうえで好ましくない。   When the semiconductor chip 2 and the wiring metal 3 are bonded using the insert material 4 as described above, a gap is formed between the semiconductor chip 2 and the wiring metal 3 if the supply of the insert material 4 is small. There is a risk that the air shielding inside becomes insufficient, the joint is oxidized, and the joint strength is lowered. On the other hand, when the supply of the insert material 4 is large, the discharged material B protrudes so as to approach the upper surface of the semiconductor chip 2 outside the semiconductor chip 2. As a result, the creeping insulation distance R between the upper and lower electrodes 2B and 2C of the semiconductor chip 2 is reduced via the discharge B. This decrease in the creeping insulation distance R is not preferable for preventing a short circuit between the electrodes.

これに対して、上記の製造装置を用いて製造された半導体装置1は、インサート材4の供給が充分であるから、半導体チップ2と配線金属3との接合中の大気遮断が充分になされ、接合部の酸化を阻止して充分な接合強度が確保される。また、押圧部14及び排出物抑制手段(15,16)により、半導体チップ2の外側の排出物Bを平坦にするので、半導体チップ2の上側電極2Bと排出物Bとの距離が短くなることも無く、上記沿面絶縁距離Rが適切に維持され、上下の電極2B,2C間の短絡を防ぐこととなる。   On the other hand, since the semiconductor device 1 manufactured using the above-described manufacturing apparatus is sufficiently supplied with the insert material 4, the air is sufficiently blocked during the bonding of the semiconductor chip 2 and the wiring metal 3, Sufficient joint strength is ensured by preventing the oxidation of the joint. Further, since the discharge B outside the semiconductor chip 2 is flattened by the pressing portion 14 and the discharge suppression means (15, 16), the distance between the upper electrode 2B of the semiconductor chip 2 and the discharge B is shortened. In addition, the creeping insulation distance R is appropriately maintained, and a short circuit between the upper and lower electrodes 2B and 2C is prevented.

以下、図7〜図9に基づいて、本発明の半導体装置の製造装置の第2〜第3の実施形態を説明する。なお、以下の各実施形態において、第1実施形態と同一の構成部位は、同一符号を付して詳細な説明を省略する。   The second to third embodiments of the semiconductor device manufacturing apparatus according to the present invention will be described below with reference to FIGS. In the following embodiments, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

〈第2実施形態〉
図7に示す半導体装置1の製造装置は、排出物抑制手段が、少なくとも押圧部14の側部(段差面14A)に形成され且つ排出物Bに対する濡れ性を低くした表面処理部14Bである。図示例の表面処理部14Bは、点線で示すように、押圧部14の段差面14Aから加圧体13の底面(半導体チップ2との接触面)に至る範囲に形成してある。この表面処理部14Bは、一例として粗面化処理により形成することができる。
Second Embodiment
In the manufacturing apparatus of the semiconductor device 1 shown in FIG. 7, the discharged matter suppressing means is a surface treatment portion 14 </ b> B that is formed at least on the side portion (step surface 14 </ b> A) of the pressing portion 14 and has low wettability with respect to the discharged matter B. The surface treatment portion 14B in the illustrated example is formed in a range from the stepped surface 14A of the pressing portion 14 to the bottom surface of the pressing body 13 (contact surface with the semiconductor chip 2) as indicated by a dotted line. This surface treatment part 14B can be formed by roughening as an example.

上記構成を備えた半導体装置1の製造装置は、加圧体13の下降により半導体チップ2及び配線金属3を加圧した際に、半導体チッ2プと配線金属3との接合界面から半導体チップ2の外側へ排出物Bが排出される。このとき、製造装置は、押圧部14により排出物Bを所定の厚さに押圧するが、押圧部14の側部に排出物Bの濡れ性が低い表面処理部14Bを有するので、排出物Bの一部が半導体チップ2と押圧部14との隙間Sに進入し難くなり、その結果、半導体チップ2の外側の排出物Bがバリ等の無い平坦な形状に形成される。   When the semiconductor chip 2 and the wiring metal 3 are pressurized by the lowering of the pressurizing body 13, the manufacturing apparatus of the semiconductor device 1 having the above-described configuration starts from the bonding interface between the semiconductor chip 2 and the wiring metal 3. Exhaust B is discharged outside. At this time, the manufacturing apparatus presses the discharge B to a predetermined thickness by the pressing portion 14, but has a surface treatment portion 14 B with low wettability of the discharge B on the side of the pressing portion 14. Is less likely to enter the gap S between the semiconductor chip 2 and the pressing portion 14, and as a result, the discharge B on the outside of the semiconductor chip 2 is formed in a flat shape free from burrs and the like.

これにより、半導体装置1は、半導体チップ2の上下の電極2B,2C間の沿面絶縁距離(図6の符号R)が適切に維持され、上下の電極2B,2C間の短絡を防止し得るものとなる。また、上記実施形態のように、表面処理部14Bを粗面化処理で形成すれば、比較的簡単な手段により、排出物Bに対する濡れ性が低い表面処理部14Bを低コストで得ることができるほか、粗面化によるピン止め効果により隙間Sへの排出物Bの進入をより一層抑制することができる。   As a result, the semiconductor device 1 can appropriately maintain the creeping insulation distance (symbol R in FIG. 6) between the upper and lower electrodes 2B and 2C of the semiconductor chip 2, and can prevent a short circuit between the upper and lower electrodes 2B and 2C. It becomes. Moreover, if the surface treatment part 14B is formed by the roughening treatment as in the above embodiment, the surface treatment part 14B having low wettability with respect to the discharged matter B can be obtained at a low cost by a relatively simple means. In addition, the entry of the discharge B into the gap S can be further suppressed by the pinning effect due to the roughening.

なお、上記のピン止め効果とは、排出物Bのように流動性を有するものが、接触角の大きな物質(粗面化した表面処理部14B)の表面にさしかかると、その表面上での接触角に到達するまで先に進めなくなる現象のことである。   The pinning effect described above is that when fluid such as the discharged matter B comes into contact with the surface of a substance having a large contact angle (roughened surface treatment portion 14B), contact on the surface is achieved. It is a phenomenon that does not proceed until it reaches the corner.

〈第3実施形態〉
図8に示す半導体装置1の製造装置は、排出物抑制手段が、押圧部14の側部に形成され且つ押圧部14の表面(底面)に対して90度未満の角度θ1を成す傾斜面14Cである。つまり、この実施形態の押圧部14は、加圧体13における段差面(14A)が傾斜面14Cになっている。
<Third Embodiment>
In the manufacturing apparatus of the semiconductor device 1 shown in FIG. 8, the emission suppressing means is formed on the side portion of the pressing portion 14 and has an inclined surface 14 </ b> C that forms an angle θ <b> 1 with respect to the surface (bottom surface) of the pressing portion 14. It is. That is, in the pressing portion 14 of this embodiment, the step surface (14A) in the pressurizing body 13 is an inclined surface 14C.

上記構成を備えた半導体装置1の製造装置は、加圧体13の下降により半導体チップ2及び配線金属3を加圧した際に、半導体チッ2プと配線金属3との接合界面から半導体チップ2の外側へ排出物Bが排出される。このとき、製造装置は、押圧部14により排出物Bを所定の厚さに押圧するが、押圧部14の側部に上記の傾斜面14Cを設けて、押圧部14の表面と傾斜面14Cとの角を鋭角にしているので、ピン止め効果により、排出物Bの一部が半導体チップ2と押圧部14との隙間Sに進入し難くなり、その結果、半導体チップ2の外側の排出物Bがバリ等の無い平坦な形状に形成される。   When the semiconductor chip 2 and the wiring metal 3 are pressurized by the lowering of the pressurizing body 13, the manufacturing apparatus of the semiconductor device 1 having the above-described configuration starts from the bonding interface between the semiconductor chip 2 and the wiring metal 3. Exhaust B is discharged outside. At this time, the manufacturing apparatus presses the discharge B to a predetermined thickness by the pressing portion 14, but the inclined surface 14C is provided on the side portion of the pressing portion 14, and the surface of the pressing portion 14 and the inclined surface 14C are provided. Because of the pin angle, due to the pinning effect, it becomes difficult for a part of the discharge B to enter the gap S between the semiconductor chip 2 and the pressing portion 14, and as a result, the discharge B outside the semiconductor chip 2. Is formed in a flat shape without burrs or the like.

なお、この実施形態におけるピン止め効果とは、排出物Bのように流動性を有するものが移動して屈曲のある表面(傾斜面14C)にさしかかると、それまで移動してきた表面(押圧部14の表面)における接触角よりも大きな接触角に到達するまで先に進めなくなる現象のことである。   In addition, the pinning effect in this embodiment is the surface (pressing part 14) which has moved so far when a fluid such as the discharge B moves and reaches a curved surface (inclined surface 14C). This is a phenomenon in which it cannot proceed further until a contact angle larger than the contact angle on the surface) is reached.

これにより、半導体装置1は、半導体チップ2の上下の電極2B,2C間の沿面絶縁距離(図6の符号R)が適切に維持され、上下の電極2B,2C間の短絡を防止し得るものとなる。また、上記実施形態のように、傾斜面14Cを採用すれば、比較的簡単な構造で排出物抑制手段を実現することができる。   As a result, the semiconductor device 1 can appropriately maintain the creeping insulation distance (symbol R in FIG. 6) between the upper and lower electrodes 2B and 2C of the semiconductor chip 2, and can prevent a short circuit between the upper and lower electrodes 2B and 2C. It becomes. Moreover, if the inclined surface 14C is employed as in the above embodiment, the emission control means can be realized with a relatively simple structure.

〈第4実施形態〉
図8に示す半導体装置1の製造装置は、排出物抑制手段が、押圧部14の外周側に形成された面取り状の傾斜面14Dである。つまり、この実施形態の押圧部14は、水平面に対して90度未満の角度θ2を有する傾斜面14Dにより、排出物Bの排出方向に対してその進路を拡大するような構造、又は排出物Bを逃がすような構造になっている。
<Fourth embodiment>
In the manufacturing apparatus of the semiconductor device 1 shown in FIG. 8, the emission suppressing means is a chamfered inclined surface 14 </ b> D formed on the outer peripheral side of the pressing portion 14. That is, the pressing portion 14 of this embodiment has a structure in which the course of the discharge B is expanded with respect to the discharge direction of the discharge B or the discharge B by the inclined surface 14D having an angle θ2 of less than 90 degrees with respect to the horizontal plane. It has a structure that lets you escape.

上記構成を備えた半導体装置1の製造装置は、加圧体13の下降により半導体チップ2及び配線金属3を加圧した際に、半導体チッ2プと配線金属3との接合界面から半導体チップ2の外側へ排出物Bが排出される。このとき、製造装置は、押圧部14により排出物Bを所定の厚さに押圧するが、押圧部14の外周側に面取り状の傾斜面14Dを有するので、排出物Bの流動抵抗が減少して、その流れが傾斜面14D側へ促進される。これにより、製造装置は、半導体チップ2と押圧部14との隙間Sに排出物B一部が進入し難くなる。その結果、排出物Bは、図8に示すように、傾斜面14Dの部分では厚くなるが、半導体チップ2に近い部分ではバリ等の無い薄肉形状に形成される。   When the semiconductor chip 2 and the wiring metal 3 are pressurized by the lowering of the pressurizing body 13, the manufacturing apparatus of the semiconductor device 1 having the above-described configuration starts from the bonding interface between the semiconductor chip 2 and the wiring metal 3. Exhaust B is discharged outside. At this time, the manufacturing apparatus presses the discharge B to a predetermined thickness by the pressing portion 14, but has a chamfered inclined surface 14D on the outer peripheral side of the pressing portion 14, so that the flow resistance of the discharge B decreases. Thus, the flow is promoted to the inclined surface 14D side. Thereby, in the manufacturing apparatus, it becomes difficult for a part of the discharge B to enter the gap S between the semiconductor chip 2 and the pressing portion 14. As a result, as shown in FIG. 8, the discharge B is thick at the inclined surface 14 </ b> D, but is formed in a thin shape without burrs at the portion close to the semiconductor chip 2.

このようにして、半導体装置1は、半導体チップ2の上下の電極2B,2C間の沿面絶縁距離(図6の符号R)が適切に維持され、上下の電極2B,2C間の短絡を防止し得るものとなる。また、上記実施形態のように、面取り状の傾斜面14Dを採用すれば、比較的簡単な構造で排出物抑制手段を実現することができる。なお、この実施形態の構造においては、例えば、上記傾斜面14Dに、排出物Bに対する濡れ性が高い表面処理を施すことも有効である。これにより、排出物Bの傾斜面14D側への流れをより一層促進させることができる。   In this manner, the semiconductor device 1 appropriately maintains the creeping insulation distance (the symbol R in FIG. 6) between the upper and lower electrodes 2B and 2C of the semiconductor chip 2, and prevents a short circuit between the upper and lower electrodes 2B and 2C. To get. Moreover, if the chamfered inclined surface 14D is employed as in the above embodiment, the emission control means can be realized with a relatively simple structure. In the structure of this embodiment, for example, it is also effective to subject the inclined surface 14D to a surface treatment with high wettability with respect to the discharge B. Thereby, the flow of the discharge B to the inclined surface 14D side can be further promoted.

本発明の半導体装置の製造装置は、その構成が上記各実施形態のみに限定されるものではなく、本発明の要旨を逸脱しない範囲で、各構成部位の材料、形状及び数などの細部を適宜変更することが可能である。   The semiconductor device manufacturing apparatus according to the present invention is not limited to the above embodiments, and the details of the material, shape, number, and the like of each component are appropriately selected without departing from the scope of the present invention. It is possible to change.

本発明の半導体装置の製造装置は、例えば、加圧手段11における押圧部14は、加圧体13と別体にすることも可能であるが、各実施形態で説明したように、加圧体13に押圧部14を一体化すれば、装置構造の簡略化や製造コストの低減などを実現することができる。また、製造装置は、上記第1〜第4の実施形態で説明した排出物抑制手段、すなわちガス供給路15及びガス供給源16、表面処理部14B、傾斜面14C,14Dを適宜選択して組み合わせることができる。   In the semiconductor device manufacturing apparatus of the present invention, for example, the pressing portion 14 in the pressing means 11 can be separated from the pressing body 13, but as described in each embodiment, the pressing body 14 If the pressing unit 14 is integrated with the unit 13, the structure of the apparatus can be simplified and the manufacturing cost can be reduced. Further, the manufacturing apparatus appropriately selects and combines the emission control means described in the first to fourth embodiments, that is, the gas supply path 15 and the gas supply source 16, the surface treatment unit 14B, and the inclined surfaces 14C and 14D. be able to.

1 半導体装置
2 半導体チップ
2B 上側電極
2C 下側電極
3 配線金属
4 インサート材
5 凹凸
11 加圧手段
12 加熱手段
13 加圧体
14 押圧部
14A 段差面
14B 表面処理部(排出物抑制手段)
14C 傾斜面(排出物抑制手段)
14D 傾斜面(排出物抑制手段)
15 ガス供給路(排出物抑制手段)
16 ガス供給源(排出物抑制手段)
B 排出物
R 沿面絶縁距離
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 2B Upper electrode 2C Lower electrode 3 Wiring metal 4 Insert material 5 Concavity and convexity 11 Pressure means
DESCRIPTION OF SYMBOLS 12 Heating means 13 Pressurization body 14 Press part 14A Step surface 14B Surface treatment part (exhaust matter suppression means)
14C inclined surface (exhaust control means)
14D inclined surface (exhaust control means)
15 Gas supply path (exhaust control means)
16 Gas supply source (exhaust control means)
B Emission R Creeping insulation distance

Claims (9)

半導体チップの接合面と、配線金属の少なくとも接合面との間に、各接合面の金属と共晶反応を生じる金属を含むインサート材を介在させると共に、接合面の酸化皮膜を破壊するための凹凸を接合面及びインサート材表面の少なくとも一部に設け、接合界面の少なくとも一部において半導体チップと配線金属とを直接接合して成る半導体装置を製造するための製造装置であって、
半導体チップ及び配線金属を相対的に加圧する加圧手段と、
半導体チップ及び配線金属を加熱する加熱手段とを備えると共に、
加圧手段が、
半導体チップ又は配線金属の主面に接触する加圧体と、
半導体チップと配線金属との接合界面から半導体チップの外側へ排出された共晶反応溶融物及び酸化皮膜から成る排出物を所定の厚さに押圧する押圧部と、
半導体チップの外周部とこれに相対向する押圧部の側部との隙間に排出物が進入するのを抑制する排出物抑制手段とを備えていることを特徴とする半導体装置の製造装置。
An unevenness for interposing an insert material containing a metal that causes a eutectic reaction with the metal of each bonding surface between the bonding surface of the semiconductor chip and at least the bonding surface of the wiring metal and destroying the oxide film on the bonding surface Is provided on at least a part of the bonding surface and the surface of the insert material, and a manufacturing apparatus for manufacturing a semiconductor device formed by directly bonding a semiconductor chip and a wiring metal at at least a part of the bonding interface,
Pressurizing means for relatively pressurizing the semiconductor chip and the wiring metal;
A heating means for heating the semiconductor chip and the wiring metal,
Pressurizing means
A pressure member that contacts the main surface of the semiconductor chip or wiring metal;
A pressing portion for pressing the eutectic reaction melt discharged from the bonding interface between the semiconductor chip and the wiring metal to the outside of the semiconductor chip and the discharge formed of the oxide film to a predetermined thickness;
An apparatus for manufacturing a semiconductor device, comprising: an emission suppressing means for suppressing the entry of an emission into a gap between an outer peripheral portion of a semiconductor chip and a side portion of a pressing portion opposed to the outer peripheral portion.
半導体チップが、接合面にアルミニウム系金属を備えると共に、配線金属が、少なくとも接合面にアルミニウム系金属を備え、インサート材が、Znを主成分とする金属であることを特徴とする請求項1に記載の半導体装置の製造装置。   The semiconductor chip includes an aluminum-based metal on a bonding surface, the wiring metal includes at least an aluminum-based metal on the bonding surface, and the insert material is a metal mainly composed of Zn. The manufacturing apparatus of the semiconductor device of description. 加圧手段において、加圧体に押圧部が一体化してあることを特徴とする請求項1又は2に記載の半導体装置の製造装置。   3. The semiconductor device manufacturing apparatus according to claim 1, wherein in the pressurizing means, a pressing portion is integrated with the pressurizing body. 排出物抑制手段が、加圧体を経て半導体チップの外周部と押圧部の側部との隙間に連通するガス供給路と、加圧体の外部からガス供給路に排出物加圧用のガスを供給するガス供給源を備えていることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置の製造装置。
The exhaust emission control means passes a gas supply passage communicating with the gap between the outer peripheral portion of the semiconductor chip and the side of the pressing portion through the pressurizer, and gas for pressurizing the exhaust from the outside of the pressurizer to the gas supply passage. The apparatus for manufacturing a semiconductor device according to claim 1, further comprising a gas supply source to supply.
排出物抑制手段が、少なくとも押圧部の側部に形成され且つ排出物に対する濡れ性を低くした表面処理部であることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置の製造装置。   5. The semiconductor device according to claim 1, wherein the emission control unit is a surface treatment unit that is formed at least on a side of the pressing unit and has low wettability with respect to the emission. manufacturing device. 表面処理部が、粗面化処理により形成されていることを特徴とする請求項5に記載の半導体装置の製造装置。   The semiconductor device manufacturing apparatus according to claim 5, wherein the surface treatment portion is formed by a roughening treatment. 排出物抑制手段が、押圧部の側部に形成され且つ押圧部の底面から上方に向かうにかけて前記隙間の幅が広がるように、前記押圧部の底面に対して90度未満の角度を成す傾斜面であることを特徴とする請求項1〜6のいずれか1項に記載の半導体装置の製造装置。
An inclined surface that forms an angle of less than 90 degrees with respect to the bottom surface of the pressing portion so that the discharge suppression means is formed on the side portion of the pressing portion and the width of the gap widens from the bottom surface of the pressing portion toward the upper side. The semiconductor device manufacturing apparatus according to claim 1, wherein the apparatus is a semiconductor device manufacturing apparatus.
排出物抑制手段が、押圧部の外周側に形成された面取り状の傾斜面であることを特徴とする請求項1〜7のいずれか1項に記載の半導体装置の製造装置。   The apparatus for manufacturing a semiconductor device according to claim 1, wherein the discharge suppression means is a chamfered inclined surface formed on an outer peripheral side of the pressing portion. 請求項1〜8のいずれか1項に記載の製造装置を用いて製造された半導体装置であって、半導体チップと配線金属を備え、半導体チップ及び配線金属が、双方の接合界面の少なくとも一部において直接接合され、この直接接合部の周囲において、共晶反応溶融物及び酸化皮膜から成る排出物が所定の厚さに押圧された状態で存在していることを特徴とする半導体装置。
A semiconductor device manufactured using the manufacturing apparatus according to claim 1 , wherein the semiconductor device includes a semiconductor chip and a wiring metal, and the semiconductor chip and the wiring metal are at least a part of a bonding interface between the two. The semiconductor device is characterized in that a discharge formed of a eutectic reaction melt and an oxide film is present in a state of being pressed to a predetermined thickness around the direct bonding portion.
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