JP6265870B2 - Digital protection relay device - Google Patents

Description

  The present invention relates to a digital protection relay device, and more particularly to a digital protection relay device having a function of inspecting and monitoring an analog / digital (A / D) converter.

  As a method for inspecting and monitoring the A / D conversion unit of the digital protection relay device, a method of applying an inspection signal to a plurality of input channels and comparing a signal that has passed through the A / D conversion unit with a reference value has been conventionally known. Yes.

  For example, Japanese Patent Laid-Open No. 60-55820 (Patent Document 1) discloses a method of applying bias voltages having different magnitudes as test signals to a plurality of input channels. The A / D converter is inspected and monitored based on the magnitude of the bias voltage.

  Japanese Patent Laid-Open No. 61-88715 (Patent Document 2) discloses an example in which a high-frequency signal is used as an inspection signal. By using the high-frequency inspection signal, the characteristic fluctuation in the high-frequency region of the analog filter constituting the A / D converter is detected.

Japanese Patent Laid-Open No. 60-55820 JP-A-61-88715

  By the way, the A / D converter is configured by a plurality of circuits such as an analog filter, a multiplexer, and an A / D converter. These circuits usually generate an offset voltage. The cause of the offset voltage is, for example, variations in the characteristics of the semiconductor elements included in each circuit and changes in element characteristics over time. Therefore, in the case of the inspection monitoring method described in Patent Document 1, it is difficult to distinguish the offset voltage from the inspection monitoring bias voltage, and therefore the soundness of the A / D converter cannot be accurately determined. There's a problem.

  In the case of the inspection and monitoring method described in Patent Document 2, since the high-frequency signal is used as the inspection signal, the above-described problem of distinction from the offset voltage does not occur. However, since Patent Document 2 mainly aims to detect a characteristic change of an analog filter, attention is not paid to a failure of another circuit in the A / D conversion unit. For example, there is no mention of multiplexer switching failure.

  The present invention has been made in consideration of the above-mentioned problems, and an object of the present invention is to provide an inspection and monitoring function that can more accurately determine the occurrence of a failure in each circuit component constituting the A / D conversion unit than before. Is to provide a digital protection relay device.

  The digital protection relay device according to the present invention includes an addition unit, an A / D conversion unit, a digital filter unit, and a soundness determination unit. The adder unit receives analog input signals of a plurality of channels each representing a voltage value or a current value of the power system, and inputs a plurality of inspection signals having different waveforms from each other and periodically changing the analog input signals of the plurality of channels. Add individually to the signal. The A / D converter performs A / D conversion of analog input signals of a plurality of channels to which a plurality of inspection signals are added. The digital filter unit removes a signal component corresponding to each inspection signal from the result of the A / D conversion described above for use in the relay calculation. The soundness determination unit determines the soundness of the A / D conversion unit for each channel based on the signal component corresponding to each inspection signal.

  According to the present invention, since the periodic signals having different waveforms are used as the inspection signals input to the respective channels, it is possible to detect, for example, a multiplexer switching failure. As a result, the occurrence of a failure in each component of the A / D converter can be determined more accurately than in the past.

It is a block diagram which shows the structure of the digital protection relay apparatus by 1st Embodiment. It is a block diagram which shows the structural example of the test | inspection signal production | generation part of FIG. It is a functional block diagram which shows the arithmetic processing content in the arithmetic processing part of FIG. It is a flowchart which shows operation | movement of the arithmetic processing part of FIG. It is a block diagram which shows the structure of the test | inspection signal production | generation part used by 2nd Embodiment. It is a block diagram which shows the structure of the test | inspection signal production | generation part used by 3rd Embodiment. It is a block diagram which shows the structure of the digital protection relay apparatus by 4th Embodiment.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<First Embodiment>
[Configuration of digital protection relay device]
FIG. 1 is a block diagram showing the configuration of the digital protection relay device according to the first embodiment. Referring to FIG. 1, digital protection relay device 15 is connected to a plurality of voltage transformers and / or a plurality of current transformers provided in the power system via input converter 10. The input converter 10 includes a plurality of auxiliary transformers 11_1, 11_2,. Each auxiliary transformer 11 converts the signal from each voltage transformer and each current transformer connected to the power system into a voltage level suitable for processing in the digital protection relay device 15. The digital protective relay device 15 receives analog input signals X1, X2,... Of a plurality of channels from the input converter 10.

  The digital protection relay device 15 includes an adder 20, an analog / digital (A / D: Analog to Digital) converter 16, an arithmetic processor 26, an inspection signal generator 27, and a timing signal generator 28. .

  Adder 20 includes a plurality of adders 21_1, 21_2,... That receive analog input signals X1, X2,... Of a plurality of channels that respectively represent voltage values or current values of the power system. These adders 21 individually add the inspection signals TS1, TS2,... To the analog input signals X1, X2,. The inspection signals TS1, TS2,... Are periodic signals having different waveforms, and are generated by the inspection signal generator 27.

  The A / D converter 16 performs A / D conversion on the analog input signals X1, X2,... Of a plurality of channels to which the plurality of inspection signals TS1, TS2,. More specifically, the A / D converter 16 includes a plurality of analog filters (AF) 22_1, 22_2,..., A plurality of sample hold circuits (S / F) 23_1, 23_2,. And a multiplexer (MUX) 24 and an A / D converter 25.

  The plurality of analog filters 22 are provided corresponding to the plurality of adders 21, respectively. Each analog filter 22 performs a filtering process on the signal output from the corresponding adder 21 (the analog input signal Xi added with the inspection signal TSi, where i = 1, 2,...). Specifically, each analog filter 22 functions as a low-pass filter that removes a high-frequency component of the output signal of the corresponding adder 21 in order to remove aliasing errors during A / D conversion.

  The plurality of sample hold circuits 23 are provided corresponding to the plurality of analog filters, respectively. Each sample and hold circuit 23 samples the voltage signal that has passed through the corresponding analog filter 22 at a predetermined sampling frequency, and holds the sampled voltage value until the next sampling. The sampling frequency is, for example, 96 × Fr (Fr is the fundamental frequency of the power system). Note that the sample hold circuit 23 is not necessarily provided.

  The multiplexer 24 sequentially selects the voltage values held in the plurality of sample and hold circuits 23. The A / D converter 25 converts the analog value selected by the multiplexer into a digital value.

  The arithmetic processing unit 26 is configured as a microcomputer including a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), and the like (not shown). The CPU operates according to programs stored in the ROM and an external storage device (not shown), and performs arithmetic processing on the digital data output from the A / D converter 25.

  The timing signal generator 28 generates a timing signal TMG. The multiplexer 24, the A / D converter 25, and the arithmetic processing unit 26 described above operate according to the timing signal TMG.

[Configuration of inspection signal generator]
FIG. 2 is a block diagram illustrating a configuration example of the inspection signal generation unit in FIG. 2, test signal generation unit 27 includes an oscillator 30 and frequency multiplication circuits 31_1, 31_2,... Corresponding to a plurality of channels, respectively. The oscillator 30 generates a sine wave signal having the fundamental frequency Fr of the power system. The frequency multiplication circuits 31_1, 31_2,... Have inspection frequencies having higher-order frequencies f1, f2,... Than the fundamental frequency obtained by multiplying the fundamental frequency by an integer by multiplying the frequency of the sine wave signal output from the oscillator 30. TS1, TS2,... Are generated respectively.

  The conversion cycle Fsp (ie, sampling frequency) of the A / D converter 25 in FIG. 1 needs to be at least twice the frequency at which the arithmetic processing unit 26 can perform arithmetic processing according to the sampling theorem. If the maximum frequency of the inspection signal TS is Fmax, it is necessary to satisfy Fsp> Fmax / 2. If the minimum frequency of the inspection signal is Fmin, it is necessary to make Fmin distinguishable from the fundamental frequency Fr of the power system by digital arithmetic processing in the arithmetic processing unit 26. Furthermore, it is necessary to set a value that avoids the frequency band of noise generated in the power system.

  In general, even harmonics of the fundamental frequency do not occur in the power system. For example, when the analog input signal has three channels, f1 = 4 × Fr, f2 = 8 × Fr, f3 = It can be 12 × Fr. In this case, assuming that the current digital value obtained by A / D conversion is V (t) and the digital value obtained 90 ° before the fundamental frequency is V (t−90 °), V (t) The component of the inspection signal can be easily removed by −V (t−90 °).

  Alternatively, the upper limit of the noise frequency generated in the power system may be about 15 times the fundamental frequency Fr in the case of a commercial system. Therefore, for example, when the analog input signal is four channels, the inspection signals TS1, TS2, TS3, and TS4 are generated as f1 = 20 × Fr, f2 = 21 × Fr, f3 = 22 × Fr, and f4 = 23 × Fr, respectively. be able to.

[Operation of arithmetic processing unit]
FIG. 3 is a functional block diagram showing the contents of arithmetic processing in the arithmetic processing unit of FIG. Each functional block in FIG. 3 is realized by a CPU constituting the arithmetic processing unit 26 in FIG.

  With reference to FIG. 3, the arithmetic processing unit 26 includes a demultiplexer (DMUX) 40, a first digital filter unit 41, a relay arithmetic unit 42, a second digital filter unit 43, and soundness determination. Part 44. The demultiplexer 40 distributes the digital signal output from the A / D converter 25 to the channels CH1, CH2,... Of the analog input signals X1, X2,.

  The digital filter unit 41 removes signal components corresponding to the inspection signals TS1, TS2,... From the result of A / D conversion for each channel for use in the relay calculation. When each inspection signal is a sine wave signal having a higher-order frequency than the fundamental frequency obtained by multiplying the fundamental frequency of the power system by an integer, the current A / D conversion result and the A / D at one or more past points in time The inspection signal component can be easily removed by linear combination with the conversion result (for example, by subtracting a constant multiple of the past value from a constant multiple of the current value). When the offset voltage (DC component) of each circuit constituting the A / D conversion unit 16 is added to the result of A / D conversion, the offset voltage is removed by digital arithmetic processing.

  The relay calculation unit performs various relay calculations using the digital signal after filtering by the digital filter unit 41 (that is, the A / D conversion result of the original analog input signals X1, X2,...).

  The digital filter unit 43 removes signal components corresponding to the analog input signals X1, X2,... From the result of A / D conversion for each input channel. For example, since the amount of electricity detected by the power system does not change abruptly when it is normal, the filter function can be realized by subtracting the digital values of the analog input signals X1, X2,. . When the offset voltage (DC component) of each circuit constituting the A / D conversion unit 16 is added to the result of A / D conversion, the offset voltage is removed by digital arithmetic processing.

  The soundness determination unit 44 determines the soundness of the A / D conversion unit for each channel based on signal components corresponding to the inspection signals TS1, TS2,... Obtained as a result of the filter processing by the digital filter unit 43. . For example, the soundness determination unit 44 confirms that the magnitude of the signal component corresponding to the inspection signals TS1, TS2,... Has not changed from the reference range.

  FIG. 4 is a flowchart showing the operation of the arithmetic processing unit in FIG. 1 and shows a program process for checking the soundness of the A / D conversion unit 16. Hereinafter, the description so far regarding the arithmetic processing unit 26 will be summarized with reference to FIGS. 3 and 4.

  First, in step S100, the digital input signal output from the A / D converter 25 is distributed by the demultiplexer 40 for each channel CHi (i = 1, 2,...). A digital input signal for each channel is input.

  Next, in step S110, the first digital filter unit 41 removes a signal component corresponding to the inspection signal TSi from the digital input signal for each channel CHi. As a result, the result of A / D conversion of the original analog input signal Xi is obtained. The output of the digital filter unit 41 is used for relay calculation in the relay calculation unit 42.

  Thereafter, in step S120, the second digital filter unit 43 removes the signal component corresponding to the analog input signal Xi from the digital input signal for each channel CHi. Thereby, an A / D conversion result of the inspection signal TSi is obtained.

  Next, in step S130, the soundness determination unit 44 determines whether or not the A / D conversion result of the inspection signal TSi obtained by the digital filter unit 43 is within the reference range. If the A / D conversion result of the inspection signal TSi is within the reference range (YES in step S130), the process proceeds to step S140. In step S140, the soundness determination unit 44 determines that the operation of the channel CHi (i = 1, 2,...) Of the A / D conversion unit 16 is normal, and the process ends.

  On the other hand, if the A / D conversion result of the inspection signal TSi is not within the reference range in step S130 (NO in step S130), the process proceeds to step S150. In step S150, the soundness determination unit 44 determines whether the value of each inspection signal TSi is fixed to the value of a specific channel. Since the inspection signal TSi has a different waveform for each channel, the switching failure of the multiplexer 24 can be determined by this determination. As a result, when the value of each inspection signal TSi is fixed to a specific channel, the process proceeds to step S160, and the soundness determination unit 44 determines that the multiplexer 24 has a switching failure.

  If it is determined in step S150 that the value of each inspection signal TSi is not fixed to a specific channel value, the process proceeds to step S170. In step S170, the soundness determination unit 44 determines that the channel in which the A / D conversion result of the inspection signal TSi is not within the reference range is defective, and the process ends. The series of processes described above are executed at predetermined intervals.

  In order to prevent erroneous detection as a failure of the A / D converter 16 when the amount of electricity suddenly changes due to a disturbance or a transient state after an accident, the failure state is determined for a predetermined time (for example, 10 seconds). It is desirable to determine the defect of the A / D conversion unit 16 when it is continued. Thereby, the reliability of the detection of the defective state of the A / D conversion unit 16 can be improved.

[Effect of the first embodiment]
As described above, in the digital protection relay device according to the first embodiment, by changing the waveform (especially frequency) of the inspection signal for each input channel, it is easy to identify a channel that has failed in the A / D converter 16 in a short time. Can be specified. Furthermore, it is possible to identify a switching failure of the multiplexer 24. Further, the A / D conversion unit 16 can be inspected while performing a relay calculation for protecting the power system.

  Furthermore, by making the waveform of the inspection signal a sine wave having an integer multiple of the fundamental frequency of the power system, the signal component corresponding to the inspection signal can be easily removed from the A / D conversion result.

<Second Embodiment>
FIG. 5 is a block diagram illustrating a configuration of an inspection signal generation unit used in the second embodiment. 5 includes an oscillator 30 and amplifiers 32_1, 32_2,... Corresponding to a plurality of input channels CH1, CH2, CH3,.

  The oscillator 30 generates a sine wave signal having a frequency F. This frequency F must satisfy the condition of Fmin described in FIG. For example, the frequency F generated by the oscillator 30 is set to 20 times the fundamental frequency Fr of the power system.

  The amplifiers 32_1, 32_2,... Generate test signals TS1, TS2,... Having different waveforms from each other by amplifying the sine wave signals generated by the oscillator 30 with mutually different gains A1, A2,. For example, when there are four input channels, the gain settings can be set to A1 = 0.5, A2 = 1.0, A3 = 1.5, and A4 = 2.0, respectively.

  Even when the inspection signal generation unit having the above-described configuration is used, the digital protection relay device can achieve the same effects as those of the first embodiment. In the above example, the amplitudes of the inspection signals TS1, TS2,... Are different from each other. However, in combination with the case of FIG. 2, both the amplitudes and frequencies of the inspection signals TS1, TS2,. You may make it let.

<Third Embodiment>
FIG. 6 is a block diagram illustrating a configuration of an inspection signal generation unit used in the third embodiment. 6 corresponds to a ROM (Read Only Memory) 33, a digital / analog (D / A) converter 34, and a plurality of input channels CH1, CH2, CH3,. Phase shifters (phase shifters) 35_1, 35_2, 35_3,.

  The D / A converter 34 generates a sine wave signal sin (ω · t) by performing digital / analog conversion of the waveform data stored in advance in the ROM 33. In this case, the frequency F of the sine wave signal (= ω / (2π), π is the circumference) must satisfy the condition of Fmin described in FIG. For example, the frequency F is set to 20 times the basic frequency Fr of the power system.

  The phase shifters 35_1, 35_2,... Shift the phases of the sine wave signals generated by the D / A converter 34 by different phases θ1, θ2,. As a result, inspection signals TS1, TS2,... Having different waveforms are generated. For example, when there are four input channels, the phase settings can be set to θ1 = 0 °, θ2 = 90 °, θ3 = 180 °, and θ4 = 270 °, respectively.

  Note that the timing of the D / A conversion operation by the D / A converter 34 is controlled by the timing signal TMG. Therefore, for example, the arithmetic processing unit 26 can calculate the phase shift amount based on the timing of the zero cross point of the sine wave signal, and can detect which channel is the inspection signal input.

  Even when the inspection signal generation unit having the above-described configuration is used, the digital protection relay device can achieve the same effects as those of the first embodiment. It is possible to combine the third embodiment with the first and second embodiments. That is, the inspection signals TS1, TS2,... May be different from each other in at least one of frequency, amplitude, and phase.

<Fourth Embodiment>
In the first to third embodiments, the case where the inspection signals TS1, TS2,... Are sine wave signals has been described, but the inspection signals are not limited to sine wave signals. For example, the inspection signal may be a periodic signal having a pulse waveform such as a rectangular wave, a triangular wave, or a sawtooth wave. In the fourth embodiment, a case where the waveform of the inspection signal is not limited to a sine wave signal will be described.

  FIG. 7 is a block diagram showing the configuration of the digital protection relay device according to the fourth embodiment. Referring to FIG. 7, in the digital protection relay device 15A of the fourth embodiment, the configuration of the test signal generation unit 27A and the arithmetic processing unit 26A is the test signal generation of the first embodiment shown in FIGS. Different from the configuration of the unit 27 and the arithmetic processing unit 26.

  Specifically, the arithmetic processing unit 26A includes a waveform data generation unit 51 in addition to the demultiplexer 40, the first digital filter unit 41, the relay calculation unit 42, the second digital filter unit 43, and the soundness determination unit 44. Is different from the arithmetic processing unit 26 of FIG. The waveform data generation unit 51 generates digital waveform data corresponding to the inspection signals TS1, TS2,. In FIG. 7, the second digital filter unit 43 and the soundness determination unit 44 are not shown.

  The inspection signal generation unit 27A includes D / A converters 50_1, 50_2,... For performing D / A conversion of digital waveform data output from the waveform data generation unit 51 for each input channel. The output signals of the D / A converters 50_1, 50_2,... Are used as inspection signals TS1, TS2,.

  The first digital filter unit 41 removes signal components corresponding to the inspection signals TS1, TS2,... From the result of A / D conversion for each channel for use in the relay calculation. However, when the inspection signal TS is not a sine wave signal, the signal component corresponding to the inspection signal TS is the same as the original inspection signal due to the influence of the analog filters 22_1, 22_2,... Provided in the A / D converter 16. It should be noted that the waveforms are not the same.

  Therefore, in the case of the fourth embodiment, the digital filter unit 41 includes an analog filter simulation unit (AF simulation unit) 52 and a subtraction unit 53 for each input channel (in FIG. 7, one corresponding to the channel CH1). Only shown). The AF simulation unit 52 simulates the transfer function of the analog filter of the corresponding channel using digital processing. The subtracting unit 53 subtracts the waveform data processed by the AF simulation unit 52 from the A / D conversion output of the corresponding channel. As a result, the signal component corresponding to each inspection signal TS can be removed from the A / D conversion output of the corresponding channel.

  In the case of the digital protection relay device according to the fourth embodiment, the A / D converter 16 becomes defective by changing the waveform of the inspection signal for each input channel, as in the case of the first embodiment. Channels can be easily identified in a short time. Furthermore, it is possible to identify a switching failure of the multiplexer 24. Further, the A / D conversion unit 16 can be inspected while performing a relay calculation for protecting the power system.

  Each embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 input converter, 11 auxiliary transformer, 15, 15A digital protection relay device, 16 A / D converter, 20 adder, 21 adder, 22 analog filter, 23 sample hold circuit, 24 multiplexer, 25 A / D conversion 26, 26A arithmetic processing unit, 27, 27A inspection signal generation unit, 28 timing signal generation unit, 30 oscillator, 31 frequency multiplication circuit, 32 amplifier, 33 ROM, 34, 50 D / A converter, 35 phase shifter , 40 Demultiplexer, 41 First digital filter unit, 42 Relay operation unit, 43 Second digital filter unit, 44 Soundness determination unit, 51 Waveform data generation unit, 52 AF simulation unit, 53 Subtraction unit, CH1, CH2 , ... Input channel, Fr fundamental frequency, TS1, TS2, ... Inspection signal, X1, X2, ... Analog input signal.

Claims (4)

Receives multiple channels of analog input signals, each representing the voltage or current value of the power system, and individually adds multiple inspection signals that have different waveforms and change periodically to the analog input signals of the multiple channels An adder to
An analog / digital conversion unit that performs analog / digital conversion of the analog input signals of the plurality of channels to which the plurality of inspection signals are respectively added;
A digital filter unit that removes signal components corresponding to each inspection signal from the result of the analog / digital conversion for use in a relay operation;
A sound determination unit for determining the soundness of the analog / digital conversion section for each of the channels based on a signal component corresponding to each of the test signal seen including,
The plurality of inspection signals are sinusoidal signals having different frequencies and having a frequency that is an integral multiple of the fundamental frequency of the power system, and having a higher order than the fundamental frequency,
The analog / digital converter is
A plurality of analog filters for respectively filtering the analog input signals of the plurality of channels to which the plurality of inspection signals are individually added;
A multiplexer for sequentially selecting the plurality of filtered signals;
An analog / digital converter that performs analog / digital conversion of the signal selected by the multiplexer,
The soundness determination unit is a digital protection relay device that determines soundness of each analog filter and presence / absence of switching failure of the multiplexer . Each said test signal has a frequency of an even multiple of the fundamental frequency of the power system, the digital protection relay device according to claim 1. The digital filter unit removes a signal component corresponding to each of the inspection signals by linearly combining the analog / digital conversion result at the present time and one or more past times for each channel. The digital protection relay device according to 1 or 2 . Receives multiple channels of analog input signals, each representing the voltage or current value of the power system, and individually adds multiple inspection signals that have different waveforms and change periodically to the analog input signals of the multiple channels An adder to
An analog / digital conversion unit that performs analog / digital conversion of the analog input signals of the plurality of channels to which the plurality of inspection signals are respectively added;
A digital filter unit that removes signal components corresponding to each inspection signal from the result of the analog / digital conversion for use in a relay operation;
A sound determination unit for determining the soundness of the analog / digital conversion section for each of the channels based on a signal component corresponding to each of the test signal seen including,
The analog / digital converter is
A plurality of analog filters for respectively filtering the analog input signals of the plurality of channels to which the plurality of inspection signals are individually added;
A multiplexer for sequentially selecting the plurality of filtered signals;
And a analog / digital converter for performing analog / digital conversion of the selected signal by pre-Symbol multiplexer,
The soundness determination unit determines the soundness of each channel of the analog filter and the multiplexer,
Each of the inspection signals is generated by performing digital / analog conversion of waveform data determined for each channel ,
The digital filter unit is
An analog filter simulation unit that simulates a transfer function of the analog filter by digital processing;
A subtractor that removes the signal component corresponding to each inspection signal by subtracting the waveform data processed by the analog filter simulation unit from the result of the analog / digital conversion for each channel . Digital protection relay device.

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