JP6257757B2 - カメラ制御インターフェース拡張バス - Google Patents

カメラ制御インターフェース拡張バス Download PDF

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Publication number
JP6257757B2
JP6257757B2 JP2016519659A JP2016519659A JP6257757B2 JP 6257757 B2 JP6257757 B2 JP 6257757B2 JP 2016519659 A JP2016519659 A JP 2016519659A JP 2016519659 A JP2016519659 A JP 2016519659A JP 6257757 B2 JP6257757 B2 JP 6257757B2
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Japan
Prior art keywords
serial bus
symbols
wire serial
bus
sequence
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2016519659A
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Japanese (ja)
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JP2016528589A (ja
JP2016528589A5 (cg-RX-API-DMAC7.html
Inventor
祥一郎 仙石
祥一郎 仙石
ジョージ・アラン・ウィリー
ジョセフ・チュン
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クアルコム,インコーポレイテッド
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Multimedia (AREA)
JP2016519659A 2013-06-12 2014-06-12 カメラ制御インターフェース拡張バス Expired - Fee Related JP6257757B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US201361834151P 2013-06-12 2013-06-12
US61/834,151 2013-06-12
US201361836777P 2013-06-19 2013-06-19
US61/836,777 2013-06-19
US201361886002P 2013-10-02 2013-10-02
US61/886,002 2013-10-02
US14/302,365 2014-06-11
US14/302,362 US9552325B2 (en) 2013-06-12 2014-06-11 Camera control interface extension bus
US14/302,365 US9582457B2 (en) 2013-06-12 2014-06-11 Camera control interface extension bus
US14/302,362 2014-06-11
PCT/US2014/042188 WO2014201293A1 (en) 2013-06-12 2014-06-12 Camera control interface extension bus

Publications (3)

Publication Number Publication Date
JP2016528589A JP2016528589A (ja) 2016-09-15
JP2016528589A5 JP2016528589A5 (cg-RX-API-DMAC7.html) 2017-06-29
JP6257757B2 true JP6257757B2 (ja) 2018-01-10

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
JP2016519659A Expired - Fee Related JP6257757B2 (ja) 2013-06-12 2014-06-12 カメラ制御インターフェース拡張バス
JP2016519656A Ceased JP2016528588A (ja) 2013-06-12 2014-06-12 カメラ制御インターフェース拡張バス

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2016519656A Ceased JP2016528588A (ja) 2013-06-12 2014-06-12 カメラ制御インターフェース拡張バス

Country Status (8)

Country Link
US (4) US9552325B2 (cg-RX-API-DMAC7.html)
EP (2) EP3008609B1 (cg-RX-API-DMAC7.html)
JP (2) JP6257757B2 (cg-RX-API-DMAC7.html)
KR (2) KR101790900B1 (cg-RX-API-DMAC7.html)
CN (2) CN105283862B (cg-RX-API-DMAC7.html)
CA (2) CA2911401A1 (cg-RX-API-DMAC7.html)
TW (1) TWI607318B (cg-RX-API-DMAC7.html)
WO (2) WO2014201293A1 (cg-RX-API-DMAC7.html)

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WO2022050599A1 (ko) * 2020-09-07 2022-03-10 삼성전자 주식회사 카메라의 신호 라인을 감소시킨 전자 장치
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Also Published As

Publication number Publication date
JP2016528589A (ja) 2016-09-15
KR20160018781A (ko) 2016-02-17
CN105283862B (zh) 2018-08-14
TW201506634A (zh) 2015-02-16
CA2911404A1 (en) 2014-12-18
EP3008609B1 (en) 2017-08-30
CN105283862A (zh) 2016-01-27
WO2014201293A1 (en) 2014-12-18
KR101790900B1 (ko) 2017-10-26
US20140372644A1 (en) 2014-12-18
US20170220518A1 (en) 2017-08-03
EP3008610B1 (en) 2017-08-30
EP3008610A1 (en) 2016-04-20
US20140372643A1 (en) 2014-12-18
CA2911401A1 (en) 2014-12-18
TWI607318B (zh) 2017-12-01
US9639499B2 (en) 2017-05-02
US9811499B2 (en) 2017-11-07
US9552325B2 (en) 2017-01-24
US20140372642A1 (en) 2014-12-18
CN105283863A (zh) 2016-01-27
US9582457B2 (en) 2017-02-28
KR20160019103A (ko) 2016-02-18
JP2016528588A (ja) 2016-09-15
WO2014201289A1 (en) 2014-12-18
EP3008609A1 (en) 2016-04-20

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