JP6253551B2 - Imaging device, imaging device, endoscope, and endoscope system - Google Patents

Description

  The present invention relates to an imaging device, an imaging device, an endoscope, and an endoscope system that capture an image of a subject and generate image data of the subject.

  Conventionally, in an image sensor such as a CCD (Charge Coupled Device) or CMOS (Complementary Metal Oxide Semiconductor), the signal voltage of the image sensor is amplified by a buffer circuit in which an impedance matching resistor is connected in series to the output terminal of the transistor. Is known (see Patent Document 1).

JP-A-6-141201

  However, in Patent Document 1 described above, there is a problem in that the output impedance of the transistor fluctuates because the resistance value of the impedance matching resistor varies for each manufacturing.

  The present invention has been made in view of the above, and an object thereof is to provide an imaging device, an imaging device, an endoscope, and an endoscope system that can stabilize the output impedance of a transistor.

  In order to solve the above-described problems and achieve the object, the imaging device according to the present invention is arranged in a two-dimensional matrix, receives light from the outside, and generates and outputs an imaging signal corresponding to the amount of received light. In an imaging device having a buffer chip for transferring the imaging signal output from each of a plurality of pixels to the outside, a first transistor having a gate to which the imaging signal is input, and one end side being an output end of the first transistor A first resistor connected; and a compensation unit connected in series with the other end of the first resistor and compensating for variations in the resistance value of the first resistor and outputting the imaging signal to the outside. It is characterized by that.

  In the imaging device according to the present invention, in the above invention, the compensation unit is connected to an input end in which the other end of the first resistor is connected in series and a transmission cable that propagates the imaging signal to the outside. A third transistor having a second transistor having an output terminal; an input terminal connected to a power supply voltage; and an output terminal connected to a gate of the second transistor; a ground; and an output of the third transistor And a third resistor and a fourth resistor connected in series between the power supply voltage and the ground, and the divided output voltage is supplied to the gate of the third transistor. And a voltage dividing circuit to be applied to the circuit.

  In the image pickup device according to the present invention as set forth in the invention described above, the first resistor and the second resistor are formed on the buffer chip.

  In the image pickup device according to the present invention as set forth in the invention described above, the first resistor and the second resistor are formed by the same semiconductor process.

  In the image pickup device according to the present invention as set forth in the invention described above, the first resistor and the second resistor compensate for a variation in impedance resistance composed of the channel resistance of the first resistor and the second transistor. And

  In addition, an imaging apparatus according to the present invention includes the above-described imaging element.

  In addition, an endoscope according to the present invention includes the above-described imaging device on the distal end side of the insertion portion.

  In addition, an endoscope system according to the present invention includes the endoscope described above and a processing device that converts the imaging signal into an image signal.

  According to the present invention, it is possible to compensate for variations in the resistance value of the impedance matching resistor.

FIG. 1 is a diagram schematically showing an overall configuration of an endoscope system according to an embodiment of the present invention. FIG. 2 is a block diagram showing functions of main parts of the endoscope system according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a detailed configuration of the second chip shown in FIG. 2 and a configuration of a main part of the connector unit. FIG. 4 is a plan view showing the arrangement of the first resistors shown in FIG. FIG. 5 is a plan view showing the arrangement of the second resistors shown in FIG. FIG. 6 is a plan view showing the arrangement of the second transistors shown in FIG. FIG. 7 is a plan view showing the arrangement of the third transistors shown in FIG.

  Hereinafter, as an embodiment for carrying out the present invention (hereinafter referred to as “embodiment”), an endoscope system including an image sensor will be described. Further, the present invention is not limited by this embodiment. Furthermore, the same code | symbol is attached | subjected to the same part in description of drawing. Furthermore, the drawings are schematic, and it should be noted that the relationship between the thickness and width of each member, the ratio of each member, and the like are different from the actual ones. Moreover, the part from which a mutual dimension and ratio differ also in between drawings.

[Configuration of endoscope system]
FIG. 1 is a diagram schematically showing an overall configuration of an endoscope system according to an embodiment of the present invention. An endoscope system 1 shown in FIG. 1 includes an endoscope 2 (imaging device), a transmission cable 3, a connector unit 5, a processor 6 (processing device), a display device 7, a light source device 8, and an input. Part 9.

  The endoscope 2 captures an in-vivo image of the subject by inserting the insertion unit 100 that is a part of the transmission cable 3 into the body cavity of the subject, and outputs an imaging signal (image data) to the processor 6. In addition, the endoscope 2 is provided on one end side of the transmission cable 3 and on the distal end 101 side of the insertion unit 100 that is inserted into the body cavity of the subject, an imaging unit 20 (imaging device) that captures in-vivo images. The operation unit 4 that receives various operations on the endoscope 2 is connected to the proximal end 102 side of the insertion unit 100. The imaging unit 20 is connected to the connector unit 5 via the operation unit 4 by the transmission cable 3. The imaging signal of the image captured by the imaging unit 20 is output to the connector unit 5 through the transmission cable 3 having a length of several meters, for example. In the present embodiment, the endoscope 2 functions as an imaging device.

  The transmission cable 3 connects the endoscope 2 and the connector unit 5, and connects the endoscope 2 and the light source device 8. In addition, the transmission cable 3 propagates the imaging signal generated by the imaging unit 20 to the connector unit 5.

  The connector unit 5 is connected to the endoscope 2, the processor 6, and the light source device 8, performs predetermined signal processing on the imaging signal output from the connected endoscope 2, and converts the imaging signal into an analog-digital conversion (A / D-converted) and output to the processor 6 as an image signal.

  The processor 6 performs predetermined image processing on the image signal output from the connector unit 5 and comprehensively controls the entire endoscope system 1. In the first embodiment, the processor 6 functions as a processing device.

  The display device 7 displays an image corresponding to the image signal subjected to image processing by the processor 6. The display device 7 displays various information related to the endoscope system 1. The display device 7 is configured using a display panel such as liquid crystal or organic EL (Electro Luminescence).

  The light source device 8 is configured using, for example, a halogen lamp, a white LED (Light Emitting Diode), or the like, and is directed from the distal end side of the insertion portion 100 of the endoscope 2 to the subject via the connector portion 5 and the transmission cable 3. Irradiate with illumination light.

  The input unit 9 is configured using, for example, a keyboard, a mouse, and the like, and receives input of information on various operations of the endoscope system 1. For example, the input unit 9 receives input of an instruction signal for instructing amplification (gain increase) of an imaging signal captured by the endoscope 2 and a light amount of the light source device 8.

  FIG. 2 is a block diagram illustrating functions of a main part of the endoscope system 1. With reference to FIG. 2, the detail of each part structure of the endoscope system 1 and the path | route of the electric signal in the endoscope system 1 are demonstrated. As illustrated in FIG. 2, the imaging unit 20 includes a first chip 21 (imaging element) and a second chip 22.

  The first chip 21 is arranged in a two-dimensional matrix, and has a light receiving unit 23 that has a plurality of pixels that generate and output an imaging signal corresponding to the amount of received light, and reads out the imaging signal photoelectrically converted by the light receiving unit 23 A timing generation unit 25 that generates a timing signal based on the reference clock signal and the synchronization signal input from the connector unit 5 and outputs the timing signal to the reading unit 24; and an imaging signal read out from the light receiving unit 23 by the reading unit 24 And a buffer 26 for temporarily holding.

  The second chip 22 includes a buffer 27 that transfers an imaging signal output from each of the plurality of pixels output from the first chip 21 to the outside. The buffer 27 is connected in series to the first transistor 28 to which the imaging signal from the first chip 21 is input to the gate, and one end side to the output terminal of the first transistor 28, and a first resistor for impedance matching with respect to the transmission cable 3. 29 and a compensator 30 connected in series to the other end of the first resistor 29 and compensating for variations in the resistance value of the first resistor 29 and outputting an imaging signal to the outside. A more detailed configuration of the second chip 22 will be described later with reference to FIG.

  Further, the imaging unit 20 receives the power supply voltage VDD generated by the power supply unit 61 in the processor 6 through the transmission cable 3 together with the ground (GND). A power supply stabilization capacitor C100 is provided between the power supply voltage VDD supplied to the imaging unit 20 and the ground (GND).

  The connector unit 5 functions as a relay processing unit that electrically connects the endoscope 2 (imaging unit 20) and the processor 6 and relays an electrical signal. The connector part 5 and the imaging part 20 are connected by the transmission cable 3, and the connector part 5 and the processor 6 are imaged by a coil cable. The connector unit 5 is also connected to the light source device 8. The connector unit 5 includes a termination resistor 51, an analog front end unit 52 (hereinafter referred to as “AFE unit 52”), an imaging signal processing unit 53, a drive signal generation unit 54, and a control unit 55. .

  The termination resistor 51 is provided at the termination of the transmission cable 3. A more detailed configuration of the termination resistor 51 will be described later with reference to FIG.

  The AFE unit 52 receives the imaging signal transmitted from the imaging unit 20, performs impedance matching with a passive element such as a resistor, extracts an AC component with a capacitor, and determines an operating point with a voltage dividing circuit. The AFE unit 52 performs A / D conversion on the analog imaging signal transmitted from the imaging unit 20 and outputs the analog imaging signal to the imaging signal processing unit 53 as a digital imaging signal.

  The imaging signal processing unit 53 performs predetermined signal processing such as vertical line removal and noise removal on the digital imaging signal input from the AFE unit 52 and outputs the result to the processor 6. The imaging signal processing unit 53 is configured using, for example, an FPGA (Field Programmable Gate Array).

  The drive signal generation unit 54 is supplied from the processor 6 and is a synchronization that represents the start position of each frame based on a reference clock signal (for example, a 27 MHz clock signal) that serves as a reference for the operation of each component of the endoscope 2. A signal is generated and output to the timing generation unit 25 of the imaging unit 20 via the transmission cable 3 together with the reference clock signal. Here, the synchronization signal generated by the drive signal generation unit 54 includes a horizontal synchronization signal and a vertical synchronization signal.

  The processor 6 is a control device that comprehensively controls the entire endoscope system 1. The processor 6 includes a power supply unit 61, an image signal processing unit 62, and a clock generation unit 63.

  The power supply unit 61 generates a power supply voltage VDD, and supplies the generated power supply voltage VDD together with the ground (GND) to the imaging unit 20 via the connector unit 5 and the transmission cable 3.

  The image signal processing unit 62 performs a synchronization process, a white balance (WB) adjustment process, a gain adjustment process, a gamma correction process, a digital analog (for a digital image signal that has been subjected to signal processing by the image signal processing unit 53. D / A) Image processing such as conversion processing and format conversion processing is performed to convert it into an image signal, and this image signal is output to the display device 7.

  The clock generation unit 63 generates a reference clock serving as a reference for the operation of each component of the endoscope system 1, and outputs this reference clock signal to the AFE unit 52, the imaging signal processing unit 53, and the drive signal generation unit 54. .

[Configuration of second chip and termination resistor]
Next, the detailed configuration of the second chip 22 and the detailed configuration of the main part of the connector unit 5 will be described. FIG. 3 is a circuit diagram showing the detailed configuration of the second chip 22 shown in FIG. 2 and the configuration of the main part of the connector unit 5.

  As shown in FIG. 3, the second chip 22 includes a buffer 27. The buffer 27 includes a first transistor 28, a first resistor 29, and a compensation unit 30.

  The first transistor 28 is configured using NMOS, and has an input terminal to which the power supply voltage VDD is connected, an output terminal to which one end side of the first resistor 29 is connected in series, and an imaging signal (from the first chip). And a gate to which a signal line for supplying Vin) is connected. Specifically, the power supply voltage VDD is connected to the input terminal (drain side) of the first transistor 28, one end side of the first resistor 29 is connected in series to the output terminal (source side), and the first chip is connected to the gate. A signal line for supplying an imaging signal (Vin) input from 21 is connected.

  One end of the first resistor 29 is connected in series to the output end (source side) of the first transistor 28, and the other end is connected in series to the input end (drain side) of the second transistor 303 of the compensation unit 30 described later. The Specifically, the first resistor 29 is connected in series between the output end (source side) of the first transistor 28 and the input end (drain side) of the second transistor 303. As shown in FIG. 4, the first resistor 29 has an output terminal (source side) of the first transistor 28 and an input terminal (drain) of the second transistor 303 in a state where a plurality of resistors 291 are connected in parallel. Connected in series.

  The compensation unit 30 is connected in series with the other end side of the first resistor 29, compensates for variations in the resistance value of the first resistor 29, and outputs the compensated value to the transmission cable 3. The compensation unit 30 includes a second resistor 301, a voltage dividing circuit 302, a second transistor 303, and a third transistor 304.

  The second resistor 301 has one end connected between the gate of the second transistor 303 and the output terminal of the third transistor 304, and the other end connected to the ground. Specifically, as shown in FIG. 5, the second resistor 301 includes a resistor 301 a having one end connected between the gate of the second transistor 303 and the output end of the third transistor 304 and the other end connected to the ground. Connected. The second resistor 301 and the first resistor 29 are formed by at least the same semiconductor process and the same size. Here, the same semiconductor process is formed by the same process, for example, element isolation formation, resistance element formation, wiring formation, and manufacturing timing. For example, the second resistor 301 and the first resistor 29 are formed by the same semiconductor process, and thus have the same resistance characteristics. The second resistor 301 and the first resistor 29 are formed on the same buffer 27 (on the buffer chip). In addition, the number of each resistor of the 1st resistance 29 and the 2nd resistance 301 can be changed suitably.

  The voltage dividing circuit 302 has a third resistor 302a and a fourth resistor 302b connected in series between the power supply voltage VDD and the ground, and applies the divided output voltage Vbias2 to the gate of the third transistor 304. . Specifically, in the voltage dividing circuit 302, a signal line (connection portion) that propagates the divided output voltage Vbias2 is connected to the gate of the third transistor 304. The third resistor 302 a and the fourth resistor 302 b may be formed by the same semiconductor process and the same size as the second resistor 301 and the first resistor 29.

  The second transistor 303 is configured by using a plurality of NMOSs, and has an input end connected in series to the other end of the first resistor 29, an output end connected to the transmission cable 3 that propagates an imaging signal to the outside, Have Specifically, the second transistor 303 has an input end (drain side) connected to the other end of the first resistor 29 in series, and an output end (source side) having a transmission cable 3 that propagates the imaging signal Vout to the outside. A signal line that propagates the output voltage Vbias1 input from the third transistor 304 is connected to the gate. Specifically, as shown in FIG. 6, the second transistor 303 is configured by using a plurality of NMOS 303a, and a signal line that propagates the voltage Vd input through the first resistor 29 is connected to the input terminal 303b. Then, the transmission cable 3 that propagates the imaging signal Vout to the outside is connected to the output terminal 303c, and the signal line that propagates the output voltage Vbias1 input from the third transistor 304 is connected to the gate 303d. Further, the channel resistance of the second transistor 303 is changed by the change of the gate potential.

  The third transistor 304 is configured using an NMOS transistor, the power supply voltage VDD is connected to the input end (drain side), the gate of the second transistor 303 is connected to the output side, and the gate potential of the second transistor 303 is controlled. To do. As shown in FIG. 7, the third transistor 304 is configured by using one NMOS transistor 304a, the input terminal 304b is connected to the power supply voltage VDD, the output terminal 304c is the gate of the second transistor 303, and the second transistor 304c. A signal line that propagates the output voltage Vbias2 divided from the voltage dividing circuit 302 is connected to the resistor 301 and to the gate 304d. The third transistor 304 and the second transistor 303 are formed by the same semiconductor process.

  The connector unit 5 includes at least an AC termination resistor 501, a DC termination resistor 502, and a DC cut capacitor 503.

  In the second chip 22 configured in this way, when the resistance value of the first resistor 29 is smaller than normal, the resistance value of the second resistor 301 is also small, and thus the output voltage Vbias1 input to the gate of the second transistor 303. Decreases, and the channel resistance of the second transistor 303 increases. As a result, the matching resistor formed by the first resistor 29 and the second transistor 303 cancels each other, so that the variation of the first resistor 29 can be compensated.

  On the other hand, when the resistance value of the first resistor 29 is larger than normal, the resistance value of the second resistor 301 also increases, so that the output voltage Vbias1 input to the gate of the second transistor 303 also increases, and the second transistor The channel resistance of 303 is reduced. As a result, the matching resistor formed by the first resistor 29 and the second transistor 303 cancels each other, so that the variation of the first resistor 29 can be compensated.

  According to the embodiment described above, the compensation unit 30 compensates for variations in the first resistor 29 based on the resistance value of the first resistor 29, so that the output impedance of the first transistor 28 is stabilized. Can do.

  In addition, according to the present embodiment, the second resistor 301, the voltage dividing circuit 302, the second transistor 303, and the third transistor 304 are provided, and the channel of the second transistor 303 is determined based on the resistance value of the first resistor 29. By changing the resistance, the impedance matching resistance composed of the first resistance 29 and the second transistor 303 cancel each other, so that the variation in individual differences of the first resistance 29 in the semiconductor formation process (resistance element formation process) can be reduced. Can be compensated.

  Further, according to the present embodiment, since the first resistor 29 and the second resistor 301 are formed on the same buffer 27, it is not necessary to provide separate discrete resistor chips in the imaging unit 20. The unit 20 (imaging device) can be downsized.

  Further, according to the present embodiment, the first resistor 29 and the second resistor 301 are formed by the same semiconductor process (resistive element forming process), and thus have the same resistance characteristics. Variations in the resistance 29 can be compensated.

  Further, according to the present embodiment, the first resistor 29 and the second resistor 301 compensate for the fluctuation of the impedance resistance composed of the channel resistance of the first resistor 29 and the second transistor 303, so that the output impedance is stabilized. can do.

  In addition, according to the present embodiment, even when the resistance value of the first resistor 29 varies as the temperature of the imaging unit 20 rises, the second resistor 301 has the same resistance as the first resistor 29. Since the channel resistance of the second transistor 303 is changed by changing the value, the output impedance of the transistor can be stabilized.

(Other embodiments)
In the present embodiment described above, each transistor is configured by NMOS, but may be configured by using, for example, PMOS.

  As described above, the present invention can include various embodiments not described herein, and various design changes and the like can be made within the scope of the technical idea specified by the claims. Is possible.

DESCRIPTION OF SYMBOLS 1 Endoscope system 2 Endoscope 3 Transmission cable 4 Operation part 5 Connector part 6 Processor 7 Display apparatus 8 Light source device 9 Input part 20 Imaging part 21 1st chip 22 2nd chip 23 Light-receiving part 24 Reading part 25 Timing generation part 26, 27 Buffer 28 First transistor 29 First resistor 30 Compensator 51 Termination resistor 52 AFE unit 53 Imaging signal processor 54 Drive signal generator 61 Power supply unit 62 Image signal processor 63 Clock generator 301 Second resistor 302 Voltage division Circuit 302a Third resistor 302b Fourth resistor 303 Second transistor 304 Third transistor 501 AC termination resistor 502 DC termination resistor 503 DC cut capacitor

Claims (7)

Arranged in a two-dimensional matrix, receives the light from the outside, generates an imaging signal according to the amount of received light, and outputs it, temporarily holding the imaging signal output from each of the plurality of pixels and transferring it to the outside In an imaging device having a buffer chip to
A first transistor having a gate to which the imaging signal is input;
A first resistor having one end connected to the output end of the first transistor;
A compensation unit connected in series with the other end side of the first resistor, compensating for a variation in the resistance value of the first resistor, and outputting the imaging signal to the outside;
An image pickup device comprising: The compensation unit
A second transistor having an input end connected in series to the other end of the first resistor, and an output connected to a transmission cable for propagating the imaging signal to the outside;
A third transistor having an input terminal to which a power supply voltage is connected and an output terminal to which the gate of the second transistor is connected;
A second resistor connected between the ground and the output terminal of the third transistor;
A voltage dividing circuit having a third resistor and a fourth resistor connected in series between a power supply voltage and the ground, and applying the divided output voltage to the gate of the third transistor;
The image pickup device according to claim 1, comprising:   The imaging device according to claim 2, wherein the first resistor and the second resistor are formed on the buffer chip.   The image sensor according to claim 2, wherein the first resistor and the second resistor are formed by the same semiconductor process.   An imaging device comprising the imaging device according to claim 1.   An endoscope comprising the imaging device according to claim 5 on a distal end side of an insertion portion. An endoscope according to claim 6;
A processing device for converting the imaging signal into an image signal;
An endoscope system comprising:

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