JP2017123971A - Endoscope - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an endoscope capable of accurately correcting lateral streak noise even when noise different in a dummy pixel and in an effective pixel occurs.SOLUTION: An endoscope 2 includes: a first signal processing part 52 that can generate a first signal by subjecting a dummy signal transmitted from a transmission cable 3 to first signal processing and output the first signal to the outside, and outputs an imaging signal to the outside as it is; and an FPGA 57 that causes the first signal processing part 52 to execute the first signal processing and output the first signal to the outside during a dummy signal output period in which an imaging part 20 outputs the dummy signal from a dummy pixel 247 based on a drive signal generated by a pulse generation part 55, and causes the first signal processing part 52 to output the imaging signal to the outside as it is during an imaging signal output period in which the imaging part 20 outputs the imaging signal from a unit pixel 230.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an endoscope that is introduced into a subject and generates image data of the subject.

  In recent years, CMOS (Complementary Metal Oxide Semiconductor) imaging devices are known in which dummy pixels that are not connected to photoelectric conversion elements are provided in each line row, and lateral stripe noise in each row due to fluctuations in power supply voltage is corrected (Patent Literature). 1). In this technique, the horizontal stripe noise generated in the image data is corrected by subtracting the pixel value output from the dummy pixel from the pixel value output from the effective pixel.

JP 2013-106225 A

  Incidentally, in Patent Document 1 described above, different noises may be generated between the dummy pixel and the effective pixel due to fluctuations in the power supply voltage. In such a case, there is a problem that the horizontal stripe noise cannot be accurately corrected and the image quality is deteriorated.

  The present invention has been made in view of the above, and provides an endoscope capable of accurately correcting lateral stripe noise even when different noises are generated between a dummy pixel and an effective pixel. For the purpose.

  In order to solve the above-described problems and achieve the object, the endoscope according to the present invention is arranged in a two-dimensional matrix, receives light from the outside, and generates and outputs an imaging signal corresponding to the amount of received light. Imaging having a plurality of effective pixels, and one or a plurality of dummy pixels provided for each horizontal line in the arrangement of the plurality of effective pixels and generating and outputting a dummy signal used for correction processing of the imaging signal An element, a transmission cable connected to the imaging element and transmitting the imaging signal and the dummy signal, and provided on a proximal end side of the transmission cable, and can be output to the outside while receiving the imaging signal. In addition, a first signal processing unit that performs a first signal processing on the dummy signal to generate a first signal and outputs the first signal to the outside, and a drive signal for driving the image sensor Based on the drive signal generated by the generation unit and the generation unit, the first signal processing unit is caused to execute the first signal processing in a dummy signal output period in which the dummy pixel outputs the dummy signal. A control unit that causes the first signal processing unit to output the imaging signal to the outside as it is during an imaging signal output period in which the effective pixel outputs the imaging signal while outputting the first signal to the outside. It is characterized by that.

  Moreover, the endoscope according to the present invention is the termination resistor provided on the proximal end side of the transmission cable and on the proximal end side on the distal end side of the transmission cable from the first signal processing unit. And a signal processing unit that is provided on the proximal end side of the transmission cable and downstream from the first signal processing unit and performs signal processing for correcting the imaging signal using the first signal. The first signal processing unit is provided between the termination resistor and the second signal processing unit, and the imaging signal and the first signal are transmitted to the second signal processing unit. It outputs to a signal processing part.

  The endoscope according to the present invention is the endoscope according to the above invention, wherein the first signal processing unit generates the first signal by performing the first signal processing on the dummy signal. A signal processing unit, and a switching unit that selectively switches one of the transmission cable and the third signal processing unit to connect to the second signal processing unit, and the control unit includes The third signal processing unit and the second signal processing unit are connected to the switching unit in the dummy signal output period, while the transmission cable and the second signal processing are connected to the switching unit in the imaging signal output period. It connects with a part, It is characterized by the above-mentioned.

  The endoscope according to the present invention is the endoscope according to the above invention, wherein the first signal processing unit generates the first signal by performing the first signal processing on the dummy signal. A signal processing unit, and a switching unit that selectively switches one of the second signal processing unit and the third signal processing unit to connect to the transmission cable, and the control unit In the dummy signal output period, the switching unit is connected to the third signal processing unit and the transmission cable, while in the imaging signal output period, the switching unit is connected to the second signal processing unit and the transmission cable. It is characterized by making it.

  The endoscope according to the present invention is characterized in that, in the above invention, the first signal processing section includes either a high-pass filter or a band-pass filter.

  Further, in the endoscope according to the present invention, in the above invention, the control unit performs the first signal processing performed by the first signal processing unit based on the drive signal generated by the generation unit. The content is changed.

  According to the present invention, there is an effect that the horizontal stripe noise can be accurately corrected even when different noises are generated between the dummy pixel and the effective pixel.

FIG. 1 is a schematic diagram schematically showing an overall configuration of an endoscope system according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing functions of main parts of the endoscope system according to Embodiment 1 of the present invention. FIG. 3 is a block diagram showing a detailed configuration of the first chip shown in FIG. FIG. 4 is a circuit diagram showing a configuration of the first chip. FIG. 5A is a circuit diagram showing a configuration of a reference voltage generation unit of the light receiving unit of the endoscope according to Embodiment 1 of the present invention. FIG. 5B is a circuit diagram showing a configuration of a reference voltage generation unit of the light receiving unit of the endoscope according to Embodiment 1 of the present invention. FIG. 6 is a flowchart showing an outline of processing executed by the endoscope system according to Embodiment 1 of the present invention. FIG. 7 is a block diagram showing functions of main parts of the endoscope system according to Embodiment 2 of the present invention.

  Hereinafter, as an embodiment for carrying out the present invention (hereinafter referred to as “embodiment”), an endoscope system including an endoscope inserted into a subject will be described. Further, the present invention is not limited by this embodiment. Further, in the description of the drawings, the same portions will be described with the same reference numerals. Furthermore, the drawings are schematic, and it should be noted that the relationship between the thickness and width of each member, the ratio of each member, and the like are different from the actual ones. Moreover, the part from which a mutual dimension and ratio differ between drawings is contained.

[Configuration of endoscope system]
FIG. 1 is a schematic diagram schematically showing an overall configuration of an endoscope system according to Embodiment 1 of the present invention. An endoscope system 1 shown in FIG. 1 includes an endoscope 2 (endoscope scope), a transmission cable 3, a connector unit 5, a processor 6 (processing device), a display device 7, and a light source device 8. .

  The endoscope 2 images the inside of the subject by inserting the insertion portion 100 that is a part of the transmission cable 3 into the body cavity of the subject, and outputs an imaging signal (image data) to the processor 6. In addition, the endoscope 2 is provided at one end side of the transmission cable 3 and on the distal end 101 side of the insertion unit 100 inserted into the body cavity of the subject, an imaging unit 20 (imaging device) that captures an in-vivo image. It has been. Furthermore, the endoscope 2 is provided with an operation unit 4 on the proximal end 102 side of the insertion unit 100 for receiving various operations on the endoscope 2. An image pickup signal of an image picked up by the image pickup unit 20 is output to the connector unit 5 via the transmission cable 3 having a length of, for example, several meters.

  The transmission cable 3 connects the endoscope 2 and the connector unit 5, and connects the endoscope 2, the processor 6, and the light source device 8. Further, the transmission cable 3 transmits the imaging signal generated by the imaging unit 20 to the connector unit 5. The transmission cable 3 is configured using a cable, an optical fiber, or the like.

  The connector unit 5 is connected to the endoscope 2, the processor 6, and the light source device 8, performs predetermined signal processing on the imaging signal output from the connected endoscope 2, and converts the analog imaging signal into a digital imaging signal. (A / D conversion) and output to the processor 6.

  The processor 6 performs predetermined image processing on the imaging signal input from the connector unit 5 and outputs the processed image signal to the display device 7. The processor 6 connects the entire endoscope system 1 in an integrated manner. For example, the processor 6 performs control to switch the illumination light emitted from the light source device 8 or switch the imaging mode of the endoscope 2.

  The display device 7 displays an image corresponding to the imaging signal that has been subjected to image processing by the processor 6. The display device 7 displays various information related to the endoscope system 1. The display device 7 is configured using a display panel such as liquid crystal or organic EL (Electro Luminescence).

  The light source device 8 irradiates illumination light from the distal end 101 side of the insertion portion 100 of the endoscope 2 toward the subject (subject) via the connector portion 5 and the transmission cable 3. The light source device 8 is configured using a white LED (Light Emitting Diode) that emits white light. The light source device 8 irradiates the subject with illumination light through the endoscope 2 under the control of the processor 6. In the first embodiment, a simultaneous illumination method is employed for the light source device 8, but a frame sequential illumination method may be used.

FIG. 2 is a block diagram illustrating functions of a main part of the endoscope system 1.
First, the configuration of the endoscope 2 will be described.
The endoscope 2 includes an imaging unit 20, a transmission cable 3, and a connector unit 5. The imaging unit 20 includes a first chip 21 (imaging device) and a second chip 22.

  The first chip 21 is input from the connector unit 5, the light receiving unit 23 having a plurality of unit pixels 230 and a plurality of dummy pixels 247, a reading unit 24 that reads out an imaging signal and a dummy signal photoelectrically converted by the light receiving unit 23. And a timing generator 25 that generates a timing signal based on the reference clock signal and the synchronization signal.

  The plurality of unit pixels 230 are arranged in a two-dimensional matrix in the matrix direction, receive light from the outside, and generate and output an imaging signal corresponding to the amount of received light.

  The plurality of dummy pixels 247 are provided for each horizontal line in the arrangement of the plurality of unit pixels 230, and generate and output dummy signals used for the correction processing of the imaging signal. A more detailed configuration of the first chip 21 will be described later with reference to FIG.

  The second chip 22 includes a buffer 27 that transmits an imaging signal output from the first chip 21 to the processor 6 via the transmission cable 3 and the connector unit 5. The combination of circuits mounted on the first chip 21 and the second chip 22 can be changed as appropriate.

  Further, the imaging unit 20 receives the power supply voltage VDD generated in the power supply unit 61 of the processor 6 through the transmission cable 3 together with the ground GND. A power supply stabilizing capacitor C1 is provided between the power supply voltage VDD supplied to the imaging unit 20 and the ground GND.

  The connector unit 5 includes a termination resistor 51, a first signal processing unit 52, an analog front end unit 53 (hereinafter referred to as “AFE unit 53”), an A / D conversion unit 54, and a pulse generation unit 55. And a power supply voltage generation unit 56 and an FPGA 57 (Field Programmable Gate Array).

  The termination resistor 51 is provided at the termination of the transmission cable 3. The termination resistor 51 has an AC termination resistor 511 having one end connected to the transmission cable 3 and the other end connected to the ground GND, and a DC termination resistor having one end connected to the transmission cable 3 and the other end connected to the ground GND. 512 and a DC cut capacitor 513 for cutting a DC component. Further, the termination resistor 51 is provided on the proximal end side of the distal end side of the transmission cable 3 from the first signal processing unit 52.

  The first signal processing unit 52 is provided on the proximal end side of the transmission cable 3 and is disposed between the termination resistor 51 and the AFE unit 53. The first signal processing unit 52 performs a first signal processing on the dummy signal transmitted from the transmission cable 3 to generate a first signal, and this first signal is sent to the AFE unit 53 (external). Output. Further, the first signal processing unit 52 outputs the imaging signal transmitted from the transmission cable 3 as it is to the AFE unit 53 (external). The first signal processing unit 52 includes a high-pass filter unit 521 (hereinafter referred to as “HPF unit 521”) and a switching unit 522.

  The HPF unit 521 is disposed between the termination resistor 51 and the switching unit 522. The HPF unit 521 performs first signal processing on the dummy signal transmitted via the transmission cable 3 to generate a first signal, and outputs the first signal to the switching unit 522. Here, the first signal processing is high-pass filter processing. In the first embodiment, the HPF unit 521 functions as a signal generation unit.

  The switching unit 522 has one end connected to the transmission cable 3 and the HPF unit 521, and the other end connected to the AFE unit 53. The switching unit 522 selectively switches one of the transmission cable 3 and the HPF unit 521 to connect to the AFE unit 53 under the control of the FPGA 57. The switching unit 522 is configured using a switch or the like.

  The AFE unit 53 receives the signal input from the switching unit 522, and performs analog processing such as gain-up processing and noise reduction processing (for example, CDS processing and clamp processing) on the received signal. Later, the data is output to the A / D converter 54. The AFE unit 53 is provided on the base end side of the transmission cable 3 and on the base end side downstream of the first signal processing unit 52. In the first embodiment, the AFE unit 53 functions as a second signal processing unit.

  The A / D converter 54 performs A / D conversion on the signal input from the AFE unit 53 and outputs the signal to the processor 6.

  The pulse generation unit 55 is supplied from the processor 6 and is a synchronization signal representing the start position of each frame based on a reference clock signal (for example, a 27 MHz clock signal) serving as a reference for the operation of each component of the endoscope 2. Is output to the timing generation unit 25 and the FPGA 57 of the imaging unit 20 through the transmission cable 3 together with the reference clock signal. Here, the synchronization signal (drive signal) generated by the pulse generation unit 55 includes a horizontal synchronization signal and a vertical synchronization signal. In the first embodiment, the pulse generation unit 55 functions as a generation unit that generates a drive signal for driving the imaging unit 20.

  The power supply voltage generator 56 generates a power supply voltage necessary for driving the first chip 21 and the second chip 22 from the power supplied from the processor 6 and outputs the power supply voltage to the first chip 21 and the second chip 22. . The power supply voltage generator 56 generates a power supply voltage necessary for driving the first chip 21 and the second chip 22 using a regulator or the like.

  Based on the reference clock signal and the synchronization signal input from the pulse generation unit 55, the FPGA 57 outputs the first signal processing unit 52 to the first signal processing unit 52 during the dummy signal output period in which the imaging unit 20 outputs the dummy signal from the dummy pixel 247. The signal processing is executed to output the first signal to the AFE unit 53. On the other hand, the FPGA 57 outputs the imaging signal to the first signal processing unit 52 as it is (without performing signal processing) to the AFE unit 53 in the imaging signal output period in which the imaging unit 20 outputs the imaging signal from the unit pixel 230. Let Specifically, the FPGA 57 controls the switching of the connection destination by the switching unit 522 based on the reference clock signal and the synchronization signal input from the pulse generation unit 55, thereby causing the switching unit 522 to HPF in the dummy signal output period. While the unit 521 and the AFE unit 53 are connected, the transmission cable 3 and the AFE unit 53 are connected to the switching unit 522 in the imaging signal output period. In the first embodiment, the FPGA 57 functions as a control unit.

[Processor configuration]
Next, the configuration of the processor 6 will be described.
The processor 6 is a control device that comprehensively controls the entire endoscope system 1. The processor 6 includes a power supply unit 61, an image signal processing unit 62, a clock generation unit 63, a recording unit 64, an input unit 65, and a processor control unit 66.

  The power supply unit 61 generates a power supply voltage, and supplies the generated power supply voltage together with the ground (GND) to the power supply voltage generation unit 56 of the connector unit 5.

  The image signal processing unit 62 performs synchronization processing, white balance (WB) adjustment processing, gain adjustment processing, gamma correction processing, digital analog (D / D) on the digital image pickup signal output from the A / D conversion unit 54. A) Image processing such as conversion processing and format conversion processing is performed to convert it into an image signal, and this image signal is output to the display device 7.

  The clock generation unit 63 generates a reference clock signal that serves as a reference for the operation of each component of the endoscope system 1, and outputs this reference clock signal to the pulse generation unit 55.

  The recording unit 64 records various information related to the endoscope system 1 and data being processed. The recording unit 64 is configured using a recording medium such as a flash memory or a RAM (Random Access Memory).

  The input unit 65 receives input of various operations related to the endoscope system 1. For example, the input unit 65 receives an input of an instruction signal for switching the type of illumination light emitted from the light source device 8. The input unit 65 is configured using, for example, a cross switch or a push button.

  The processor control unit 66 comprehensively controls each unit constituting the endoscope system 1. The processor control unit 66 is configured using a CPU (Central Processing Unit) or the like. The processor control unit 66 controls the endoscope system 1 according to the instruction signal input from the input unit 65.

[Configuration of the first chip]
Next, the detailed configuration of the first chip 21 described above will be described.
FIG. 3 is a block diagram showing a detailed configuration of the first chip 21 shown in FIG. FIG. 4 is a circuit diagram showing a configuration of the first chip 21.

  As shown in FIGS. 3 and 4, the first chip 21 includes a light receiving unit 23, a reading unit 24 (drive unit), a timing generation unit 25, a hysteresis unit 28, and an output unit 31 (amplifier). Have.

  The hysteresis unit 28 shapes the waveform of the reference clock signal and the synchronization signal input via the transmission cable 3, and outputs the reference clock signal and the synchronization signal subjected to the waveform shaping to the timing generation unit 25.

  The timing generation unit 25 generates various drive signals based on the reference clock signal and the synchronization signal input from the hysteresis unit 28, and a vertical scanning unit 241 (row selection circuit) of the readout unit 24, which will be described later, and a noise removal unit. 243 and the horizontal scanning unit 245, respectively.

  The reading unit 24 transfers the imaging signal output from each of a plurality of pixels of the light receiving unit 23 described later and the reference signal output from the reference voltage generation unit 246 to the output unit 31.

  Here, a detailed configuration of the reading unit 24 will be described. The reading unit 24 includes a vertical scanning unit 241 (row selection circuit), a constant current source 242, a noise removing unit 243 (noise removing circuit), a column source follower transistor 244, a horizontal scanning unit 245, and a reference voltage generating unit. 246.

  The vertical scanning unit 241 selects a selected row (horizontal line) <M> (M = 0, 1, 2,...) Of the light receiving unit 23 based on a drive signal (φT, φR, etc.) input from the timing generation unit 25. , M−1, m) by applying drive signals φT <M> and φR <M> and driving each unit pixel 230 and dummy pixel 247 of the light receiving unit 23 with a constant current source 242, The dummy signal and the noise signal at the time of pixel reset are transferred to the vertical transfer line 239 (first transfer line) and output to the noise removing unit 243.

  The noise removing unit 243 removes output variation of each unit pixel 230 and a noise signal at the time of pixel reset, and outputs an imaging signal photoelectrically converted by each unit pixel 230. Details of the noise removing unit 243 will be described later.

  The horizontal scanning unit 245 selects a selected column (vertical line) <N> (N = 0, 1, 2,..., N−) of the light receiving unit 23 based on the drive signal (φHCLK) supplied from the timing generation unit 25. 1, n) is applied with the drive signal φHCLK <N>, and the imaging signal photoelectrically converted by each unit pixel 230 is transferred to the horizontal transfer line 258 (second transfer line) via the noise removing unit 243, Output to the output unit 31. In the first embodiment, the horizontal transfer line 258 functions as a transfer unit that transfers an imaging signal output from each unit pixel 230.

  A large number of unit pixels 230 are arranged in a two-dimensional matrix in the light receiving unit 23 of the first chip 21. Each unit pixel 230 includes a photoelectric conversion element 231 (photodiode), a charge conversion unit 233, a transfer transistor 234 (first transfer unit), a pixel reset unit 236 (transistor), a pixel source follower transistor 237, Dummy pixels 247 (reference signal generation unit). In this specification, one or a plurality of photoelectric conversion elements and a transfer transistor for transferring signal charges from the respective photoelectric conversion elements to the charge conversion unit 233 are referred to as a unit cell. That is, the unit cell includes a set of one or a plurality of photoelectric conversion elements and transfer transistors, and each unit pixel 230 includes one unit cell.

  The photoelectric conversion element 231 photoelectrically converts incident light into a signal charge amount corresponding to the amount of light and accumulates it. The photoelectric conversion element 231 has a cathode connected to one end of the transfer transistor 234 and an anode connected to the ground GND. The charge conversion unit 233 includes a floating diffusion capacitor (FD), and converts the charge accumulated in the photoelectric conversion element 231 into a voltage.

  The transfer transistor 234 transfers charges from the photoelectric conversion element 231 to the charge conversion unit 233. A signal line to which a drive signal (row selection pulse) φR and a drive signal φT are supplied is connected to the gate of the transfer transistor 234, and the other end side is connected to the charge conversion unit 233. The transfer transistor 234 is turned on when the drive signal φR and the drive signal φT are supplied from the vertical scanning unit 241 via the signal line, and transfers the signal charge from the photoelectric conversion element 231 to the charge conversion unit 233.

  The pixel reset unit 236 resets the charge conversion unit 233 to a predetermined potential. The pixel reset unit 236 has one end connected to the power supply voltage VR, the other end connected to the charge conversion unit 233, and a gate connected to a signal line to which a drive signal φR is supplied. When the drive signal φR is supplied from the vertical scanning unit 241 via the signal line, the pixel reset unit 236 is turned on, and the signal charge accumulated in the charge conversion unit 233 is released, and the charge conversion unit 233 has a predetermined potential. Reset to.

  One end of the pixel source follower transistor 237 is connected to the power supply voltage VR, the other end is connected to the vertical transfer line 239, and a signal (imaging signal or reset signal) voltage-converted by the charge conversion unit 233 is connected to the gate. Entered. When a drive signal φT is supplied to the gate of the transfer transistor 234 after the selection operation described later, the pixel source follower transistor 237 reads the charge from the photoelectric conversion element 231 and is converted into a voltage by the charge conversion unit 233. Later, it is transferred to the vertical transfer line 239.

  A plurality of dummy pixels 247 are provided for each horizontal line of the unit pixel 230. In FIG. 4, an example in which one dummy pixel 247 is provided in each horizontal line is described for the sake of simplicity. However, the present invention is not limited to this, and the number of dummy pixels 247 may be changed as appropriate. Can do. The dummy pixel 247 includes a pixel reset unit 236a and a pixel source follower transistor 237a. That is, the photoelectric conversion element 231 (photodiode), the charge conversion unit 233, and the transfer transistor 234 (first transfer unit) are omitted from the unit pixel 230.

  The pixel reset unit 236a fixes the gate of the pixel source follower transistor 237a at a predetermined potential. One end of the pixel reset unit 236a is connected to the power supply voltage VR, the other end is connected to the gate of the pixel source follower transistor 237a, and a signal line to which the drive signal φT and the drive signal φR are supplied is connected to the gate.

  When the drive signal φR is supplied to the gate of the pixel reset unit 236a from the timing generation unit 25 via the signal line, the pixel reset unit 236a is turned on, and the gate of the pixel source follower transistor 237a is set to a predetermined potential (VR). Fixed.

  The pixel source follower transistor 237a has one end connected to the power supply voltage VR supplied from the reference voltage generation unit 246 (reference voltage generation unit 246a shown in FIG. 5A), the other end connected to the vertical transfer line 239, and the gate A predetermined potential (VR) is input. When the pixel source follower transistor 237a configured as described above performs a selection operation described later, a dummy signal (corresponding to an OB signal) corresponding to a predetermined potential (VR) is vertically transmitted via the pixel source follower transistor 237a. It is transferred to the transfer line 239.

  As in the case of the normal unit pixel 230, in the first embodiment, the power supply voltage VR is supplied to the gate of the pixel reset unit 236a when the power supply voltage VDD level (eg, 3.3V) and VR (eg, 2V) are input. When the drive signal φR is supplied, the pixel source follower transistor 237a is turned on, and the dummy pixel 247 including the pixel reset unit 236a is selected (selection operation). In addition, when the drive signal φR is supplied to the gate of the pixel reset unit 236a when the power supply voltage VR is input with a non-selection voltage level (for example, 1V) and VR (for example, 1V), the pixel source follower transistor 237a. Is turned off, and the selection of the dummy pixel 247 including the pixel reset unit 236a is released (non-selection operation).

  The constant current source 242 has one end connected to the vertical transfer line 239, the other end connected to the ground GND, and a bias voltage Vbias1 applied to the gate. The constant current source 242 drives the unit pixel 230 with the constant current source 242 and reads the output of the unit pixel 230 to the vertical transfer line 239. The signal read to the vertical transfer line 239 is input to the noise removing unit 243.

  The noise removing unit 243 includes a transfer capacitor 252 (AC coupling capacitor) and a clamp switch 253 (transistor).

  The transfer capacitor 252 has one end connected to the vertical transfer line 239 and the other end connected to the column source follower transistor 244.

  One end of the clamp switch 253 is connected to a signal line to which the clamp voltage Vclp is supplied from the reference voltage generation unit 246. The other end side of the clamp switch 253 is connected between the transfer capacitor 252 and the column source follower transistor 244, and the drive signal φVCL is input from the timing generation unit 25 to the gate. The imaging signal input to the noise removing unit 243 is an optical noise sum signal including a noise component.

  The transfer capacitor 252 is reset by the clamp voltage Vclp supplied from the reference voltage generator 246 when the drive signal φVCL is input from the timing generator 25 to the gate of the clamp switch 253 and the clamp switch 253 is turned on. . The imaging signal from which noise has been removed by the noise removing unit 243 is input to the gate of the column source follower transistor 244.

  Since the noise removing unit 243 does not require a sampling capacitor (sampling capacity), the capacity of the transfer capacity (AC coupling capacitor) 252 may be sufficient with respect to the input capacity of the column source follower transistor 244. In addition, the noise removing unit 243 can reduce the area occupied by the first chip 21 because of the absence of the sampling capacity.

  The column source follower transistor 244 has one end side connected to the power supply voltage VDD, the other end side connected to one end side of the column selection switch 254 (second transfer unit), and a gate in which noise is removed by the noise removing unit 243. A signal is input.

  The column selection switch 254 has one end connected to the other end of the column source follower transistor 244, the other end connected to the horizontal transfer line 258 (second transfer line), and a gate from the horizontal scanning unit 245 to the drive signal φHCLK. A signal line for supplying <M> is connected. The column selection switch 254 is turned on when the drive signal φHCLK <M> is supplied from the horizontal scanning unit 245 to the gate of the column selection switch 254 of the column <M>, and the signal of the vertical transfer line 239 of the column <M>. The image pickup signal from which noise has been removed by the noise removing unit 243 is transferred to the horizontal transfer line 258.

  One end of the horizontal reset transistor 256 is connected to the ground GND, the other end is connected to the horizontal transfer line 258, and a drive signal φHCLR is input to the gate from the timing generator 25. The horizontal reset transistor 256 is turned on when the drive signal φHCLR is input from the timing generation unit 25 to the gate of the horizontal reset transistor 256 and resets the horizontal transfer line 258.

  The constant current source 257 has one end connected to the horizontal transfer line 258, the other end connected to the ground GND, and a bias voltage Vbias2 applied to the gate. The constant current source 257 reads the imaging signal from the vertical transfer line 239 to the horizontal transfer line 258. The imaging signal or dummy signal read to the horizontal transfer line 258 is input to the output unit 31.

  The output unit 31 amplifies the noise-removed imaging signal and the dummy signal (a reference signal that serves as a reference when correcting the horizontal line) as necessary and outputs the amplified signal (Vout).

  In the first embodiment, the readout of the imaging signal after noise removal from the vertical transfer line 239 and the reset of the horizontal transfer line 258 by the horizontal reset transistor 256 are performed alternately, thereby cross-talking the imaging signal in the column direction. Can be suppressed.

  In the second chip 22, the dummy signal and the imaging signal are transmitted to the connector unit 5 through the transmission cable 3.

  5A and 5B are circuit diagrams showing the configuration of the reference voltage generation unit 246 of the light receiving unit 23 of the endoscope 2 according to the first embodiment.

  The reference voltage generation unit 246a illustrated in FIG. 5A includes a resistance voltage dividing circuit including two resistors 291 and 292, and a multiplexer 293 driven by a drive signal φVRSEL.

  The multiplexer 293 alternately generates the power supply voltage VDD (for example, 3.3 V) and the non-selection voltage Vfd_L (for example, 1 V) generated by the resistance voltage dividing circuit in accordance with the drive signal φVRSEL input from the timing generation unit 25. Switching is applied to all the pixels and the dummy pixel 247 as the power supply voltage VR.

  The reference voltage generation unit 246b illustrated in FIG. 5B includes a resistance voltage dividing circuit including two resistors 291 and 292, and a switch (transistor) 294 driven by the drive signal φVSH. The reference voltage generation unit 246b generates the clamp voltage Vclp of the noise removal unit 243 at the timing when the drive signal φVSH is driven by driving the switch 294.

[Operation of endoscope system]
Next, the operation of the endoscope system 1 described above will be described. FIG. 6 is a flowchart showing an outline of processing executed by the endoscope system 1, and is a flowchart showing an example of processing executed by the FPGA 57.

  As illustrated in FIG. 6, the FPGA 57 determines whether the period during which the imaging unit 20 outputs a signal is a dummy signal output period based on the reference clock signal and the synchronization signal input from the pulse generation unit 55. (Step S101). When the FPGA 57 determines that the dummy signal output period is in effect (step S101: Yes), the endoscope system 1 proceeds to step S102 described later. In contrast, when the FPGA 57 determines that it is not the dummy signal output period (step S101: No), the endoscope system 1 proceeds to step S104 described later.

  In step S <b> 102, the FPGA 57 controls the switching unit 522 to connect the HPF unit 521 and the AFE unit 53, thereby outputting the first signal from the HPF unit 521 to the AFE unit 53. Thereby, in the dummy signal output period, the first signal (dummy signal from which noise has been cut) subjected to the high-pass filter processing in the HPF unit 521 is output from the switching unit 522 to the AFE unit 53. The resulting horizontal stripe noise can be reduced.

  Subsequently, when an instruction signal to be ended is input from the processor 6 (step S103: Yes), the endoscope system 1 ends this process. On the other hand, when the instruction | indication signal which complete | finishes from the processor 6 is not input (step S103: No), the endoscope system 1 returns to step S101 mentioned above.

  In step S <b> 104, the FPGA 57 controls the switching unit 522 to connect the transmission cable 3 and the AFE unit 53, thereby outputting the imaging signal from the second chip 22 of the imaging unit 20 to the AFE unit 53 as it is. . As a result, the imaging signal from the imaging unit 20 is output to the AFE unit 53 as it is without passing through the HPF unit 521. After step S104, the endoscope system 1 proceeds to step S103.

  According to the first embodiment of the present invention described above, the horizontal stripe noise can be accurately corrected even when different noises are generated between the dummy pixel 247 and the unit pixel 230.

  Further, according to the first embodiment of the present invention, the switching unit 522 is arranged immediately after the HPF unit 521, so that the cable resistance of the transmission cable 3 and the switching can be switched even when the small-diameter transmission cable 3 is used. This can be performed without considering matching with the impedance of the portion 522.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The second embodiment is different in configuration from the endoscope 2 according to the first embodiment described above. Specifically, the endoscope according to the second embodiment is configured by disposing a switching unit between the terminal resistance, the AFE unit, and the HPF unit. Hereinafter, the configuration of the endoscope system according to the second embodiment will be described. In addition, the same code | symbol is attached | subjected to the structure same as the endoscope system 1 which concerns on Embodiment 1 mentioned above, and description is abbreviate | omitted.

[Configuration of endoscope system]
FIG. 7 is a block diagram illustrating functions of main parts of the endoscope system according to the second embodiment. An endoscope system 1a shown in FIG. 7 includes an endoscope 2a instead of the endoscope 2 according to the first embodiment described above. The endoscope 2a includes a connector portion 5a instead of the connector portion 5 according to the first embodiment described above.

  The connector unit 5a includes a termination resistor 51, a first signal processing unit 52a, an AFE unit 53, an A / D conversion unit 54, a pulse generation unit 55, a power supply voltage generation unit 56, and an FPGA 57. .

  The first signal processing unit 52 a is provided on the proximal end side of the transmission cable 3 and is disposed between the termination resistor 51 and the AFE unit 53. The first signal processing unit 52a can perform first signal processing on the dummy signal transmitted from the transmission cable 3 to generate a first signal and output the first signal to the AFE unit 53 (external). The imaging signal transmitted from the transmission cable 3 is output to the AFE unit 53 (external) as it is. The first signal processing unit 52a includes a switching unit 522a and an HPF unit 521a.

  The switching unit 522a is disposed between the termination resistor 51, the AFE unit 53, and the HPF unit 521a, one end side is connected to the transmission cable 3 via the termination resistor 51, and the other end side is connected to the AFE unit 53 and the HPF unit 521a. Is done. The switching unit 522a selectively switches one of the AFE unit 53 and the HPF unit 521a in the transmission cable 3 under the control of the FPGA 57.

  The HPF unit 521a performs first signal processing on the dummy signal input via the switching unit 522a to generate a first signal, and outputs the first signal to the AFE unit 53.

  In the endoscope system 1 a configured as described above, the FPGA 57 switches when it is determined that it is the dummy signal output period of the imaging unit 20 based on the reference clock signal and the synchronization signal input from the pulse generation unit 55. By connecting the transmission cable 3 and the HPF unit 521a to the unit 522, the dummy signal input from the imaging unit 20 is subjected to the first signal processing on the HPF unit 521a and output to the AFE unit 53. On the other hand, when the FPGA 57 determines that it is the image signal output period of the imaging unit 20 based on the reference clock signal and the synchronization signal input from the pulse generation unit 55, the FPGA 57 and the AFE are switched to the switching unit 522. By connecting to the unit 53, the imaging signal input from the imaging unit 20 is output to the AFE unit 53 as it is.

  According to the second embodiment of the present invention described above, the horizontal stripe noise can be accurately corrected even when different noises are generated in the dummy pixel 247 and the unit pixel 230.

(Other embodiments)
In the first and second embodiments, the HPF unit performs high-pass filter processing on the dummy signal as the first signal processing. However, for example, the HPF unit is configured by a band bus circuit instead of the HPF unit, Then, band-pass filter processing may be performed.

  In the first and second embodiments, the HPF unit is provided in the first signal processing unit. However, for example, under the control of the FPGA, filter processing performance, for example, filter processing for cutting only a predetermined frequency component is performed. A filter circuit for performing the above may be provided.

  In the first and second embodiments, the first signal processing unit is provided in the connector unit. However, the first signal processing unit is not limited to this, and may be provided, for example, in the second chip. Of course, the first signal processing unit may be provided in the processing device (processor).

  As described above, the present invention can include various embodiments not described herein, and various design changes and the like can be made within the scope of the technical idea specified by the claims. Is possible.

DESCRIPTION OF SYMBOLS 1, 1a Endoscope system 2, 2a Endoscope 3 Transmission cable 4 Operation part 5, 5a Connector part 6 Processor 7 Display apparatus 8 Light source device 20 Imaging part 21 1st chip 22 2nd chip 23 Light-receiving part 24 Reading part 25 Timing generation unit 27 Buffer 28 Hysteresis unit 31 Output unit 51 Termination resistor 52, 52a First signal processing unit 53 AFE unit 54 A / D conversion unit 55 Pulse generation unit 56 Power supply voltage generation unit 57 FPGA
61 power supply unit 62 image signal processing unit 63 clock generation unit 64 recording unit 65 input unit 66 processor control unit 100 insertion unit 101 front end 102 base end 230 unit pixel 231 photoelectric conversion element 233 charge conversion unit 234 transfer transistor 236, 236a pixel reset unit 237, 237a Pixel source follower transistor 239, 241 Vertical transfer line 241 Vertical scanning unit 242, 257 Constant current source 243 Noise removal unit 244 Column source follower transistor 245 Horizontal scanning unit 246, 246a, 246b Reference voltage generation unit 247 Dummy pixel 252 Transfer Capacitance 253 Clamp switch 254 Column selection switch 256 Horizontal reset transistor 258 Horizontal transfer line 291 Resistance 293 Multiplexer 294 Switch 503 DC cut capacitor 5 11 AC termination resistor 512 DC termination resistor 521, 521a HPF unit 522, 522a switching unit C1 capacitor

Claims (6)

A plurality of effective pixels that are arranged in a two-dimensional matrix, receive light from outside, generate and output an imaging signal corresponding to the amount of received light, and are provided for each horizontal line in the arrangement of the plurality of effective pixels, An imaging device having one or more dummy pixels that generate and output a dummy signal used for correction processing of the imaging signal;
A transmission cable connected to the imaging device and transmitting the imaging signal and the dummy signal;
Provided on the base end side of the transmission cable and capable of outputting to the outside while receiving the imaging signal, and performing a first signal processing on the dummy signal to generate a first signal A first signal processing unit for outputting to the outside,
A generating unit that generates a drive signal for driving the image sensor;
Based on the drive signal generated by the generation unit, the first signal processing unit is caused to execute the first signal processing in a dummy signal output period in which the dummy pixel outputs the dummy signal. A control unit that causes the first signal processing unit to output the imaging signal to the outside as it is in an imaging signal output period in which the effective pixel outputs the imaging signal while outputting the signal to the outside;
An endoscope characterized by comprising: A termination resistor provided on the proximal end side of the transmission cable, on the proximal end side of the transmission cable from the first signal processing unit;
A second signal that is provided on the proximal end side of the transmission cable and downstream from the first signal processing unit and performs signal processing for correcting the imaging signal using the first signal. A processing unit;
With
The first signal processing unit is provided between the termination resistor and the second signal processing unit, and outputs the imaging signal and the first signal to the second signal processing unit. The endoscope according to claim 1. The first signal processing unit includes:
A third signal processing unit that performs the first signal processing on the dummy signal to generate the first signal;
A switching unit that selectively switches one of the transmission cable and the third signal processing unit to connect to the second signal processing unit;
Have
The control unit connects the third signal processing unit and the second signal processing unit to the switching unit in the dummy signal output period, and connects the transmission cable to the switching unit in the imaging signal output period. The endoscope according to claim 2, wherein the endoscope is connected to the second signal processing unit. The first signal processing unit includes:
A third signal processing unit that performs the first signal processing on the dummy signal to generate the first signal;
A switching unit that selectively switches one of the second signal processing unit and the third signal processing unit to connect to the transmission cable;
Have
The control unit connects the third signal processing unit and the transmission cable to the switching unit in the dummy signal output period, and connects the second signal processing unit to the switching unit in the imaging signal output period. The endoscope according to claim 2, wherein the endoscope is connected to the transmission cable.   The endoscope according to claim 3 or 4, wherein the first signal processing unit includes either a high-pass filter or a band-pass filter.   The said control part changes the content of the said 1st signal processing which the said 1st signal processing part performs based on the said drive signal which the said production | generation part produced | generated. Endoscope.

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