JP2019146064A - Imaging element, imaging device, endoscope, and endoscope system - Google Patents

Abstract

To provide an imaging element, imaging device, endoscope, and endoscope system, capable of preventing application of high voltage to the imaging element regardless of a drive state of the imaging element.SOLUTION: An imaging unit 20 comprises: a pixel unit 211 including a plurality of pixels that are arranged in a two-dimensional matrix shape and generate and output an imaging signal depending on a quantity of incident light; a signal processing unit 222 that takes the imaging signal output from the pixel unit 211 as an input signal and outputs to the outside an output signal corresponding to the input signal; a monitoring unit 226 that on the basis of a magnitude of a voltage level of an input terminal 221 and a magnitude of a preset reference level, outputs a control signal for controlling a current value; and a current generation unit 227 that according to the control signal output by the monitoring unit 226, generates predetermined current.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an imaging device, an imaging device, an endoscope, and an endoscope system that are inserted into a subject and that captures an image of the inside of the subject to generate image data.

  Conventionally, an imaging signal output from an imaging device is amplified by an imaging device such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) at the distal end of an insertion portion of an endoscope and an amplifier provided in the vicinity of the imaging device. A technique for outputting to a processor is known (see Patent Document 1). In this technique, a DC signal applied to the image sensor and the amplifier is generated by using a pulse signal for driving the image sensor, thereby reducing the number of power cables, thereby reducing the size of the insertion portion of the endoscope. We are trying to reduce the diameter.

JP 2003-153858 A

  By the way, as for the power supply of the image sensor provided in the conventional endoscope, the power cable becomes thinner as the insertion portion of the endoscope becomes thinner, and the resistance of the power cable increases. For this reason, in a conventional endoscope, the power supply voltage is determined in consideration of a voltage drop due to current consumption of the image sensor during normal operation. However, in the endoscope in which the diameter of the power cable is reduced as in Patent Document 1 described above, when the current consumption is smaller than that during normal operation, the current consumption is greatly reduced, and a high voltage is applied to the image sensor. As a result, the breakdown voltage of the image sensor may be exceeded.

  The present invention has been made in view of the above, and includes an image pickup device, an image pickup apparatus, and an image pickup device capable of preventing a high voltage from being applied to the image pickup device regardless of the driving state of the image pickup device. An object is to provide an endoscope and an endoscope system.

In order to solve the above-described problems and achieve the object, an imaging device according to the present disclosure is arranged in a two-dimensional matrix, and includes a pixel unit having a plurality of pixels that generate and output an imaging signal corresponding to the amount of incident light A signal processing unit that outputs the imaging signal output from the pixel unit as an input signal and outputs an output signal corresponding to the input signal to the outside, a voltage level magnitude of a predetermined terminal, and a preset reference level A monitoring unit that outputs a control signal that controls a current value based on the magnitude, and a current generation unit that generates a predetermined current according to the control signal output by the monitoring unit.

  Further, the imaging device according to the present disclosure is characterized in that, in the above disclosure, the monitoring unit compares the voltage level with the reference level and outputs the comparison result as the control signal. .

  In the imaging device according to the present disclosure, in the above disclosure, the monitoring unit compares the reference level generation unit that generates the reference level, the magnitude of the voltage level and the magnitude of the reference level, and the comparison result. And a comparison section that outputs as a control signal.

  Further, in the imaging device according to the present disclosure, in the above disclosure, the current generation unit includes a switch circuit having a transistor and a resistor having a predetermined value, and the resistance of the resistor when the switch circuit is turned on by the control signal. A current based on the value is generated.

  Further, in the imaging device according to the present disclosure, in the above disclosure, the current generation unit includes a switch circuit having a transistor and a resistor having a predetermined value, and the resistance of the resistor when the switch circuit is turned on by the control signal. A current based on the value is generated by the signal processing unit.

  In the imaging device according to the present disclosure, in the above disclosure, the comparison unit includes at least a logic circuit, the reference level is a circuit threshold value of the logic circuit, and the logic circuit receives the input voltage. The level is compared with the reference level.

  In the image sensor according to the present disclosure, in the above disclosure, the comparison unit includes at least an inverter circuit, the reference level is a circuit threshold value of the inverter circuit, and the inverter circuit receives the input voltage. The level is compared with the reference level.

  Further, in the imaging device according to the present disclosure, in the above disclosure, the reference level generation unit includes a resistor provided between a power supply voltage and a ground, and the reference level is a voltage level obtained by dividing the resistance by the resistor. It is characterized by being.

  Further, the imaging device according to the present disclosure is characterized in that, in the above disclosure, the reference level generation unit includes a band gap reference circuit, and the reference level is a voltage level generated by the band gap reference circuit. And

  In the above disclosure, the imaging device according to the present disclosure is characterized in that the comparison unit includes a comparator circuit that compares the magnitude of the voltage level with the magnitude of the reference level.

  In the above disclosure, the imaging device according to the present disclosure includes a first chip in which the plurality of pixels are arranged, and a second chip in which the signal processing unit, the monitoring unit, and the current generation unit are arranged. The first chip is stacked on the second chip.

  In the above disclosure, the imaging device according to the present disclosure is characterized in that the monitoring unit outputs the control signal when the imaging device is activated.

  In addition, an imaging apparatus according to the present disclosure includes the above-described imaging element.

  In addition, an endoscope according to the present disclosure includes the above-described imaging device and an insertion unit that can be inserted into a subject, and the insertion unit includes the imaging device disposed at a distal end portion. Features.

  An endoscope system according to the present disclosure includes the endoscope disclosed above and a processing device that performs image processing on the imaging signal to generate an image signal.

  According to the present disclosure, there is an effect that it is possible to prevent a high voltage from being applied to the image sensor regardless of the driving state of the image sensor.

FIG. 1 is a diagram schematically illustrating an overall configuration of an endoscope system according to the first embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a timing chart of operation processing of the imaging unit according to Embodiment 1 of the present disclosure. FIG. 4 is a diagram in which the power supply voltage VDD, the input terminal, and the circuit threshold values of the first inverter in the endoscope system according to the first embodiment of the present disclosure are summarized on the same voltage axis. FIG. 5 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the second embodiment of the present disclosure. FIG. 6 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the third embodiment of the present disclosure. FIG. 7 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the fourth embodiment of the present disclosure. FIG. 8 is a diagram illustrating a timing chart of operation processing of the imaging unit according to Embodiment 4 of the present disclosure. FIG. 9 is a diagram in which the power supply voltage VDD, the input terminal, and the circuit threshold values of the first inverter of the endoscope system according to the fourth embodiment of the present disclosure are summarized on the same voltage axis. FIG. 10 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the fifth embodiment of the present disclosure. FIG. 11 is a diagram illustrating a timing chart of operation processing of the imaging unit according to Embodiment 5 of the present disclosure. FIG. 12 is a diagram in which the power supply voltage VDD, the input terminal, and the circuit threshold values of the first inverter in the endoscope system according to the fifth embodiment of the present disclosure are summarized on the same voltage axis. FIG. 13 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the sixth embodiment of the present disclosure. FIG. 14 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the seventh embodiment of the present disclosure.

  Hereinafter, as an embodiment for carrying out the present invention (hereinafter referred to as “embodiment”), an endoscope system including an endoscope in which a distal end portion is inserted into a subject will be described. Further, the present invention is not limited by this embodiment. Furthermore, the same code | symbol is attached | subjected to the same part in description of drawing. Furthermore, the drawings are schematic, and it should be noted that the relationship between the thickness and width of each member, the ratio of each member, and the like are different from the actual ones. Moreover, the part from which a mutual dimension and ratio differ also in between drawings.

(Embodiment 1)
[Configuration of endoscope system]
FIG. 1 is a diagram schematically illustrating an overall configuration of an endoscope system according to the first embodiment of the present disclosure. An endoscope system 1 shown in FIG. 1 includes an endoscope 2, a transmission cable 3, a connector unit 5, a processor 6 (processing device), a display device 7, and a light source device 8.

  The endoscope 2 images the inside of the subject by inserting the insertion portion 100 which is a part of the transmission cable 3 into the body cavity of the subject. The endoscope 2 outputs an imaging signal generated by imaging the inside of the subject to the processor 6. In addition, the endoscope 2 is provided on one end side of the transmission cable 3 and an imaging unit 20 (imaging device) that performs imaging on the distal end 101 side of the insertion unit 100 inserted into the body cavity of the subject. Yes. Furthermore, in the endoscope 2, an operation unit 4 that receives various operations on the endoscope 2 is connected to the proximal end 102 side of the insertion unit 100. An imaging signal generated by imaging by the imaging unit 20 is output to the connector unit 5 via the transmission cable 3 having a length of, for example, several meters.

  The connector unit 5 is detachably connected to the processor 6 and the light source device 8. The connector unit 5 performs predetermined signal processing on the imaging signal transmitted from the transmission cable 3 and outputs it to the processor 6.

  The processor 6 performs predetermined image processing on the imaging signal input from the connector unit 5 and outputs the processed image signal to the display device 7. Further, the processor 6 controls the entire endoscope system 1 in an integrated manner.

  The display device 7 displays an image corresponding to the image signal subjected to image processing by the processor 6. The display device 7 displays various information related to the endoscope system 1.

  Under the control of the processor 6, the light source device 8 irradiates illumination light from the distal end 101 side of the insertion portion 100 of the endoscope 2 toward the subject via the connector portion 5 and the transmission cable 3. The light source device 8 is configured using, for example, a halogen lamp lamp, a white LED (Light Emitting Diode), or the like. In the first embodiment, an example in which the light source device 8 is a simultaneous type will be described. However, the light source device 8 is a surface sequential type that irradiates red, green, and blue illumination light while sequentially switching depending on the type of the imaging unit 20. Also good.

[Functional configuration of main part of endoscope system]
Next, the functional configuration of the main part of the endoscope system 1 described above will be described. FIG. 2 is a block diagram illustrating a functional configuration of a main part of the endoscope system 1.

[Configuration of endoscope]
First, the configuration of the endoscope 2 will be described.
As shown in FIG. 2, the endoscope 2 includes an imaging unit 20, a transmission cable 3, and a connector unit 5.

  The imaging unit 20 includes a first chip 21 and a second chip 22. The first chip 21 and the second chip 22 receive a power supply voltage VDD (for example, 3.3 V) supplied from a power supply unit 61 of the processor 6 described later via the signal lines 31 and 32 of the transmission cable 3 and the connector unit 5. Receive with Grand GND. Further, the first chip 21 receives a drive signal supplied from a drive signal generation unit 63 of the processor 6 described later via the signal line 33 of the transmission cable 3. The first chip 21 is formed by being stacked on the second chip 22. A power stabilization capacitor may be provided between the power supply voltage VDD supplied to the imaging unit 20 and the ground GND. In the first embodiment, the first chip 21 and the second chip 22 function as an image sensor.

  The first chip 21 has a pixel unit 211. The pixel unit 211 has a plurality of pixels arranged in a two-dimensional matrix in the matrix direction. Each of the plurality of pixels receives light from the outside, generates an imaging signal corresponding to the amount of received light, and outputs the generated imaging signal. The pixel unit 211 is configured using a CMOS (Complementary Metal Oxide Semiconductor) image sensor. In addition, the pixel unit 211 includes a reading unit (not shown) and a timing generation unit (not shown). The reading unit reads the imaging signal photoelectrically converted by the pixel unit 211 and outputs it to the input terminal 221 of the second chip 22. The timing generation unit generates a timing signal based on a drive signal (including a reference clock signal and a synchronization signal) input via the transmission cable 3 and the connector unit 5 and outputs the timing signal to the reading unit. Note that the reading unit and the timing generation unit may be provided in the second chip 22 described later.

  The second chip 22 is input from the input terminal 221 to which the imaging signal is input from the first chip 21, the signal processing unit 222 that amplifies and outputs the imaging signal input from the input terminal 221, and the signal processing unit 222. And an output terminal 223 for outputting the captured image signal. In the first embodiment, the input terminal 221 corresponds to a predetermined terminal.

  The signal processing unit 222 amplifies the imaging signal input from the input terminal 221 and outputs the amplified image signal to the output terminal 223. The signal processing unit 222 includes a transistor 224, a resistor 225, a monitoring unit 226, and a current generation unit 227.

  The transistor 224 is configured using an NMOS transistor. The transistor 224 has a drain terminal connected to the power supply voltage VDD, a source terminal connected to a resistor 225 for matching the impedance of the transmission cable 3, and a gate terminal to which an imaging signal is input from the first chip 21. Is connected. The transistor 224 amplifies the imaging signal input from the input terminal 221 and outputs the amplified imaging signal to the signal line 34 of the transmission cable 3 via the resistor 225 and the output terminal 223.

  The monitoring unit 226 outputs a control signal for controlling a current value flowing through the pixel unit 211 to the current generation unit 227 based on the voltage level of the input terminal 221 and a preset reference level. Specifically, the monitoring unit 226 compares the magnitude of the voltage level of the input terminal 221 with a preset reference level, and outputs the comparison result to the current generation unit 227 as a control signal. The monitoring unit 226 is configured using a logic circuit. Specifically, the monitoring unit 226 includes a first inverter circuit 2261 and a second inverter circuit 2262 that function as a comparison unit.

  The first inverter circuit 2261 generates a control signal based on the magnitude of the voltage level input to the input terminal 221 and the preset reference level, and sends this control signal to the second inverter circuit 2262. Output. The first inverter circuit 2261 detects the magnitude of the voltage level input to the input terminal 221. Specifically, the first inverter circuit 2261 detects the voltage level of the input terminal 221 and compares the detected voltage level of the input terminal 221 with the reference level. Then, the first inverter circuit 2261 outputs a comparison result obtained by comparing the magnitude of the voltage level of the input terminal 221 and the magnitude of the reference level to the second inverter circuit 2262. Here, the reference level is a circuit threshold value of the first inverter circuit 2261. For example, the circuit threshold is 1.5 V when the power supply voltage VDD is 3.0 V. That is, the first inverter circuit 2261 compares and determines whether or not the voltage level of the input terminal 221 is greater than or equal to the reference level threshold value, and outputs the comparison result to the second inverter circuit 2262 as a control signal. To do. Specifically, in the first inverter circuit 2261, when the voltage level of the input terminal 221 is less than the reference level, the voltage level of the input terminal 221 is less than the reference level. A control signal indicating a comparison result is output to the second inverter circuit 2262. In contrast, in the first inverter circuit 2261, when the voltage level of the input terminal 221 is equal to or larger than the reference level, the voltage level of the input terminal 221 is equal to or larger than the reference level. A control signal indicating a comparison result is output to the second inverter circuit 2262.

  The second inverter circuit 2262 outputs an on / off signal to the current generator 227 based on the control signal input from the first inverter circuit 2261. Specifically, the second inverter circuit 2262 receives a comparison result control signal indicating that the voltage level of the input terminal 221 is less than the reference level from the first inverter circuit 2261. In the case, the ON signal is output to the current generator 227. On the other hand, the second inverter circuit 2262 receives a comparison control signal indicating that the voltage level of the input terminal 221 is greater than or equal to the reference level from the first inverter circuit 2261. In this case, an off signal is output to the current generator 227.

  The current generation unit 227 changes the value of the current flowing through the pixel unit 211 based on the control signal output from the monitoring unit 226. The current generator 227 includes a transistor 2271 and a resistor 2272 having a predetermined resistance value.

  The transistor 2271 is configured using a PMOS transistor. In the transistor 2271, the power supply voltage VDD is connected to the drain terminal, the resistor 2272 is connected to the source terminal, and the second inverter circuit 2262 is connected to the gate terminal. The transistor 2271 is turned on when an on signal is input from the second inverter circuit 2262, and a current determined by the resistor 2272 is supplied. On the other hand, the transistor 2271 is turned off when the off signal is input from the second inverter circuit 2262, and a current determined by the resistor 2272 does not flow.

  The connector unit 5 has a circuit board 51. The circuit board 51 includes a receiving circuit 511 and a processing circuit 512.

  The receiving circuit 511 receives the imaging signal transmitted via the signal line 34 of the transmission cable 3 and outputs the received imaging signal to the processing circuit 512. The reception circuit 511 includes at least an AC termination resistor 5111 connected to GND, a DC termination resistor 5112 connected to GND, and a DC cut capacitor 5113 that cuts a DC current output from the second chip 22. .

  The processing circuit 512 performs signal processing on the imaging signal input from the receiving circuit 511 and outputs the imaging signal subjected to this signal processing to the processor 6. The processing circuit 512 includes an analog front end unit 5121 (hereinafter referred to as “AFE unit 5121”) and an imaging signal processing unit 5122.

  The AFE unit 5121 receives the imaging signal output from the receiving circuit 511, extracts an AC component with a capacitor, and determines an operating point with a voltage dividing circuit. The AFE unit 5121 performs A / D conversion on the analog imaging signal transmitted from the receiving circuit 511 and outputs the analog imaging signal to the imaging signal processing unit 5122 as a digital imaging signal.

  The imaging signal processing unit 5122 performs predetermined signal processing such as vertical line removal and noise removal on the digital imaging signal input from the AFE unit 5121 and outputs the result to the processor 6. The imaging signal processing unit 5122 is configured using, for example, an FPGA (Field Programmable Gate Array).

[Processor configuration]
Next, the configuration of the processor 6 will be described.
The processor 6 includes a power supply unit 61, an image signal processing unit 62, a drive signal generation unit 63, a recording unit 64, an input unit 65, and a control unit 66.

  The power supply unit 61 generates a power supply voltage VDD under the control of the control unit 66, and outputs the generated power supply voltage VDD to the signal lines 31 and 32 of the transmission cable 3 together with the ground GND. Specifically, the power supply unit 61 generates a power supply voltage VDD by adjusting the supply power input from the outside to a predetermined voltage, for example, 3.3 V, under the control of the control unit 66. The supplied power supply voltage VDD is output to the signal line 31 of the transmission cable 3. The power supply unit 61 is configured using a voltage regulator or the like.

  The image signal processing unit 62 performs synchronization processing, white balance (WB) adjustment processing, and gain adjustment on the digital imaging signal subjected to signal processing by the imaging signal processing unit 5122 under the control of the control unit 66. Image processing such as processing, γ correction processing, and format conversion processing is performed to convert the image signal into an image signal, and the image signal is output to the display device 7. The image signal processing unit 62 is configured using a GPU (Graphics Processing Unit), an FPGA, or the like.

  Under the control of the control unit 66, the drive signal generation unit 63 generates a drive signal including a reference clock signal and a synchronization signal that are the operations of the respective components of the endoscope system 1, and transmits the drive signal to the transmission cable 3 Output to the signal line 33. The drive signal generation unit 63 is configured using a clock generator or the like.

  The recording unit 64 records various programs executed by the endoscope system 1, data being processed, image data, and the like. The recording unit 64 is configured using a volatile memory, a nonvolatile memory, and a memory card.

  The input unit 65 receives input of various operations related to the endoscope system 1. For example, the input unit 65 receives an input of an instruction signal for switching the type of illumination light emitted from the light source device 8 and an instruction signal for instructing termination. The input unit 65 is configured using, for example, a changeover switch, a cross switch, a push button, a touch panel, and the like.

  The control unit 66 comprehensively controls each unit constituting the endoscope system 1. The control unit 66 is configured using a CPU (Central Processing Unit) or the like. The control unit 66 switches the illumination light emitted from the light source device 8 in accordance with the instruction signal input from the input unit 65.

[Configuration of display device]
The display device 7 displays the image captured by the imaging unit 20 based on the image signal input from the image signal processing unit 62. The display device 7 is configured using a display panel such as liquid crystal or organic EL (Electro Luminescence).

[Operation processing of imaging unit]
Next, operation processing of the imaging unit 20 will be described. FIG. 3 is a diagram illustrating a timing chart of the operation process of the imaging unit 20. FIG. 4 is a diagram in which the power supply voltage VDD, the input terminal 221, and the circuit threshold values of the first inverter circuit 2261 are grouped on the same voltage axis. 3 and 4, the horizontal axis indicates time, and the vertical axis indicates voltage (V). In FIG. 3, (a) shows the timing of the synchronization signal, (b) shows the timing of the clock signal, (c) shows the output change of the power supply voltage VDD, and (d) shows the second signal from the top. An output change of the inverter circuit 2262 is shown, (e) shows an output change of the first inverter circuit 2261, and (f) shows an output change of each of the input terminal 221 and the transistor 224. Further, in FIGS. 3 and 4, a curve L1 indicates an output change of the power supply voltage VDD, a broken line L2 indicates an output change of the second inverter circuit 2262, a curve L3 indicates an output change of the inverter INV1, and a broken line L4 indicates The output changes of the input terminal 221 and the transistor 224 are shown. Further, in FIG. 4, a curve L <b> 11 indicates a change in output of the conventional power supply voltage VDD, and a curve LT <b> 1 indicates a circuit threshold value of the first inverter circuit 2261.

  In the following description, when the imaging unit 20 is activated, the time from when power is supplied to the endoscope 2 to when the pixel unit 211 starts to be activated when the power supply voltage VDD is supplied to the pixel unit 211. A short period. Specifically, as shown in FIG. 3, when the pixel unit 211 is activated, the pixel signal is supplied from the drive signal generation unit 63 of the processor 6 to the pixel unit from the time when the power supply voltage VDD is supplied to the pixel unit 211 and the activation is started. A period from when the synchronization signal is output to 211 to when it is received by the pixel unit 211.

  The normal operation of the imaging unit 20 is a period from the time when the pixel unit 211 starts outputting the imaging signal to the time when the imaging signal is stopped after the pixel unit 211 is started, This is a period in which the operation of the unit 211 itself is stable and the power consumption in the transmission cable 3 that supplies the power supply voltage VDD to the pixel unit 211 is also within the rated operation range.

  As shown in FIGS. 3 and 4, first, when the imaging unit 20 is activated, the first inverter circuit 2261 has a voltage level input to the input terminal 221 and a threshold LT1 (for example, 1) as a reference level. .5V), and if it is less than the threshold LT1, the second inverter circuit 2262 outputs a control signal indicating that the magnitude of the voltage level input to the input terminal 221 is less than the threshold LT1. In this case, as illustrated in FIGS. 3 and 4, the transistor 2271 is turned on because the on signal is input from the second inverter circuit 2262, and is determined by the resistance value of the transistor 2271 and the resistance value of the resistor 2272. Current flows. As a result, as shown by the curves L1 and L11 in FIG. 4, according to the first embodiment, the power supply voltage VDD exceeding the rated operation range of the pixel unit 211 is applied when the imaging unit 20 is started. Can be prevented.

  Thereafter, as shown in FIGS. 3 and 4, the first inverter circuit 2261 compares the magnitude of the voltage level input to the input terminal 221 with the threshold LT1, and if it is equal to or higher than the threshold LT1, A control signal indicating that the magnitude of the input voltage level is greater than or equal to threshold LT1 is output to second inverter circuit 2262. In this case, as illustrated in FIGS. 3 and 4, the transistor 2271 receives an off signal from the second inverter circuit 2262, so that the transistor 2271 is turned off and current is stopped. Accordingly, the transistor 224 outputs the imaging signal input from the input terminal 221 to the output terminal 223.

  According to the first embodiment described above, since the current generation unit 227 controls the current value based on the control signal input from the monitoring unit 226, the power supply voltage that exceeds the rated operation range of the pixel unit 211. Application of VDD can be prevented.

  According to the first embodiment, the monitoring unit 226 compares the voltage level of the input terminal 221 with the reference level, and outputs the comparison result to the current generation unit 227 as a control signal. It is possible to prevent the power supply voltage VDD exceeding the rated operation range 211 from being applied.

  Further, according to the first embodiment, when the first inverter circuit 2261 has a voltage level magnitude of the input terminal 221 less than a reference level magnitude that is a circuit threshold value of the first inverter circuit 2261, the control signal Is output to the gate terminal of the transistor 2271, a current determined by the resistance value of the transistor 2271 and the resistance value of the resistor 2272 is applied, so that the power supply voltage VDD exceeding the rated operation range of the pixel portion 211 is applied. Can be prevented.

  Further, according to the first embodiment, since the first chip 21 is stacked on the second chip 22, the diameter of the tip portion 101 can be reduced.

  Further, according to the first embodiment, when the imaging unit 20 is started up, the monitoring unit 226 compares the magnitude of the voltage level of the input terminal 221 with the magnitude of the reference level, and the current generation unit 227 uses the comparison result as a control signal. Therefore, it is possible to prevent application of the power supply voltage VDD exceeding the rated operation range of the pixel unit 211 when the imaging unit 20 is started.

(Embodiment 2)
Next, a second embodiment of the present disclosure will be described. The endoscope system according to the second embodiment of the present disclosure is different in configuration from the signal processing unit 222 of the second chip 22 in the endoscope system 1 according to the first embodiment described above. In the following, the configuration of the endoscope system according to the second embodiment will be described. In addition, the same code | symbol is attached | subjected to the structure same as the endoscope system 1 which concerns on Embodiment 1 mentioned above, and detailed description is abbreviate | omitted.

[Functional configuration of main part of endoscope system]
FIG. 5 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the second embodiment of the present disclosure. An endoscope system 1A shown in FIG. 5 includes an endoscope 2A instead of the endoscope 2 according to the first embodiment described above. The endoscope 2A includes an imaging unit 20A instead of the imaging unit 20 according to the first embodiment described above. Furthermore, the imaging unit 20A includes a second chip 22A instead of the second chip 22 according to the first embodiment described above. Furthermore, the second chip 22A includes a signal processing unit 222A instead of the signal processing unit 222 described above. In addition, the signal processing unit 222A includes a monitoring unit 226A and a current generation unit 227A instead of the monitoring unit 226 and the current generation unit 227 according to Embodiment 1 described above.

  The monitoring unit 226 </ b> A outputs a control signal for controlling the current value flowing through the pixel unit 211 to the current generation unit 227 based on the voltage level of the input terminal 221 and a preset reference level. The monitoring unit 226A is configured using a logic circuit. Specifically, the monitoring unit 226A includes a first inverter circuit 2261A.

  The first inverter circuit 2261A generates a control signal based on the voltage level of the input terminal 221 and a preset reference level, and outputs the control signal to the current generator 227A. Specifically, the first inverter circuit 2261A compares the voltage level of the input terminal 221 with the reference level, and outputs the comparison result to the current generator 227A. Here, the reference level is a circuit threshold value of the first inverter circuit 2261A. For example, the circuit threshold is 1.5 V when the power supply voltage VDD is 3.0 V. That is, the first inverter circuit 2261A compares and determines whether or not the voltage level of the input terminal 221 is equal to or higher than a reference level threshold (for example, 1.5 V), and the comparison result is sent to the current generator 227A. Output.

  The current generation unit 227A changes the value of the current flowing through the pixel unit 211 based on the control signal output from the monitoring unit 226A. The current generator 227A includes a transistor 2271A and a resistor 2272A having a predetermined resistance value.

  The transistor 2271A is configured using an NMOS transistor. The transistor 2271A has a drain terminal connected to the power supply voltage VDD via a resistor 2272A, a source terminal connected to the ground GND, and a gate terminal connected to the first inverter circuit 2261A. The transistor 2271A is turned on when the control signal of the comparison result determined by the first inverter circuit 2261 that the voltage level of the input terminal 221 is less than the threshold value, and the resistance value of the transistor 2271A and the resistance value of the resistor 2272A are The current determined by is energized. On the other hand, the transistor 2271A is turned off when the first inverter circuit 2261 receives a control signal as a comparison result determined that the voltage level of the input terminal 221 is equal to or higher than the threshold, and the current determined by the resistor 2272A. Stops.

  In the signal processing unit 222A configured in this manner, the transistor 2271A is turned on and the current determined by the resistor 2272A is energized when the imaging unit 20A is activated at the same timing as in the first embodiment. It is possible to prevent the supply voltage VDD exceeding the rated operation range of the unit 211 from being applied.

  According to the second embodiment described above, since the current generation unit 227A changes the current value based on the control signal input from the monitoring unit 226A, the rated operation range of the pixel unit 211 when the imaging unit 20A is activated. It is possible to prevent the supply voltage VDD exceeding the inside from being applied. Furthermore, according to the second embodiment, the same effect as in the first embodiment described above is obtained.

(Embodiment 3)
Next, a third embodiment of the present disclosure will be described. The endoscope system according to the third embodiment of the present disclosure is different in configuration from the signal processing unit 222 of the second chip 22 in the endoscope system 1 according to the first embodiment described above. Hereinafter, the configuration of the endoscope system according to the third embodiment will be described. In addition, the same code | symbol is attached | subjected to the structure same as the endoscope system 1 which concerns on Embodiment 1 mentioned above, and detailed description is abbreviate | omitted.

[Functional configuration of main part of endoscope system]
FIG. 6 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the third embodiment of the present disclosure. An endoscope system 1B shown in FIG. 6 includes an endoscope 2B instead of the endoscope 2 according to the first embodiment described above. The endoscope 2B includes an imaging unit 20B instead of the imaging unit 20 according to the first embodiment described above. Furthermore, the imaging unit 20B includes a second chip 22B instead of the second chip 22 according to the first embodiment described above. Furthermore, the second chip 22B includes a signal processing unit 222B instead of the signal processing unit 222 described above. In addition, the signal processing unit 222B includes a monitoring unit 226B and a current generation unit 227B instead of the monitoring unit 226 and the current generation unit 227 according to Embodiment 1 described above.

  The monitoring unit 226B outputs a control signal for controlling the current value to the current generation unit 227B based on the voltage level of the input terminal 221 and a preset reference level. The monitoring unit 226 </ b> B includes a first inverter circuit 2261 and a second inverter circuit 2262.

  The current generation unit 227B changes the value of the current flowing through the pixel unit 211 based on the control signal output from the monitoring unit 226B. The current generator 227B includes a transistor 2271B and a resistor 2272B having a predetermined resistance value.

  The transistor 2271B is configured using a PMOS transistor. In the transistor 2271B, the power supply voltage VDD is connected to the source terminal, the resistor 2272B and the resistor 225 are connected to the drain terminal, and the second inverter circuit 2262 is connected to the gate terminal. The transistor 2271B is turned on based on the on signal output from the second inverter circuit 2262, and a current determined by the resistance value of the resistor 2272B and the resistance value of the resistor 225 is supplied. On the other hand, the transistor 2271B is turned off based on the off signal output from the second inverter circuit 2262, and the current determined by the resistor 2272B and the resistor 225 is stopped.

  In the signal processing unit 222B configured as described above, the transistor 2271B is turned on when the imaging unit 20B is activated at the same timing as in the first embodiment, and is determined by the resistance value of the resistor 2272B and the resistance value of the resistor 225. Therefore, it is possible to prevent the power supply voltage VDD exceeding the rated operation range of the pixel portion 211 from being applied.

  According to the third embodiment described above, since the current generation unit 227B changes the current value based on the control signal input from the monitoring unit 226B, the range of the rated operation of the pixel unit 211 when the imaging unit 20B is activated. It is possible to prevent the supply voltage VDD exceeding the inside from being applied. Furthermore, the third embodiment has the same effect as the first embodiment described above.

(Embodiment 4)
Next, a fourth embodiment of the present disclosure will be described. The endoscope system according to the fourth embodiment of the present disclosure is different in configuration from the signal processing unit 222 of the second chip 22 in the endoscope system 1 according to the first embodiment described above. Hereinafter, the configuration of the endoscope system according to the fourth embodiment will be described. In addition, the same code | symbol is attached | subjected to the structure same as the endoscope system 1 which concerns on Embodiment 1 mentioned above, and detailed description is abbreviate | omitted.

[Functional configuration of main part of endoscope system]
FIG. 7 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the fourth embodiment of the present disclosure. An endoscope system 1C illustrated in FIG. 7 includes an endoscope 2C instead of the endoscope 2 according to the first embodiment described above. The endoscope 2C includes an imaging unit 20C instead of the imaging unit 20 according to the first embodiment described above. Furthermore, the imaging unit 20C includes a second chip 22C instead of the second chip 22 according to the first embodiment described above. Furthermore, the second chip 22C includes a signal processing unit 222C instead of the signal processing unit 222 described above. In addition, the signal processing unit 222C includes a monitoring unit 226C and a current generation unit 227C instead of the monitoring unit 226 and the current generation unit 227 according to Embodiment 1 described above.

  The monitoring unit 226C outputs a control signal for controlling the current value to the current generation unit 227C based on the voltage level of the input terminal 221 and a preset reference level. The monitoring unit 226 </ b> C includes a first inverter circuit 2261, a second inverter circuit 2262, and a switch unit 2263.

  The switch unit 2263 is configured using a PMOS transistor and an NMOS transistor. One of the switch units 2263 is connected to the output destination of the first inverter circuit 2261, and the other is connected to the output destination of the second inverter circuit 2262. When the control signal of the comparison result indicating that the magnitude of the voltage level of the input terminal 221 is less than the threshold value is input from the first inverter circuit 2261, the switch unit 2263 is turned off, and the input terminal 221 and the transistor 224 And is electrically cut off. On the other hand, when the control signal of the comparison result indicating that the voltage level of the input terminal 221 is equal to or higher than the threshold value is input from the first inverter circuit 2261C, the switch unit 2263 is turned on, The transistor 224 is electrically connected.

  The transistor 2271C is configured using a PMOS transistor. In the transistor 2271C, the power supply voltage VDD is connected to the source terminal, the drain terminal is connected to the gate terminal of the transistor 224, and the control signal from the second inverter circuit 2262 is input to the gate terminal. The transistor 2271C is turned on based on an on signal output from the second inverter circuit 2262, and a current corresponding to the power supply voltage VDD is supplied. On the other hand, the transistor 2271C is turned off based on the off signal output from the second inverter circuit 2262 and no current flows.

[Operation processing of imaging unit]
Next, an operation process of the imaging unit 20C will be described. FIG. 8 is a diagram illustrating a timing chart of operation processing of the imaging unit 20C. FIG. 9 is a diagram in which the power supply voltage VDD, the input terminal 221, the gate of the transistor 224, and the circuit threshold value of the first inverter circuit 2261 are all summarized on the same voltage axis. 8 and 9, the horizontal axis indicates time, and the vertical axis indicates voltage (V). In FIG. 8, (a) shows the timing of the synchronization signal, (b) shows the timing of the clock signal, (c) shows the rising timing of the power supply voltage VDD, and (d) shows the second inverter circuit. The output timing of 2262 is shown, (e) shows the output timing of the first inverter circuit 2261, (f) shows the output change of the input terminal 221, and (g) shows the output change of the gate of the transistor 224. Further, in FIGS. 8 and 9, a curve L21 indicates a change in the power supply voltage VDD, a broken line L22 indicates an output change of the second inverter circuit 2262, a broken line L23 indicates an output change of the first inverter circuit 2261, A broken line L24 indicates an output change of the input terminal 221 and a curve L25 indicates an output change of the gate of the transistor 224. Further, in FIG. 9, a curve L11 indicates a change in the conventional power supply voltage VDD, and a straight line LT1 indicates a circuit threshold value of the first inverter circuit 2261.

  As shown in FIGS. 8 and 9, first, when the pixel unit 211 is activated, the first inverter circuit 2261 has a voltage level input to the input terminal 221 and a threshold LT1 (for example, 1) as a reference level. .5V), and if it is smaller than the threshold LT1, a control signal indicating that the magnitude of the voltage level input to the input terminal 221 is smaller than the threshold LT1 is passed through the second inverter circuit 2262 and the gate terminal of the transistor 2271C. Output to. In this case, as illustrated in FIGS. 8 and 9, the transistor 2271 </ b> C is turned on and outputs the power supply voltage VDD to the gate terminal of the transistor 224. As a result, as shown by the curve L11 and the curve L21 in FIG. 9, according to the fourth embodiment, the power supply voltage VDD exceeding the rated operation range of the pixel unit 211 is applied when the imaging unit 20C is activated. Can be prevented.

  After that, as shown in FIGS. 8 and 9, the first inverter circuit 2261 compares the magnitude of the voltage level input to the input terminal 221 with a threshold LT1 (for example, 1.5 V), and the first inverter circuit 2261 is equal to or higher than the threshold LT1. In this case, a control signal indicating that the magnitude of the voltage level input to the input terminal 221 is greater than or equal to the threshold LT1 is output to the gate terminal of the transistor 2271C via the second inverter circuit 2262. In this case, as illustrated in FIGS. 8 and 9, the transistor 2271C is turned off. Accordingly, the transistor 224 outputs an output signal corresponding to the imaging signal input from the input terminal 221 to the output terminal 223.

  According to the fourth embodiment described above, since the current generation unit 227C changes the current value based on the control signal input from the monitoring unit 226C, the range of the rated operation of the pixel unit 211 when the imaging unit 20C is activated. It is possible to prevent the supply voltage VDD exceeding the inside from being applied. Furthermore, the fourth embodiment has the same effect as the first embodiment described above.

(Embodiment 5)
Next, a fifth embodiment of the present disclosure will be described. The endoscope system according to the fifth embodiment of the present disclosure is different in configuration from the signal processing unit 222C of the second chip 22C in the endoscope system 1C according to the fourth embodiment described above. Hereinafter, the configuration of the endoscope system according to the fifth embodiment will be described. In addition, the same code | symbol is attached | subjected to the structure same as the endoscope system 1C which concerns on Embodiment 4 mentioned above, and detailed description is abbreviate | omitted.

[Functional configuration of main part of endoscope system]
FIG. 10 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the fifth embodiment of the present disclosure. An endoscope system 1D shown in FIG. 10 includes an endoscope 2D instead of the endoscope 2C according to the fourth embodiment described above. The endoscope 2D includes an imaging unit 20D instead of the imaging unit 20C according to the third embodiment described above. Furthermore, the imaging unit 20D includes a second chip 22D instead of the second chip 22C according to the fourth embodiment described above. Furthermore, the second chip 22D includes a signal processing unit 222D instead of the signal processing unit 222C according to Embodiment 4 described above. The signal processing unit 222D includes a current generation unit 227D instead of the current generation unit 227C according to the fourth embodiment described above.

  The current generation unit 227D further includes a transistor 2273D and resistors 2272D and 2274D having predetermined resistance values in addition to the configuration of the current generation unit 227C according to the fourth embodiment described above.

  The transistor 2271C has a drain terminal connected to the resistor 2272D connected to the gate terminal of the transistor 224, a source terminal connected to the power supply voltage VDD, and a gate terminal connected to the second inverter circuit 2262.

  The transistor 2273D is formed using an NMOS transistor. The transistor 2273D has a drain terminal connected to the resistor 2274D connected to the gate terminal of the transistor 224, a source terminal connected to the ground GND, and a gate terminal connected to the first inverter circuit 2261.

  The transistors 2271C and 2273D are turned on when the first inverter circuit 2261 determines that the voltage level of the input terminal 221 is lower than 1.5V. Accordingly, the voltage divided by the resistors 2272D and 2274D is output to the gate terminal of the transistor 224.

[Operation processing of imaging unit]
Next, an operation process of the imaging unit 20D will be described. FIG. 11 is a diagram illustrating a timing chart of operation processing of the imaging unit 20D. FIG. 12 is a diagram in which the power supply voltage VDD, the input terminal 221, the gate of the transistor 224, and the circuit threshold value of the first inverter circuit 2261 are all summarized on the same voltage axis. 11 and 12, the horizontal axis represents time, and the vertical axis represents voltage (V). In FIG. 11, (a) shows the timing of the synchronization signal, (b) shows the timing of the clock signal, (c) shows the rising timing of the power supply voltage VDD, and (d) shows the second inverter circuit. The output timing of 2262 is shown, (e) shows the output timing of the first inverter circuit 2261, (f) shows the output change of the input terminal 221, and (g) shows the output change of the gate of the transistor 224. Further, in FIGS. 11 and 12, a curve L31 indicates a change in the power supply voltage VDD, a broken line L32 indicates an output change of the second inverter circuit 2262, a broken line L33 indicates an output change of the first inverter circuit 2261, A broken line L34 indicates an output change of the input terminal 221 and a curve L35 indicates an output change of the gate of the transistor 224. Further, in FIG. 12, a curve L11 indicates a change in the conventional power supply voltage VDD, and a straight line LT1 indicates a circuit threshold value of the first inverter circuit 2261.

  As shown in FIGS. 11 and 12, first, when the imaging unit 20D is activated, the first inverter circuit 2261 has a voltage level input to the input terminal 221 and a threshold LT1 (for example, 1) that is a reference level. .5V), and if it is smaller than the threshold LT1, a control signal indicating that the magnitude of the voltage level input to the input terminal 221 is smaller than the threshold LT1 is passed through the second inverter circuit 2262 and the gate terminal of the transistor 2271C. And a control signal is output to the transistor 2273D. In this case, as illustrated in FIGS. 11 and 12, the transistor 224 is turned on, and the voltage divided by the resistors 2272D and 2274D is input to the gate terminal of the transistor 224. Thereby, as shown by a curve L11 and a curve L31 in FIG. 12, according to the fifth embodiment, the power supply voltage VDD exceeding the rated operation range of the pixel unit 211 is applied when the imaging unit 20D is activated. Can be prevented.

  Thereafter, as shown in FIGS. 11 and 12, the first inverter circuit 2261 compares the magnitude of the voltage level input to the input terminal 221 with a threshold LT1 (for example, 1.5 V), and the first inverter circuit 2261 has a threshold LT1 or higher. In this case, a control signal indicating that the magnitude of the voltage level input to the input terminal 221 is greater than or equal to the threshold LT1 is output to the gate terminal of the transistor 2271C via the second inverter circuit 2262, and the control signal is output to the transistor 2273D. Output to. In this case, the transistor 2271C and the transistor 2273D are turned off. Accordingly, the transistor 224 outputs an output signal corresponding to the imaging signal input from the input terminal 221 to the output terminal 223.

  According to the fifth embodiment described above, since the current generation unit 227D changes the current value based on the control signal input from the monitoring unit 226C, the range of the rated operation of the pixel unit 211 when the imaging unit 20D is activated. It is possible to prevent the supply voltage VDD exceeding the inside from being applied. Furthermore, the fifth embodiment has the same effect as the first embodiment described above.

(Embodiment 6)
Next, a sixth embodiment of the present disclosure will be described. The endoscope system according to the sixth embodiment of the present disclosure is different in configuration from the signal processing unit 222 of the second chip 22 in the endoscope system 1 according to the first embodiment described above. Hereinafter, the configuration of the endoscope system according to the sixth embodiment will be described. In addition, the same code | symbol is attached | subjected to the structure same as the endoscope system 1 which concerns on Embodiment 1 mentioned above, and detailed description is abbreviate | omitted.

[Functional configuration of main part of endoscope system]
FIG. 13 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the sixth embodiment of the present disclosure. An endoscope system 1E shown in FIG. 13 includes an endoscope 2E instead of the endoscope 2 according to the first embodiment described above. The endoscope 2E includes an imaging unit 20E instead of the imaging unit 20 according to the first embodiment described above. Furthermore, the imaging unit 20E includes a second chip 22E instead of the second chip 22 according to the first embodiment described above. Furthermore, the second chip 22E includes a signal processing unit 222E instead of the signal processing unit 222 described above. The signal processing unit 222E includes a monitoring unit 226E instead of the monitoring unit 226 of the signal processing unit 222 according to Embodiment 1 described above.

  The monitoring unit 226E includes a resistor 2264 having a predetermined resistance value and a resistor 2265 having a predetermined resistance value provided between the power supply voltage VDD and the ground GND, and a comparison unit 2266. In the sixth embodiment, the resistor 2264 and the resistor 2265 function as a reference level generation unit that generates the reference voltage VREF.

  The comparison unit 2266 generates a control signal based on the magnitude of the reference voltage VREF divided by the resistors 2264 and 2265 and the magnitude of the voltage level input to the input terminal 221, and the control signal is output to the transistor 2271. Output to. The comparison unit 2266 is configured using a comparator circuit. Specifically, the comparison unit 2266 compares the magnitude of the voltage level input to the input terminal 221 with the magnitude of the reference voltage VREF when the imaging unit 20E is activated, and is less than the magnitude of the reference voltage VREF. In this case, an ON signal is output to the transistor 2271. Accordingly, the transistor 2271 is turned on, and a current determined by the resistor 2272 is supplied. Thus, according to the sixth embodiment, it is possible to prevent the power supply voltage VDD exceeding the rated operation range of the pixel unit 211 from being applied when the imaging unit 20E is activated.

  After that, the comparison unit 2266 compares the magnitude of the voltage level input to the input terminal 221 with the magnitude of the reference voltage VREF, and outputs an off signal to the transistor 2271 when the magnitude is equal to or greater than the magnitude of the reference voltage VREF. Accordingly, the transistor 2271 is turned off, and the current determined by the resistor 2272 is stopped.

  According to the sixth embodiment described above, since the current generation unit 227 changes the current value based on the control signal input from the monitoring unit 226E, the range of the rated operation of the pixel unit 211 when the imaging unit 20E is activated. It is possible to prevent the supply voltage VDD exceeding the inside from being applied. Furthermore, according to the sixth embodiment, there are the same effects as in the first embodiment.

(Embodiment 7)
Next, a seventh embodiment of the present disclosure will be described. The endoscope system according to the seventh embodiment of the present disclosure is different in configuration from the second chip 22 in the endoscope system 1 according to the first embodiment described above. Specifically, the endoscope system according to the seventh embodiment of the present disclosure transmits an imaging signal using a differential signal. Below, the same code | symbol is attached | subjected to the structure same as the endoscope system 1 which concerns on Embodiment 7, and detailed description is abbreviate | omitted.

[Functional configuration of main part of endoscope system]
FIG. 14 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the seventh embodiment of the present disclosure. An endoscope system 1F shown in FIG. 14 includes an endoscope 2F instead of the endoscope 2 according to the first embodiment described above. In addition, the endoscope 2F includes an imaging unit 20F and a connector unit 5F instead of the imaging unit 20 and the connector unit 5 according to Embodiment 1 described above.

  First, the imaging unit 20F will be described. The imaging unit 20F includes a second chip 22F instead of the second chip 22 described above. Furthermore, the second chip 22F includes a signal processing unit 222F, a monitoring unit 226F, and a current generation unit 227.

  The signal processing unit 222F includes an output unit 235. The output unit 235 outputs the imaging signal input from the input terminal 221 using the two signal lines 34 and 35 and the output terminals 236 and 237 in the transmission cable 3F to the connector unit 5F by LVDS (Low Voltage Differential Signaling). . In the seventh embodiment, the output unit 235 outputs the imaging signal to the two signal lines 34 and 35 by LVDS. However, the present invention is not limited to this, and the signal is output superimposed on other signal lines. Or may be output to the connector unit 5F by other methods.

  The monitoring unit 226F includes a resistor 2264 having a predetermined resistance value and a resistor 2265 having a predetermined resistance value provided between the power supply voltage VDD and the ground GND, and a comparison unit 2266F. In the seventh embodiment, the reference level generation unit includes a band gap reference circuit, and generates a reference voltage that does not depend on the power supply voltage VDD.

  The comparison unit 2266F generates a control signal based on the voltage level obtained by dividing the power supply voltage VDD by the resistor 2264 and the resistor 2265 and the reference voltage VREF, and outputs the control signal to the transistor 2271. . The comparison unit 2266F is configured using a comparator circuit. Specifically, the comparison unit 2266F compares the magnitude of the voltage level divided by the resistors 2264 and 2265 with the magnitude of the reference voltage VREF when the imaging unit 20F is activated, and the magnitude of the reference voltage VREF. If it is less than that, an ON signal is output to the transistor 2271. Accordingly, the transistor 2271 is turned on, and a current determined by the resistor 2272 is supplied. Thus, according to the seventh embodiment, it is possible to prevent the power supply voltage VDD exceeding the rated operation range of the pixel unit 211 from being applied when the imaging unit 20F is activated.

  After that, the comparison unit 2266F compares the magnitude of the voltage level divided by the resistors 2264 and 2265 with the magnitude of the reference voltage VREF. If the voltage level is equal to or larger than the magnitude of the reference voltage VREF, the comparator 2266F outputs an off signal to the transistor 2271. Is output. Accordingly, the transistor 2271 is turned off, and the current determined by the resistor 2272 is stopped.

  Next, the connector part 5F will be described. The connector unit 5F includes a circuit board 51F instead of the circuit board 51 according to the first embodiment described above. Further, the circuit board 51F includes a receiving circuit 511F and a processing circuit 512F instead of the receiving circuit 511 and the processing circuit 512 described above.

  The reception circuit 511 </ b> F includes input terminals 513 and 514 and a reception unit 515. The receiving unit 515 receives the imaging signal transmitted by the LVDS from the signal lines 34 and 35 of the transmission cable 3F via the input terminals 513 and 514, and outputs it to the imaging signal processing unit 5122F.

  The imaging signal processing unit 5122F performs predetermined signal processing such as vertical line removal and noise removal on the digital imaging signal input from the reception unit 515, and outputs the result to the processor 6.

  According to the seventh embodiment described above, since the current generation unit 227 changes the current value based on the control signal input from the monitoring unit 226F, the rated operation of the pixel unit 211 is performed when the imaging unit 20F is activated. It is possible to prevent the supply voltage VDD exceeding the range from being applied. Furthermore, according to the seventh embodiment, there are the same effects as in the first embodiment.

(Other embodiments)
Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the first to seventh embodiments. For example, some components may be deleted from all the components described in the first to seventh embodiments. Furthermore, you may combine suitably the component demonstrated in Embodiment 1-7 mentioned above.

  In the first to seventh embodiments, the control device and the light source device are separate, but may be integrally formed.

  In Embodiments 1 to 7, the endoscope system is used. However, for example, a capsule endoscope, a video microscope for imaging a subject, a mobile phone having an imaging function, and a tablet terminal having an imaging function Even can be applied.

  In the first to seventh embodiments, the endoscope system includes a flexible endoscope. However, the endoscope system includes a rigid endoscope, and the endoscope includes an industrial endoscope. Even an endoscope system can be applied.

  In the first to seventh embodiments, the endoscope system includes an endoscope that is inserted into a subject. However, for example, an endoscope system that includes a rigid endoscope, and a sinus endoscope Also, the present invention can be applied to an endoscope system such as an electric knife and an inspection probe.

  In the first to seventh embodiments, the “unit” described above can be read as “means” or “circuit”. For example, the control unit can be read as control means or a control circuit.

  In the first to seventh embodiments, the signal is transmitted from the endoscope to the processor via the transmission cable. However, the signal need not be wired, for example, and may be wireless. In this case, an imaging signal or the like may be transmitted from the endoscope to the processor according to a predetermined wireless communication standard (for example, Wi-Fi (registered trademark) or Bluetooth (registered trademark)). Of course, wireless communication may be performed according to other wireless communication standards.

  In the description of the time chart in the present specification, the context of the processing between steps is clearly shown using expressions such as “first”, “after”, “follow”, etc., in order to implement the present invention. The order of the processes required for the above is not uniquely determined by their expressions. That is, the order of processing in the time chart described in this specification can be changed within a consistent range. Further, the program is not limited to such a simple branch process, and more determination items may be comprehensively determined and branched.

  As described above, some of the embodiments of the present application have been described in detail with reference to the drawings. However, these are merely examples, and various embodiments can be made based on the knowledge of those skilled in the art including the aspects described in the disclosure section of the present invention. The present invention can be implemented in other forms that have been modified or improved.

1, 1A, 1B, 1C, 1D, 1E, 1F Endoscope system 2, 2A, 2B, 2C, 2D, 2E, 2F Endoscope 3, 3F Transmission cable 4 Operation part 5, 5F Connector part 6 Processor 7 Display Device 8 Light source device 20, 20A, 20B, 20C, 20D, 20E, 20F Imaging unit 21 First chip 22, 22A, 22B, 22C, 22D, 22E, 22F Second chip 31-35 Signal line 51, 51F Circuit board 61 Power supply unit 62 Image signal processing unit 63 Drive signal generation unit 64 Recording unit 65 Input unit 66 Control unit 100 Insertion unit 101 Tip unit 102 Base end 211 Pixel unit 221,513,514 Input terminal 222 Signal processing unit 222A, 222B, 222C, 222D, 222E, 222F Signal processing units 223, 236, 237 Output terminals 224, 2234D, 271, 2271A, 2271B, 2271C, 2273D Transistors 225, 2264, 2265, 2272, 2272A, 2272B, 2272D, 2274D Resistors 226, 226A, 226B, 226C, 226D, 226E, 226F Monitoring units 227, 227A, 227B, 227C, 227D Current generation unit 235 Output unit 239, 2266, 2266F Comparison unit 511, 511F Reception circuit 512, 512F Processing circuit 515 Reception unit 2261, 2261A, 2261C First inverter circuit 2262 Second inverter circuit 2263 Switch unit 5111 AC termination resistor 5112 DC termination resistor 5113 DC cut capacitor 5121 AFE unit 5122, 5122F Imaging signal processing unit

Claims (15)

A pixel unit that is arranged in a two-dimensional matrix and has a plurality of pixels that generate and output an imaging signal corresponding to the amount of incident light;
A signal processing unit that outputs the output signal corresponding to the input signal to the outside, using the imaging signal output from the pixel unit as an input signal;
A monitoring unit that outputs a control signal for controlling a current value based on the magnitude of the voltage level of the predetermined terminal and the magnitude of a preset reference level;
A current generator that generates a predetermined current according to the control signal output by the monitoring unit;
An image pickup device comprising: The imaging device according to claim 1, wherein the monitoring unit compares the voltage level with the reference level and outputs the comparison result as the control signal. The monitoring unit
A reference level generator for generating the reference level;
A comparison unit that compares the magnitude of the voltage level with the magnitude of the reference level and outputs the comparison result as the control signal;
The image pickup device according to claim 1, wherein the image pickup device includes: The current generation unit includes a switch circuit having a transistor and a resistor having a predetermined value, and generates a current based on a resistance value of the resistor when the switch circuit is turned on by the control signal. The imaging device according to 3. The current generation unit includes a switch circuit having a transistor and a resistor having a predetermined value, and the signal processing unit generates a current based on the resistance value of the resistor when the switch circuit is turned on by the control signal. The imaging device according to claim 3, wherein The comparison unit has at least a logic circuit;
The reference level is a circuit threshold of the logic circuit;
The image pickup device according to claim 3, wherein the logic circuit compares the magnitude of the input voltage level with the magnitude of the reference level. The comparison unit has at least an inverter circuit,
The reference level is a circuit threshold value of the inverter circuit,
The image pickup device according to claim 3, wherein the inverter circuit compares the magnitude of the input voltage level with the magnitude of the reference level. The reference level generation unit has a resistor provided between a power supply voltage and ground,
The imaging device according to claim 3, wherein the reference level is a voltage level obtained by resistance-dividing by the resistor. The reference level generation unit has a band gap reference circuit,
The imaging device according to claim 3, wherein the reference level is a voltage level generated by the band gap reference circuit. The imaging device according to claim 8, wherein the comparison unit includes a comparator circuit that compares the magnitude of the voltage level with the magnitude of the reference level. A first chip in which the plurality of pixels are arranged;
A second chip in which the signal processing unit, the monitoring unit, and the current generation unit are arranged;
With
The image sensor according to claim 1, wherein the first chip is stacked on the second chip. The image sensor according to claim 11, wherein the monitoring unit outputs the control signal when the image sensor is activated. An imaging apparatus comprising the imaging device according to claim 1. An imaging device according to claim 13,
An insertion section that can be inserted into the subject;
With
The endoscope is characterized in that the insertion section is formed by disposing the imaging device at a distal end portion. The endoscope according to claim 14,
A processing device that performs image processing on the imaging signal to generate an image signal;
An endoscope system comprising:

Images