JP6221930B2 - Switching element drive circuit - Google Patents

Description

  The present invention includes a series connection body of a high-side switching element and a low-side switching element, and is applied to a power conversion circuit in which the series connection body is connected in parallel to a DC power supply. Both the high-side switching element and the low-side switching element The present invention relates to a switching element driving circuit for setting a dead time for avoiding the ON state of the switching element.

  2. Description of the Related Art Conventionally, as can be seen, for example, in Patent Document 1 below, a control device that is applied to an inverter including a series connection body of a high side switching element and a low side switching element is known. Specifically, this control device corrects the dead time based on the turn-off delay time characteristics of the switching element stored in advance, the temperature of the switching element, the current flowing through the switching element, and the like. Based on the corrected dead time, the control device generates a PWM control signal for turning on / off the high-side switching element and a PWM control signal for turning on / off the low-side switching element, and outputs them to the inverter. The inverter applies an AC voltage to a motor electrically connected to the inverter by turning on and off the high-side and low-side switching elements based on each input PWM control signal. According to the above configuration capable of correcting the dead time, the dead time can be shortened.

JP 2010-142074 A

  Here, the time from when the PWM control signals for the high side and the low side are output from the control device to when they are transmitted to the inverter may vary. As a cause of the variation, for example, individual differences in the system including the control device and the inverter, and the surrounding environment where the system is installed can be cited. If the transmission time varies, even if the control device generates the PWM control signal based on the corrected dead time, the actual dead time varies with respect to the assumed dead time. When the actual dead time becomes 0 due to variations in the dead time, the high-side and low-side switching elements are turned on, and a short-circuit current flows through the switching elements. In order to avoid such a situation, it is conceivable to increase the dead time set in the control device. However, in this case, the power conversion function of the inverter is lowered.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a switching element drive circuit capable of reducing dead time.

  In order to achieve the above-mentioned object, the present invention comprises a series connection body of a high-side switching element (SCp) and a low-side switching element (SCn), and the series connection body is connected in parallel to a DC power source (12b). A switching element driving circuit applied to the circuit (12) and comprising a single integrated circuit (20), wherein the integrated circuit receives an external driving signal for driving the high-side switching element and the low-side switching element. An input terminal (Tin) for input, a dead time calculation unit (21) for calculating a dead time for avoiding both the high-side switching element and the low-side switching element being turned on, and the input The external drive signal input via the terminal and the data calculated by the dead time calculator. A drive signal for realizing the dead time based on a dead time, a high side drive signal for turning on and off the high side switching element, and a drive signal for realizing the dead time, the low side A signal generation unit (21) that generates a low-side drive signal for turning on and off the switching element, and the high-side switching element is turned on and off based on the high-side drive signal, and the low-side switching element is turned on and off based on the low-side drive signal And a drive unit (23H, 23L) to be operated.

  In the above invention, a single integrated circuit itself has a dead time calculation unit and a signal generation unit. Therefore, unlike a configuration in which a drive signal for turning on / off each of the high-side and low-side switching elements is generated by an external device, and the drive signal generated by the external device is input to the drive unit of the integrated circuit, Variations in dead time due to variations in signal transmission time to the integrated circuit can be eliminated. As a result, variations in actual dead time can be reduced, and as a result, dead time can be shortened.

The lineblock diagram of the motor control system concerning a 1st embodiment. The block diagram of a drive circuit. The figure which shows the production | generation method of dead time. The figure which shows the fluctuation | variation of the output voltage of a boost converter. The figure which shows the delay time and rise time at the time of turn-on. The figure which shows the delay time and fall time at the time of turn-off. The flowchart which shows the procedure of a dead time calculation process. The figure which shows the relationship between the collector current of the high side side, element temperature, and delay time. The figure which shows the relationship between the collector current and element temperature of a low side, and delay time. The figure for demonstrating the calculation method of dead time. The figure for demonstrating the calculation method of dead time. The flowchart which shows the procedure of an electric current distribution direction discrimination | determination process. The flowchart which shows the procedure of an electric current distribution direction discrimination | determination process. The flowchart which shows the procedure of a dead time compensation process. The flowchart which shows the procedure of the electric current distribution direction discrimination | determination process concerning 2nd Embodiment. The flowchart which shows the procedure of an electric current distribution direction discrimination | determination process.

(First embodiment)
Hereinafter, a first embodiment in which a drive circuit of a switching element according to the present invention is applied to a vehicle including a rotating machine as an in-vehicle main machine will be described with reference to the drawings.

  As shown in FIG. 1, the in-vehicle motor control system includes a motor generator 10, an inverter 11, a boost converter 12, and a control device 13 that controls the motor generator 10. The motor generator 10 is a multi-phase rotating machine (three-phase rotating machine) as an in-vehicle main machine, and is connected to driving wheels (not shown). Motor generator 10 is connected to battery 14 via inverter 11 and boost converter 12. The output voltage of the battery 14 is, for example, 100 V or more. As the battery 14, for example, a lithium ion storage battery or a nickel hydride storage battery can be used. Moreover, as the motor generator 10, a synchronous machine (permanent magnet synchronous machine) can be used, for example.

  Boost converter 12 includes a reactor 12a, a capacitor 12b as a “DC power supply”, a boosting high-side switch SCp, and a boosting low-side switch SCn. Specifically, the boosting high-side switch SCp and the boosting low-side switch SCn are connected in series. A capacitor 12b is connected in parallel to this series connection body. A series connection body of the reactor 12a and the battery 14 is connected in parallel to the boosting low-side switch SCn. In the present embodiment, voltage controlled semiconductor switching elements are used as the switches SCp and SCn, and specifically, IGBTs are used. The boosting high-side switch SCp is connected with a boosting high-side diode DCp in antiparallel, and the boosting low-side switch SCn is connected with a boosting low-side diode DCn in antiparallel.

  The inverter 11 includes three sets of serially connected bodies of a ¥ phase high side switch S ¥ p (¥ = U, V, W) and a ¥ phase low side switch S ¥ n. The $ phase of the motor generator 10 is connected to the connection point of the $ phase switches S \ p and S \ n. In the present embodiment, a voltage-controlled semiconductor switching element is used as each switch, and specifically, an IGBT is used. The $ -phase high-side switch S \ p is connected with a \ -phase high-side diode D \ p in antiparallel, and the \ -phase low-side switch S \ n is connected with a \ -phase low-side diode D \ n in anti-parallel. Yes.

  The control device 13 is mainly composed of a microcomputer, and operates the inverter 11 and the boost converter 12 to control the control amount (for example, torque) of the motor generator 10 to the command value. First, the operation of boost converter 12 will be described. Control device 13 has a detected value of input voltage sensor 15 that detects an input voltage of boost converter 12 (an output voltage of battery 14), and an output voltage sensor that detects an output voltage of boost converter 12 (a voltage across terminals of capacitor 12b). 16 detection values are captured. The control device 13 uses an external drive signal SigC for controlling the output voltage Vout to the target voltage Vtgt based on the input voltage Vin detected by the input voltage sensor 15 and the output voltage Vout detected by the output voltage sensor 16. The external drive signal SigC having the duty ratio Duty is output to the boost drive circuit DrC. As a result, the boosting high-side switch SCp and the boosting low-side switch SCn are alternately turned on. Here, the duty ratio is the ratio of the on operation time to one cycle (one switching cycle) of the switches SCp and SCn. Here, the higher the target voltage Vtgt, the higher the duty ratio Duty is set. In the operation of boost converter 12, boost high-side switch SCp may be always turned off. In this case, when the boosting low-side switch SCn is turned off, the boosting high-side diode DCp serves as a current flow path.

  Subsequently, the operation of the inverter 11 will be described. Control device 13 outputs drive signal Sig ¥ to ¥ phase drive circuit Dr ¥ to apply an AC voltage to motor generator 10. As a result, the $ -phase high-side switch S \ p and the $ -phase low-side switch S \ n are turned on alternately, and each of the U, V, and W phases of the motor generator 10 has an electrical angle of 120 ° relative to each other. A shifted sinusoidal current flows.

  Next, each drive circuit Dr * (* = C, U, V, W) according to the present embodiment will be described with reference to FIG.

  As shown in the figure, the drive circuit Dr * includes a single drive IC 20 that is a one-chip semiconductor integrated circuit. The drive IC 20 is a so-called HVIC (High Voltage Integrated Circuit) including a signal generation circuit 21, a level shift circuit 22, a high-side drive unit 23H, and a low-side drive unit 23L. Specifically, an external drive signal Sig * that is a PWM signal is input to the signal generation circuit 21 via a single input terminal Tin of the drive IC 20. As shown in FIG. 3, the signal generation circuit 21 generates a high-side drive signal g * p and a low-side drive signal g * n while giving a dead time DT based on the external drive signal Sig *. In the present embodiment, the rising timing of each of the high side drive signal g * p and the low side drive signal g * n is delayed by the dead time DT with respect to the external drive signal Sig *.

  The level shift circuit 22 changes a reference potential of a signal such as the external drive signal Sig * from a low side reference potential that is a reference potential on the low side switch S * n side to a high side reference that is a reference potential on the high side switch S * p side. It is a circuit that converts it into a potential.

  The high side drive unit 23H is a pre-buffer circuit including a high side charge switch 23H1 (P channel MOSFET) and a high side discharge switch 23H2 (N channel MOSFET). Specifically, the first constant voltage power supply 25 is connected to the drain of the high side charge switch 23H1, and the drain of the high side discharge switch 23H2 is connected to the source of the high side charge switch 23H1. The source of the high side discharge switch 23H2 is connected to a high side reference potential terminal THb which is a terminal of the drive IC 20 and is connected to the second terminal (emitter) of the high side switch S ¥ p. In the present embodiment, the potential of the high side reference potential terminal THb is the high side reference potential. The high side drive signal g * p output from the signal generation circuit 21 is supplied to the gates of the high side charge switch 23H1 and the high side discharge switch 23H2 via the level shift circuit 22.

  A high side output terminal THO of the drive IC 20 is connected to a connection point between the high side charge switch 23H1 and the high side discharge switch 23H2. An open / close control terminal (gate) of the high-side switch S * p is connected to the high-side output terminal THO via a high-side gate resistor 26H. The configuration shown in FIG. 2 is not limited to the configuration shown in FIG. 2 in which a common gate resistance is provided in each of the charging path and the discharging path.

  The high side driving unit 23H performs charge / discharge processing of the gate charge based on the input high side driving signal g * p. In the present embodiment, the high side drive signal g * p represents an ON operation command for switching the high side switch S * p to the on state by “H”, and the high side switch S * p is switched to the OFF state by “L”. Indicates an off operation command. For this reason, when the high-side drive signal g * p is set to the on operation command “H”, the high-side charge switch 23H1 is turned on, and the high-side discharge switch 23H2 is turned off. . As a result, the high side switch S * p is switched to the on state. On the other hand, when the high side drive signal g * # is set to the off operation command “L”, the high side charge switch 23H1 is switched to the off operation, and the high side discharge switch 23H2 is switched to the on operation. Done. Accordingly, the high side switch S * p is switched to the off state.

  The low side drive unit 23L is a pre-buffer circuit including a low side charge switch 23L1 (P channel MOSFET) and a low side discharge switch 23L2 (N channel MOSFET). Specifically, the second constant voltage power supply 27 is connected to the drain of the low side charge switch 23L1, and the drain of the low side discharge switch 23L2 is connected to the source of the low side charge switch 23L1. The source of the low-side discharge switch 23L2 is connected to a terminal of the drive IC 20, which is a low-side reference potential terminal TLb connected to the emitter of the low-side switch S ¥ n. In the present embodiment, the potential of the low side reference potential terminal TLb is the low side reference potential. The low side drive signal g * n output from the signal generation circuit 21 is supplied to the gates of the low side charge switch 23L1 and the low side discharge switch 23L2. In the present embodiment, the output voltage Vom (for example, 15 V) of the second constant voltage power supply 27 is the same as the output voltage Vom of the first constant voltage power supply 25.

  A low side output terminal TLO of the drive IC 20 is connected to a connection point between the low side charge switch 23L1 and the low side discharge switch 23L2. The gate of the low side switch S * n is connected to the low side output terminal TLO via the low side gate resistor 26L. The low side drive unit 23L performs a charge / discharge process of the gate charge based on the input low side drive signal g * n. In this embodiment, the operation modes of the low-side drive unit 23L and the high-side drive unit 23H are the same. For this reason, detailed description of the operation mode of the low-side drive unit 23L is omitted.

  The drive IC 20 further includes a high side temperature detection unit 24H and a low side temperature detection unit 24L. Specifically, near the high side switch S * p, there is provided a high side temperature sensitive diode 32H whose temperature detection target is the high side switch S * p. A high side reference potential terminal THb is connected to the cathode of the high side temperature sensitive diode 32H, and a high side temperature detection unit 24H is connected to the anode via the high side temperature detection terminal THt of the drive IC 20. The high-side temperature sensitive diode 32H outputs an output voltage corresponding to the temperature of the high-side switch S * p (hereinafter, high-side element temperature). The high side temperature detection unit 24H detects the high side element temperature each time based on the output voltage. The high side element temperature αH detected by the high side temperature detection unit 24H is input to the signal generation circuit 21 through the level shift circuit 22. In the present embodiment, the high side element temperature αH is the junction temperature of the high side switch S * p.

  In the vicinity of the low-side switch S * n, a low-side temperature sensitive diode 32L whose temperature detection target is the low-side switch S * n is provided. A low-side reference potential terminal TLb is connected to the cathode of the low-side temperature sensing diode 32L, and a low-side temperature detection unit 24L is connected to the anode via the low-side temperature detection terminal TLt of the drive IC 20. The low-side temperature sensitive diode 32L outputs an output voltage corresponding to the temperature of the low-side switch S * n (hereinafter, low-side element temperature). The low side temperature detection unit 24L detects the temperature of the low side switch S * n each time based on the output voltage. The low-side element temperature αL detected by the low-side temperature detection unit 24L is input to the signal generation circuit 21. In the present embodiment, the low side element temperature αL is the junction temperature of the low side switch S * n.

  In addition, the drive IC 20 includes a high-side current detector 28H, a high-side current direction detector 29H, a high-side time detector 30H, a low-side current detector 28L, a low-side current direction detector 29L, and a low-side time detector 30L. doing. Specifically, the high-side switch S * p has a minute current (for example, “1/10000” of the collector current) having a correlation with a collector current (hereinafter, high-side current) flowing between the first terminal (collector) and the emitter. The high-side sense terminal Stp is provided. A high side current detection unit 28H is connected to the high side sense terminal Stp via a high side current detection terminal THIc of the drive IC 20. The high side current detection unit 28H detects the high side current each time based on the output current of the high side sense terminal Stp. The collector current IcH detected each time by the high side current detection unit 28H is input to the signal generation circuit 21 via the level shift circuit 22. In the present embodiment, when the high side current IcH is larger than 0, it is assumed that the current flows in the direction from the collector of the high side switch to the emitter.

  The low-side switch S * n includes a low-side sense terminal Stn that outputs a minute current having a correlation with a collector current (hereinafter referred to as a low-side current) flowing between the collector and the emitter. The low side current detection unit 28L is connected to the low side sense terminal Stn via the low side current detection terminal TLIc of the drive IC 20. The low side current detection unit 28L detects the low side current each time based on the output current of the low side sense terminal Stn. The collector current IcL detected each time by the low-side current detection unit 28L is input to the signal generation circuit 21. In the present embodiment, when the low-side current IcL is larger than 0, it is assumed that current flows in a direction from the collector of the low-side switch to the emitter.

  The high-side current direction detection unit 29H includes a collector-emitter voltage (hereinafter referred to as a high-side collector voltage VceH) of the high-side switch S * p detected through the high-side voltage detection terminal THv of the drive IC 20, and a high-side drive. Based on the high side drive signal g * p input to the unit 23H, the flow direction of the high side current is detected. The low-side current direction detection unit 29L is input to the low-side drive unit 23L and the collector-emitter voltage (hereinafter, low-side collector voltage VceL) of the low-side switch S * n detected via the low-side voltage detection terminal TLv of the drive IC 20. The flow direction of the low-side current is detected based on the low-side drive signal g * n. The current direction detectors 29H and 29L will be described in detail later.

  The high side time detection unit 30H is based on the gate voltage detected through the high side output terminal THO (hereinafter referred to as the high side gate voltage VgH) and the external drive signal input through the level shift circuit 22. Detect the delay time each time. Further, the low side time detection unit 30L detects each delay time based on a gate voltage (hereinafter, low side gate voltage VgL) detected via the low side output terminal TLO and an external drive signal. In the present embodiment, each of the time detection units 30H and 30L corresponds to a “timer”. The time detection units 30H and 30L will be described in detail later.

  Next, the dead time calculation process according to the present embodiment will be described. In the present embodiment, this processing is performed only by the drive circuit DrC corresponding to the boost converter 12 among the drive circuits DrC, DrU, DrV, DrW. Hereinafter, the reason why the dead time calculation process is performed only by the drive circuit DrC will be described with reference to FIG. 4, and then the details of this process will be described.

  4A shows the transition of the output voltage Vout of the boost converter 12, and FIGS. 4B and 4C show the transition of the operating state of the boosting high-side and low-side switches SCp and SCn.

  In step-up converter 12, when the switching frequency of step-up high-side and low-side switches SCp and SCn is decreased or the dead time is increased, variation width ΔV of output voltage Vout with reference to target voltage Vtgt is increased. When the fluctuation range ΔV increases, the output voltage of the boost converter 12 may exceed the allowable upper limit value of the voltage between the collector and emitter of each switch constituting the inverter 11. In order to avoid such a situation, for example, it is conceivable to increase the switching frequency of the boosting high-side and low-side switches SCp and SCn. However, when the switching frequency is increased, the loss and the heat generation amount are increased, so that the upper limit of the switching frequency is restricted. Therefore, in the present embodiment, dead time calculation processing is performed by the drive circuit DrC in order to shorten the dead time and reduce the fluctuation range ΔV.

  Next, a dead time calculation process in the signal generation circuit 21 of the drive circuit DrC will be described.

  First, the time detection units 30H and 30L used in this process will be described. As shown in FIG. 5, the high side time detection unit 30H determines that the logic of the external drive signal SigC is inverted from “L” to “H”, and then the high side gate voltage VgH is changed to the high side reference potential “0”. ”Until the first specified voltage Vth1 is reached is detected as the high-side on delay time tdonH. The high side on delay time tdonH is a time corresponding to a delay time from when the high side drive signal gCp is switched from the off operation command to the on operation command until the high side gate voltage VgH rises to the first specified voltage Vth1. is there. Here, in the present embodiment, the first specified voltage Vth1 is set to a threshold voltage at which the boosting high-side switch SCp switches from one of the on state and the off state to the other. In the present embodiment, the threshold voltage is set to a voltage slightly lower than the mirror voltage of the switch SCp. 5A shows the transition of the external drive signal SigU, and FIG. 5B shows the transition of the high side gate voltage VgH.

  Further, the high side time detection unit 30H determines a time from when the high side gate voltage VgH reaches the first specified voltage Vth1 to when the high side gate voltage VgH further increases and reaches the second specified voltage Vth2. Detected as high side rise time tronH. In the present embodiment, the second specified voltage Vth2 is set to a voltage higher than the first specified voltage Vth1 and lower than the output voltage Vom of the first constant voltage power supply 25.

  As shown in FIG. 6, the high side time detection unit 30H determines that the logic of the external drive signal SigC is inverted from “H” to “L”, and then the high side gate voltage VgH is changed to the first constant voltage power supply 25. The time from when the output voltage Vom drops to the second specified voltage Vth2 is detected as the high side off delay time tdoffH. The high side off delay time tdoffH is a time corresponding to a delay time from when the high side drive signal gCp is switched from the on operation command to the off operation command until the high side gate voltage VgH drops to the second specified voltage Vth2. is there. FIG. 6 corresponds to FIG.

  Further, the high side time detection unit 30H calculates a time from when the high side gate voltage VgH reaches the second specified voltage Vth2 to when the high side gate voltage VgH further decreases and reaches the first specified voltage Vth1. Detected as high side fall time troffH.

  The low-side time detection unit 30L determines that the logic of the external drive signal Sig * has been inverted from “H” to “L”, and then the low-side gate voltage VgL rises from the low-side reference potential “0” to increase the first specified voltage. The time required to reach Vth1 is detected as the low-side on delay time tdonL. In addition, the low side time detection unit 30L determines the time from when the low side gate voltage VgL reaches the first specified voltage Vth1 to when the low side gate voltage VgL further increases and reaches the second specified voltage Vth2, Detect as tronL.

  The low-side time detection unit 30L determines that the logic of the external drive signal SigU has been inverted from “L” to “H”, and then the low-side gate voltage VgL decreases from the output voltage Vom of the second constant voltage power supply 27 and increases. 2 Time until reaching the specified voltage Vth2 is detected as a low side off delay time tdoffL. Further, the low side time detection unit 30L determines the time from when the low side gate voltage VgL reaches the second specified voltage Vth2 to when the low side gate voltage VgL further decreases and reaches the first specified voltage Vth1, Detect as time troffL.

  Next, FIG. 7 shows a procedure for dead time calculation processing. This process is repeatedly executed by the signal generation circuit 21 at a predetermined cycle, for example. In the present embodiment, the signal generation circuit 21 corresponds to a “dead time calculation unit”, a “signal generation unit”, and an “output unit”.

  In this series of processing, first, in step S10, the latest high side and low side element temperatures αH and αL detected by the temperature detection units 24H and 24L, and the latest high side detected by the current detection units 28H and 28L. , Low side currents IcH and IcL are obtained. In the present embodiment, the latest high-side and low-side currents IcH and IcL detected by the current detection units 28H and 28L in a state where the high-side and low-side switches SCp and SCn are turned on are acquired.

  In subsequent step S11, the latest high side off delay time tdoffH, high side on delay time tdonH, and high side fall time troffH detected by the high side time detection unit 30H are acquired. Further, the latest low side off delay time tdoffL, low side on delay time tdonL, and low side falling time troffL detected by the low side time detection unit 30L are acquired.

  In subsequent step S12, the acquired high side off delay time tdoffH and the high side on delay time tdonH are related to the acquired high side current IcH and the high side element temperature αH, and the memory 31 in which the drive IC 20 is built. Store and update (for example, non-volatile memory). Here, as shown in FIG. 8, the delay times tdoffH and tdonH become longer as the high-side current IcH is larger or the high-side element temperature αH is higher.

  In subsequent step S13, the acquired low side off delay time tdoffL and low side on delay time tdonL are stored and updated in the memory 31 in association with the acquired low side current IcL and low side element temperature αL. Here, as shown in FIG. 9, these delay times tdoffL and tdonL become longer as the low-side current IcL is larger or the low-side element temperature αL is higher.

  In subsequent step S14, the previous high-side and low-side fall times troffH and troffL stored in the memory 31 are updated with the currently acquired high-side and low-side fall times troffH and troffL.

  In the following step S15, it is determined whether or not the next external drive signal SigU is reversed from “H” to “L”. If an affirmative determination is made in step S15, it is determined that the external drive signal SigU is inverted to “L”, and the process proceeds to step S16. In step S16, a first correction amount ΔDT1, a second correction amount ΔDT2, and a third correction amount ΔDT3 for correcting the dead time are calculated. In this step, the first correction amount ΔDT1 is selected from the memory 31 based on the high side current IcH and the high side element temperature αH from the initial value of the high side off delay time tdoffH (hereinafter, the high side off delay initial value tdoffHF). This is a value obtained by subtracting the high side off delay time tdoffH. The second correction amount ΔDT2 is a value obtained by subtracting the high-side fall time troffH stored in the memory 31 from the initial value of the high-side fall time troffH (hereinafter, the high-side fall initial value troffHF). The third correction amount ΔDT3 is obtained by subtracting the low side on delay time tdonL selected from the memory 31 based on the low side current IcL and the low side element temperature αL from the initial value of the low side on delay time tdonL (hereinafter, low side on delay initial value tdonLF). It is the value.

  In the subsequent step S17, the addition value of the first and second correction amounts ΔDT1, ΔDT2 is subtracted from the initial value DTF of the dead time, and further, the third correction amount ΔDT3 is added. Thereby, the dead time DTs is calculated. Hereinafter, the correction amounts ΔDT1 to ΔDT3 will be described with reference to FIG. Here, FIGS. 10A and 10B show transitions of the high-side and low-side drive signals gCp and gCn, and FIGS. 10C and 10D show the boosting high-side and low-side switches SCp and SCn. The transition of the gate voltages VgH and VgL is shown. In FIG. 10, the boosting high-side switch SCp that is switched off immediately before the actual dead time DTr start timing corresponds to the “first switching element”. Further, the boosting low-side switch SCn corresponds to a “second switching element”.

  As shown in the figure, the initial value DTF of the dead time and the actual dead time DTr under the situation where the logic of the external drive signal SigC is inverted to “L” has a relationship represented by the following equation (eq1). .

DTr = DTF− (tdoffHF + troffHF) + tdonLF (eq1)
In the present embodiment, the high-side off delay initial value tdoffHF and the low-side on delay initial value tdonLF are used in a situation where the high-side and low-side currents are set as reference currents and the high-side and low-side element temperatures are set as reference temperatures. This is a value preset at the time of design. For this reason, the initial value DTF of the dead time is also a value set in advance at the time of design in a situation where the high-side and low-side currents are set as reference currents and the high-side and low-side element temperatures are set as reference temperatures.

  Therefore, the first correction amount ΔDT1 indicates a difference between the initial high side off delay value tdoffHF assumed at the time of design and the actual high side off delay time tdoffH. The third correction amount ΔDT3 indicates a deviation between the low side on delay initial value tdonLF assumed at the time of design and the actual low side on delay time tdonL. These deviations occur because the actual values (collector current and element temperature) differ from the reference values (reference current and reference temperature) assumed at the time of design. These deviations increase as the difference between the reference value and the actual value increases. On the other hand, the second correction amount ΔDT2 indicates a deviation between the initial high side off fall value tdoffHF assumed at the time of design and the actual high side off fall time tdoffH. This deviation is caused by individual differences in the motor control system. Accordingly, each of the correction amounts ΔDT1 to ΔDT3 is a parameter for shortening or extending the dead time initial value DTF.

  Returning to the description of FIG. 7, when a negative determination is made in step S15, the process proceeds to step S18, and first to third correction amounts ΔDT1 to ΔDT3 are calculated. In this step, the first correction amount ΔDT1 is a low side off delay selected from the memory 31 based on the low side current IcL and the low side element temperature αL from the initial value of the low side off delay time tdoffL (hereinafter, low side off delay initial value tdoffLF). This is a value obtained by subtracting the time tdoffL. The second correction amount ΔDT2 is a value obtained by subtracting the low-side fall time troffL stored in the memory 31 from the initial value of the low-side fall time troffL (hereinafter, low-side fall initial value troffLF). The third correction amount ΔDT3 is a high side ON selected from the memory 31 based on the high side current IcH and the high side element temperature αH from the initial value of the high side ON delay time tdonH (hereinafter, the high side ON delay initial value tdonHF). This is a value obtained by subtracting the delay time tdonH. Hereinafter, each of the correction amounts ΔDT1 to ΔDT3 will be described with reference to FIG. Here, FIG. 11 corresponds to FIG. In FIG. 11, the boosting low-side switch SCn that is switched off immediately before the start timing of the actual dead time DTr corresponds to the “first switching element”. The boosting high-side switch SCp corresponds to a “second switching element”.

  As shown in the figure, the initial value DTF of the dead time and the actual dead time DTr under the situation where the logic of the external drive signal SigC is inverted to “H” have a relationship represented by the following equation (eq2). .

DTr = DTF− (tdoffLF + troffLF) + tdonHF (eq2)
In the present embodiment, the low-side off delay initial value tdoffLF and the high-side on-delay initial value tdonHF are used in a situation where the high-side and low-side currents are set as reference currents and the high-side and low-side element temperatures are set as reference temperatures. This is a value preset at the time of design. Therefore, the first correction amount ΔDT1 indicates a difference between the low side off delay initial value tdoffLF assumed at the time of design and the actual low side off delay time tdoffL. The second correction amount ΔDT2 indicates a difference between the initial low side off fall value tdoffLF assumed at the time of design and the actual low side off fall time tdoffL. Further, the third correction amount ΔDT3 indicates a deviation between the initial high side on delay value tdonHF assumed at the time of design and the actual high side on delay time tdonH.

  After the process of step S17 is completed, in the subsequent step S19, the dead time DTs calculated in step S17 is output to the control device 13 via the external output terminal Tout of the drive IC 20. In the present embodiment, when the control device 13 determines that the absolute value of the difference between the input dead time DTs and the initial value DTF of the dead time is larger than a specified value, the boost converter 12 uses each switch SCp, Scn. It is determined that some abnormality has occurred with respect to the driving of. When it is determined that an abnormality has occurred, the control device 13 performs fail-safe such as stopping the driving of the switches SCp and SCn, for example. Note that the control device 13 may notify a higher-order control device (for example, a control device that supervises vehicle control) that an abnormality has occurred.

  In addition, when the process of step S19 is completed, this series of processes is once complete | finished.

  Next, the dead time compensation process according to the present embodiment will be described. First, prior to the description of this process, the current flow direction determination process on the high side will be described with reference to FIG. This process is repeatedly executed, for example, at a predetermined cycle by the high-side current direction detection unit 29H of the drive circuit Dr ¥ configuring the inverter 11. Incidentally, in the present embodiment, the high-side current direction detection unit 29H corresponds to a “discrimination unit”.

  In this series of processing, first, in step S20, it is determined whether or not the logic of the high-side drive signal g ¥ p is “H” and the high-side gate voltage VgH is higher than zero. This process is a process for determining the flow direction of the $ phase current. In the present embodiment, a positive current is defined as a positive current that flows in a direction from the connection point of the positive phase high side and low side switches S ¥ p, S ¥ n to the positive phase of the motor generator 10.

  When an affirmative determination is made in step S20, the process proceeds to step S21, and the fact that the flow direction of the $ phase current is the positive direction is output to the signal generation circuit 21. When a negative determination is made in step S20 or when the process of step S21 is completed, the series of processes is temporarily ended.

  Next, the low-side current distribution direction determination process will be described with reference to FIG. This process is repeatedly executed, for example, at a predetermined cycle by the low-side current direction detection unit 29L of the drive circuit Dr ¥ configuring the inverter 11. Incidentally, in the present embodiment, the low-side current direction detection unit 29L corresponds to a “discrimination unit”.

  In this series of processes, first, in step S22, it is determined whether or not the logic of the low-side drive signal g ¥ n is “H” and the low-side gate voltage VgL is higher than zero. This process is a process for determining the flow direction of the $ phase current. Here, the reason why both the drive signal and the voltage information are used for the determination of the current flow direction is to improve the determination accuracy of the current flow direction. When an affirmative determination is made in step S22, the process proceeds to step S23, and the fact that the flow direction of the $ -phase current is negative is output to the signal generation circuit 21. When a negative determination is made in step S22 or when the process of step S23 is completed, the series of processes is temporarily ended.

  Next, the dead time compensation process will be described with reference to FIG. This process is repeatedly executed, for example, at a predetermined cycle by the signal generation circuit 21 of the drive circuit Dr ¥ constituting the inverter 11. In the present embodiment, the signal generation circuit 21 corresponds to a “dead time compensation unit”.

  In this series of processing, first, in step S30, it is determined whether or not the direction of the $ -phase current is the positive direction based on the information acquired from the current direction detectors 29H and 29L. If it is determined in step S30 that the direction is positive, the process proceeds to step S31. In step S31, the rising edge of the input external drive signal Sig ¥ shown in (a) is advanced by a specified time (“1/2” of dead time DTs) as shown in (c), (a) The falling edge of the external drive signal Sig ¥ shown in FIG. 4 is delayed by the specified time (“1/2” of the dead time DTs). This is because the rising edge of the external drive signal Sig \ is higher than the rising edge of the external drive signal Sig \ shown in (a) when the flow direction of the $ phase current i \ is positive, as shown in (b). Is a process for coping with the phenomenon of delaying by the dead time DTs. Such a phenomenon occurs because current flows through the $ -phase low-side diode D \ n in the dead time period. (A) shows the transition of the external drive signal Sig ¥ input to the signal generation circuit 21, (b) shows the transition of the external drive signal Sig ¥ when there is no dead time compensation, and (c) shows the dead. The transition of the external drive signal Sig ¥ when there is time compensation is shown.

  On the other hand, if it is determined in step S30 that the direction is negative, the process proceeds to step S32. In step S32, each of the rising edge and the falling edge of the input external drive signal Sig ¥ shown in (a) is set to the specified time (“1/2” of dead time DTs) as shown in (c). Just delay. This is because, when the flow direction of the $ phase current i \ is negative, as shown in (b), the falling edge of the external drive signal Sig \ is the falling edge of the external drive signal Sig \ shown in (a). This is a process for dealing with a phenomenon of delaying the dead time DTs from the edge. Such a phenomenon occurs because a current flows through the $ -phase high-side diode D \ p during the dead time period.

  In addition, when the process of step S31, S32 is completed, this series of processes is once complete | finished.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) A function for calculating a dead time and a function for generating high-side and low-side drive signals g * p and g * n are incorporated in a single drive IC 20. For this reason, it is possible to eliminate variations in dead time due to variations in signal transmission time from the control device 13 to the drive IC 20. As a result, variations in actual dead time can be reduced, and as a result, dead time can be shortened.

  In addition, since the dead time calculation function and the high-side / low-side drive signal generation function are built in the drive IC 20, the input terminal Tin for inputting the external drive signal Sig * can be made one. Thereby, the number of terminals of the drive IC 20 can also be reduced.

  Further, the current detection units 28H and 28L and the current direction detection units 29H and 29L are built in a single drive IC 20. For this reason, dead time compensation processing can be performed appropriately.

  (2) The drive IC 20 includes the current detection units 28H and 28L and the temperature detection units 24H and 24L. The dead time was corrected each time based on the high side current IcH and the low side current IcL. Further, the dead time was corrected each time based on the high side element temperature αH and the low side element temperature αL. For this reason, the dead time can be shortened even when the driving state of the motor control system changes, or when there is a secular change or individual difference in the system.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In this embodiment, the method for determining the current flow direction is changed.

  FIG. 15 shows a procedure of high-side current flow direction determination processing according to the present embodiment. This process is repeatedly executed, for example, at a predetermined cycle by the high-side current direction detection unit 29H of the drive circuit Dr ¥ configuring the inverter 11. In FIG. 15, the same processes as those in FIG. 12 are given the same step numbers for the sake of convenience.

  In this series of processes, first, in step S20a, it is determined whether or not the low-side current IcL is larger than 0 and the high-side gate voltage VgH is higher than 0. Here, the reason why both the current information and the voltage information are used for the determination of the current flow direction is to improve the determination accuracy of the current flow direction. When an affirmative determination is made in step S20a, the process proceeds to step S21 and outputs to the signal generation circuit 21 that the flow direction of the $ -phase current is the positive direction. If a negative determination is made in step S20a, or if the process of step S21 is completed, this series of processes is temporarily terminated.

  Next, FIG. 16 shows a procedure of low-side current flow direction determination processing according to the present embodiment. This process is repeatedly executed, for example, at a predetermined cycle by the low-side current direction detection unit 29L of the drive circuit Dr ¥ configuring the inverter 11. In FIG. 16, the same processes as those in FIG. 13 are given the same step numbers for convenience.

  In this series of processes, first, in step S22a, it is determined whether or not the low-side current IcL is larger than 0 and the low-side gate voltage VgL is higher than 0. When an affirmative determination is made in step S22a, the process proceeds to step S23, and the fact that the flow direction of the $ -phase current is negative is output to the signal generation circuit 21. When a negative determination is made at step S22a or when the process at step S23 is completed, the series of processes is temporarily terminated.

  According to the present embodiment described above, the same effect as that of the first embodiment can be obtained.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  In the first embodiment, the parameter used for correcting the dead time may be either the current detection value or the temperature detection value.

  In the first embodiment, if the voltage is higher than the lower limit value “0” of the first specified voltage Vth1 and lower than the upper limit value Vom, the first specified voltage Vth1 may be set to a voltage other than the threshold voltage. Good.

  When the high-side and low-side fall times troffH and troffL depend on the collector current and the element temperature, the dead time may be corrected in consideration of the current and temperature dependence of each fall time troffH and troffL.

  In the first embodiment, the dead time correction amounts ΔDT1 to ΔDT3 are continuously changed according to the collector current, but the present invention is not limited to this. For example, the correction amounts ΔDT1 to ΔDT3 may be changed in a binary manner depending on whether the collector current is larger or smaller than the reference current. The same applies to the element temperature.

  In each of the above embodiments, the first input terminal that inputs the first external drive signal that drives the high-side switch element, and the second input terminal that inputs the second external drive signal that drives the low-side switch element are single. An integrated circuit may be provided.

  In the first embodiment, the signal generation circuit 21 constituting the drive IC 20 corresponding to the inverter 11 may be provided with a function for calculating the dead time.

  The high-side and low-side switching elements are not limited to IGBTs, but may be other voltage-controlled semiconductor switching elements (for example, field effect transistors). In this case, the drain of the field effect transistor is the first terminal and the source is the second terminal. In this case, the free Hall diode connected in reverse parallel to the field effect transistor is not limited to an external diode but may be a parasitic diode of the field effect transistor. The switching element is not limited to a voltage control type semiconductor switching element, and may be a current control type switching element (for example, a bipolar transistor). Furthermore, the power conversion circuit including the switching element as a component is not limited to the step-up converter, and may be a chopper type step-down converter that steps down the input voltage and outputs it.

  DESCRIPTION OF SYMBOLS 12 ... Boost converter, 20 ... Drive IC, 21 ... Signal generation circuit, Tin ... Input terminal, 23H, 23L ... High side, low side drive part.

Claims (12)

The power converter circuit (12) is provided with a series connection body of a high side switching element (SCp) and a low side switching element (SCn), and the series connection body is connected in parallel to a DC power source (12b). A switching element drive circuit comprising an integrated circuit (20), comprising:
The integrated circuit comprises:
An input terminal (Tin) for inputting an external drive signal for driving the high-side switching element and the low-side switching element;
A dead time calculation unit (21) for calculating a dead time for avoiding both of the high side switching element and the low side switching element being turned on;
A drive signal for realizing the dead time based on the external drive signal input through the input terminal and the dead time calculated by the dead time calculation unit, the high-side switching element A signal generation unit (21) for generating a high-side drive signal for turning on and off, and a drive signal for realizing the dead time, the low-side drive signal for turning on and off the low-side switching element;
A drive unit (23H, 23L) for turning on / off the high-side switching element based on the high-side drive signal and turning on / off the low-side switching element based on the low-side drive signal;
A current detection unit (28H, 28L) for detecting a current flowing through the high-side switching element and a current flowing through the low-side switching element;
Of the high-side switching element and the low-side switching element, the one that is switched to the off operation immediately before the actual start time of the dead time is the first switching element, and after the first switching element is switched to the off operation, The one that can be switched on is the second switching element,
The dead time calculation unit is configured such that when the current detection value flowing through the first switching element by the current detection unit is small when the first switching element is turned on, the current detection value is larger than when the current detection value is large. When the detected current value flowing through the second switching element by the current detection unit is small when the second switching element is in the ON state, the dead time is corrected to be shorter than when the detected current value is large. A switching element drive circuit, wherein dead time is extended and corrected . The power converter circuit (12) is provided with a series connection body of a high side switching element (SCp) and a low side switching element (SCn), and the series connection body is connected in parallel to a DC power source (12b). A switching element drive circuit comprising an integrated circuit (20), comprising:
The integrated circuit comprises:
An input terminal (Tin) for inputting an external drive signal for driving the high-side switching element and the low-side switching element;
A dead time calculation unit (21) for calculating a dead time for avoiding both of the high side switching element and the low side switching element being turned on;
A drive signal for realizing the dead time based on the external drive signal input through the input terminal and the dead time calculated by the dead time calculation unit, the high-side switching element A signal generation unit (21) for generating a high-side drive signal for turning on and off, and a drive signal for realizing the dead time, the low-side drive signal for turning on and off the low-side switching element;
A drive unit (23H, 23L) for turning on / off the high-side switching element based on the high-side drive signal and turning on / off the low-side switching element based on the low-side drive signal;
Has a temperature before Symbol high side switching element, said temperature detecting unit for detecting the temperature of the low-side switching element (24H, 24L) and the,
Of the high-side switching element and the low-side switching element, the one that is switched to the off operation immediately before the actual start time of the dead time is the first switching element, and after the first switching element is switched to the off operation, The one that can be switched on is the second switching element,
The dead time calculation unit corrects the dead time to be shorter when the temperature detection value of the first switching element by the temperature detection unit is low than when the temperature detection value is high, and the second detection unit by the temperature detection unit A switching element drive circuit, wherein the dead time is extended and corrected when the temperature detection value of the switching element is low than when the temperature detection value is high . The integrated circuit further includes a temperature detection unit (24H, 24L) that detects the temperature of the high-side switching element and the temperature of the low-side switching element,
The dead time calculation unit corrects the dead time to be shorter when the temperature detection value of the first switching element by the temperature detection unit is low than when the temperature detection value is high, and the second detection unit by the temperature detection unit 2. The switching element drive circuit according to claim 1, wherein the dead time is extended and corrected when the temperature detection value of the switching element is low than when the temperature detection value is high. Before Symbol integrated circuit from said signal said drive signal corresponding to the generated second switching element by generating unit is switched on the operation command from the OFF operation command, the voltage of the switching control terminal of the second switching element Further has a time measuring unit (30H, 30L) for measuring a time corresponding to a delay time until the voltage rises to a specified voltage less than the upper limit value,
The switching element drive circuit according to claim 1, wherein the dead time calculation unit calculates the dead time based on a time measured by the time measuring unit. The power converter circuit (12) is provided with a series connection body of a high side switching element (SCp) and a low side switching element (SCn), and the series connection body is connected in parallel to a DC power source (12b). A switching element drive circuit comprising an integrated circuit (20), comprising:
The integrated circuit comprises:
An input terminal (Tin) for inputting an external drive signal for driving the high-side switching element and the low-side switching element;
A dead time calculation unit (21) for calculating a dead time for avoiding both of the high side switching element and the low side switching element being turned on;
A drive signal for realizing the dead time based on the external drive signal input through the input terminal and the dead time calculated by the dead time calculation unit, the high-side switching element A signal generation unit (21) for generating a high-side drive signal for turning on and off, and a drive signal for realizing the dead time, the low-side drive signal for turning on and off the low-side switching element;
A drive unit (23H, 23L) for turning on and off the high side switching element based on the high side drive signal and turning on and off the low side switching element based on the low side drive signal;
Of the high-side switching element and the low-side switching element, the one that is switched to the off operation immediately before the actual start time of the dead time is the first switching element, and after the first switching element is switched to the off operation, The one that can be switched on is the second switching element,
In the integrated circuit, after the drive signal corresponding to the second switching element generated by the signal generation unit is switched from an OFF operation command to an ON operation command, the voltage at the switching control terminal of the second switching element is It has a time measuring unit (30H, 30L) that measures the time corresponding to the delay time until it rises to a specified voltage less than the upper limit value,
The dead time calculating unit calculates the dead time based on the time measured by the time measuring unit. Before Symbol integrated circuit, said from the driving signal corresponding to the first switching element generated by the signal generator is switched off operation command from ON operation command, the voltage of the switching control terminal of the first switching element Further has a time measuring unit (30H, 30L) for measuring a time corresponding to a delay time until the voltage drops to a predetermined voltage higher than the lower limit value,
The dead time calculation unit, based on the time counted by the timer unit, the driving circuit of the switching element according to any one of claims 1 to 5 for calculating the dead time. The power converter circuit (12) is provided with a series connection body of a high side switching element (SCp) and a low side switching element (SCn), and the series connection body is connected in parallel to a DC power source (12b). A switching element drive circuit comprising an integrated circuit (20), comprising:
The integrated circuit comprises:
An input terminal (Tin) for inputting an external drive signal for driving the high-side switching element and the low-side switching element;
A dead time calculation unit (21) for calculating a dead time for avoiding both of the high side switching element and the low side switching element being turned on;
A drive signal for realizing the dead time based on the external drive signal input through the input terminal and the dead time calculated by the dead time calculation unit, the high-side switching element A signal generation unit (21) for generating a high-side drive signal for turning on and off, and a drive signal for realizing the dead time, the low-side drive signal for turning on and off the low-side switching element;
A drive unit (23H, 23L) for turning on and off the high side switching element based on the high side drive signal and turning on and off the low side switching element based on the low side drive signal;
Of the high-side switching element and the low-side switching element, the one that is switched to the off operation immediately before the actual start time of the dead time is the first switching element, and after the first switching element is switched to the off operation, The one that can be switched on is the second switching element,
In the integrated circuit, after the drive signal corresponding to the first switching element generated by the signal generation unit is switched from an on operation command to an off operation command, the voltage at the switching control terminal of the first switching element is It has a time measuring unit (30H, 30L) for measuring a time corresponding to a delay time until the voltage drops to a predetermined voltage higher than the lower limit value,
The dead time calculating unit calculates the dead time based on the time measured by the time measuring unit. The power conversion circuit includes a reactor (12b) connected to a connection point between the high-side switching element and the low-side switching element, and at least one of the high-side switching element and the low-side switching element is turned on / off. in Rukoto, the drive circuit of the switching element according to any one of claims 1 to 7 including a chopper type converter that outputs an input DC voltage by a transformer to a target voltage. The integrated circuit has one of the input terminals,
The integrated circuit comprises:
A high side output terminal (THO) connected to the open / close control terminal of the high side switching element;
A low-side output terminal (TLO) connected to the open / close control terminal of the low-side switching element;
The drive unit is
A high-side drive unit (23H) for turning on and off the high-side switching element by adjusting a voltage at an open / close control terminal of the high-side switching element via the high-side output terminal based on the high-side drive signal; ,
The low-side drive part (23L) which carries out on-off operation of the said low-side switching element by adjusting the voltage of the switching control terminal of the said low-side switching element via the said low-side output terminal based on the said low-side drive signal. driving circuit of the switching device according to any one of 1-8. The power conversion circuit includes an inverter (12) that converts an input DC voltage into an AC voltage and applies the voltage to a voltage application target (10).
In the inverter, a free wheel diode (D ¥ p, D ¥ n) is connected in antiparallel to each of the high side switching device (S ¥ p) and the low side switching device (S ¥ n),
In the inverter, each of the high-side switching element and the low-side switching element has a first terminal and a second terminal,
In the inverter, each of the high-side switching element and the low-side switching element has a current between the first terminal and the second terminal when the voltage of the switching control terminal is equal to or higher than the threshold voltage. Distribution is possible,
The integrated circuit corresponding to the inverter is
The high-side drive signal, the potential difference between the first terminal and the second terminal of the high-side switching element, the low-side drive signal, and between the first terminal and the second terminal of the low-side switching element A determination unit for determining a flow direction of a current flowing between a connection point between the high-side switching element and the low-side switching element and the voltage application target based on the potential difference of
A dead time compensation for generating the high-side drive signal and the low-side drive signal based on the current flow direction determined by the determination unit and the dead time calculated by the dead time calculation unit. driving circuit of a switching element according to any one of claims 1 to 9, further comprising a time compensator. The power conversion circuit includes an inverter (12) that converts an input DC voltage into an AC voltage and applies the voltage to a voltage application target (10).
In the inverter, a free wheel diode (D ¥ p, D ¥ n) is connected in antiparallel to each of the high side switching device (S ¥ p) and the low side switching device (S ¥ n),
In the inverter, each of the high-side switching element and the low-side switching element has a first terminal and a second terminal,
In the inverter, each of the high-side switching element and the low-side switching element has a current between the first terminal and the second terminal when the voltage of the switching control terminal is equal to or higher than the threshold voltage. Distribution is possible,
The integrated circuit corresponding to the inverter is
A current detection unit (28H, 28L) for detecting a current flowing through the high-side switching element and a current flowing through the low-side switching element;
A current detection value by the current detection unit, a potential difference between the first terminal and the second terminal of the high-side switching element, and a potential difference between the first terminal and the second terminal of the low-side switching element. Based on the connection point of the high-side switching element and the low-side switching element, and a determination unit for determining the flow direction of the current flowing between the voltage application target,
A dead time compensation for generating the high-side drive signal and the low-side drive signal based on the current flow direction determined by the determination unit and the dead time calculated by the dead time calculation unit. driving circuit of a switching element according to any one of claims 1 to 9, further comprising a time compensator. The integrated circuit, the driving circuit of the switching element according to any one of claims 1 to 11 having the further output unit which outputs the dead time calculated by the dead time calculating unit to the outside.

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