JP5939095B2 - Switching element drive circuit - Google Patents

Description

  The present invention relates to a switching element drive circuit having an active gate control function.

  As this type of drive circuit, as can be seen in Patent Document 1 below, when switching a semiconductor switching element (for example, IGBT) from an off state to an on state, there is one that changes the charge rate of charge to the gate of the switching element. Are known.

  Specifically, in the above drive circuit, the gate is charged with charge through the first gate resistor until a specified time elapses after the switching element operation signal is switched to the ON operation command. On the other hand, after the timing when the specified time elapses, the gate is charged with charge through the second gate resistor having a resistance value lower than that of the first gate resistor. This makes it possible to change the charge charging speed from a low speed to a high speed in the middle of the period from the start of charging to the completion of charging, and a surge that occurs when the switching element is switched to the ON state. Voltage and switching loss can be reduced.

JP-A-9-46201

  By the way, in order to reduce surge voltage and switching loss that occur when the switching element is switched from the on state to the off state, the present inventors have adopted a configuration that performs active gate control when switching the switching element to the off state. Thought. Specifically, in this configuration, the charge discharge rate is adjusted at the timing when a specified time elapses from the reference timing included in the above period in the middle of the period from the start of the discharge of the charge from the gate to the completion thereof. The speed is changed from high speed to low speed.

  Here, the present inventors faced the problem that when the above configuration is adopted, the change timing of the charge discharge rate deviates from an appropriate timing at which the surge voltage and switching loss can be reduced.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a surge voltage and a switching loss that occur when a switching element is switched to an off state in a switching element drive circuit having an active gate control function. It is an object of the present invention to provide a new driving circuit capable of reducing the above.

In order to solve the above-mentioned problem, the invention according to claim 1 is configured such that the switching element (S * #: * = c, u, v, w: # = p, n) is brought into the off state by being an on operation command. switched on, the driving circuit of the switching elements to switch off state the switching device from the oN state by being turned off operation command, the off-state the switching element from the on state by being with the off operation command The discharge means (Lda, Ldb, 28a, 28b, 30a, 30b) for discharging the charge from the switching control terminal of the switching element, and until the discharge is completed after the discharge of the charge is started by the discharge means. And at the timing when the specified time (TA) has elapsed from the reference timing included in the period. The specified time is set shorter as the current flowing between the active gate control means for changing the electric speed from the high speed to the low speed and the input / output terminals of the switching element when the switching element is turned on is larger. And setting means.

  The present inventors have examined in detail the factors that cause the change timing of the discharge rate to deviate from an appropriate timing at which the surge voltage and switching loss can be reduced. And it discovered that the factor was the magnitude of the electric current which flows between input-output terminals when a switching element is made into an ON state. That is, the larger the current flowing between the input and output terminals, the shorter the time from the reference timing to the appropriate timing due to the higher mirror voltage. Focusing on this point, the above-described invention includes setting means. For this reason, the change timing of the discharge rate can be set according to the current flowing between the input and output terminals, and the surge voltage and switching loss that occur when the switching element is switched to the off state can be suitably reduced. .

1 is a system configuration diagram according to a first embodiment. FIG. The block diagram of the drive unit concerning the embodiment. The figure which shows the outline | summary of the active gate control concerning the embodiment. The figure which shows the relationship between the collector electric current and discharge speed change timing concerning the embodiment. 6 is a flowchart showing a procedure of variable setting processing according to the embodiment. The figure which shows the acquisition timing of the sense voltage concerning the embodiment. The figure which shows the temperature characteristic of the sense voltage concerning 2nd Embodiment. 6 is a flowchart showing a procedure of variable setting processing according to the embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a switching element drive circuit according to the present invention is applied to a vehicle including a rotating machine as an in-vehicle main machine will be described with reference to the drawings.

  As shown in FIG. 1, the motor generator 10 is an in-vehicle main machine and is connected to drive wheels (not shown). The motor generator 10 is connected to a high voltage battery 12 via an inverter IV and a converter CV. Here, converter CV includes capacitor C, a pair of switching elements Scp and Scn connected in parallel to capacitor C, and a reactor L that connects a connection point between the pair of switching elements Scp and Scn and the positive electrode of high-voltage battery 12. And. Specifically, the converter CV has a function of boosting the voltage of the high voltage battery 12 (for example, “288V”) up to a predetermined voltage (for example, “666V”) by turning on / off the switching elements Scp, Scn.

  On the other hand, the inverter IV includes a serial connection body of switching elements Sup and Sun, a serial connection body of switching elements Svp and Svn, and a serial connection body of switching elements Swp and Swn. Connection points of these series connection bodies are respectively connected to the U, V, and W phases of the motor generator 10.

  In the present embodiment, an insulated gate bipolar transistor (IGBT) is used as the switching element S * # (* = c, u, v, w: # = p, n). In addition, a free wheel diode D * # is connected in antiparallel to each of the switching elements S * #.

  The control device 14 uses the low voltage battery 16 as a power source, and operates the inverter IV and the converter CV to control the control amount (for example, torque) of the motor generator 10 as desired. Specifically, the control device 14 outputs the operation signals gcp and gcn to the drive unit DU, thereby turning on and off the switching elements Scp and Scn of the converter CV. Further, the control device 14 outputs the operation signals gup, gun, gvp, gvn, gwp, gwn to the drive unit DU, thereby turning on / off the switching elements Sup, Sun, Svp, Svn, Swp, Swn of the inverter IV. Here, the high-potential side operation signal g * p and the corresponding low-potential side operation signal g * n are complementary to each other. That is, the high-potential side switching element S * p and the corresponding low-potential side switching element S * n are alternately turned on.

  The interface 18 is a device for exchanging signals between the high voltage system including the high voltage battery 12 and the low voltage system including the low voltage battery 16 while insulating the interface. In this embodiment, the interface 18 is provided with an optical insulating element (photocoupler).

  Next, the configuration of the drive unit DU will be described with reference to FIG.

  As shown in the figure, the drive unit DU includes a drive IC 20 that is a one-chip semiconductor integrated circuit. A constant voltage power supply 24 is connected to a terminal T1 of the drive IC 20 via a charging resistor 22. The constant voltage power supply 24 is for applying a voltage to the switching control terminal (gate) of the switching element S * #. In the present embodiment, the terminal voltage of the constant voltage power supply 24 is indicated by “VH”.

  The terminal T1 is connected to a terminal T2 of the drive IC 20 through a P-channel MOSFET (charging switching element 26). Terminal T2 is connected to the gate of switching element S * #.

  The gate of the switching element S * # is connected to the terminal T3 of the drive IC 20 via the first discharging resistor 28a, and the terminal T3 is connected to the N-channel MOSFET (first discharging switching element 30a). And connected to a terminal T4 of the drive IC 20. The gate of the switching element S * # is connected to the terminal T5 of the drive IC 20 via the second discharging resistor 28b, and the terminal T5 is an N-channel MOSFET (second discharging switching element 30b). To the terminal T4. Here, the resistance value Rb of the second discharging resistor 28b is set higher than the resistance value Ra of the first discharging resistor 28a. The terminal T4 is connected to the output terminal (emitter) of the switching element S * #.

  The switching element S * # includes a sense terminal St that outputs a minute current having a positive correlation with a current flowing between the input terminal (collector) and the emitter (hereinafter referred to as collector current). Specifically, the sense terminal St outputs, for example, a current of about “1 / several thousand” to “1/10000” of the collector current. The sense terminal St is connected to the emitter via the sense resistor 32. As a result, a voltage drop occurs in the sense resistor 32 due to a minute current output from the sense terminal St. Therefore, the potential on the sense terminal St side of the sense resistor 32 (hereinafter, sense voltage Vse) is correlated with the collector current. State quantity. The sense voltage Vse is input to the drive control unit 34 in the drive IC 20 via the terminal T6 of the drive IC 20.

  Incidentally, in the present embodiment, the sense voltage Vse when the potential on the sense terminal St side among the both ends of the sense resistor 32 is higher than the potential of the emitter is defined as positive. The emitter potential is set to “0”.

  In the vicinity of the switching element S * #, a temperature sensitive diode SD * # for detecting the temperature of the switching element S * # is provided. The temperature sensitive diode SD * # is supplied with electric charge from a constant voltage power supply 36 externally attached to the drive IC 20 via a constant current power supply 38. The cathode of the temperature sensitive diode SD * # is connected to the emitter, and the anode is connected to the terminal T7 of the drive IC 20. According to such a configuration, the temperature sensitive diode SD * # outputs an output voltage corresponding to the temperature of the switching element S * #. The output voltage of the temperature sensitive diode SD * # is input to the drive control unit 34 via the terminal T7. The drive control unit 34 detects the temperature of the switching element S * # based on the output voltage of the temperature sensitive diode SD * #.

  Next, the charge / discharge processing of the gate charge according to the present embodiment executed by the drive control unit 34 will be described. Since the drive control unit 34 according to the present embodiment is hardware, the charge / discharge processing is actually executed by a logic circuit.

  First, the charging process will be described.

  In the present embodiment, the charging process is performed by constant current control. Specifically, in the constant current control, when the operation signal g * # input via the terminal T8 of the drive IC 20 is an ON operation command, the voltage drop amount of the charging resistor 22 is set to the target value (for example, 1V). ), The gate voltage of the charging switching element 26 is manipulated. During the period when the charging process is performed, the first and second discharging switching elements 30a and 30b are turned off.

  Subsequently, the discharge process will be described.

  In the present embodiment, the resistance value of the discharge path connected to the gate of the switching element S * # is changed from a low value to a high value during the period from the start of the discharge of the charge from the gate to the completion thereof. Perform active gate control. This is control for reducing the surge voltage and switching loss that occur when the switching element S * # is switched from the on state to the off state. Hereinafter, the discharge process will be described in detail with reference to FIG.

  FIG. 3 is a diagram illustrating an example of the discharge process according to the present embodiment. Specifically, FIG. 3A shows the transition of the gate voltage Vge, the collector current Ic, and the collector-emitter voltage Vce, FIG. 3B shows the transition of the operation signal g * #, and FIG. ) Shows the transition of the operation state of the first discharge switching element 30a, and FIG. 3D shows the transition of the operation state of the second discharge switching element 30b.

  As illustrated, when the operation signal g * # is switched to the OFF operation command at time t1 which is the reference timing, the first discharge switching element 30a is switched to the ON operation, and the charge discharge rate is increased. It is said. As a result, charges are discharged from the gate by the first discharge path Lda connecting the gate and emitter of the switching element S * # via the first discharge resistor 28a.

  After that, at time t2 when the specified time TA has elapsed after the operation signal g * # is switched to the off operation command, the first discharge switching element 30a is switched to the off operation and the second discharge switching element 30b is switched to ON operation. As a result, the discharge speed of the charge is changed to a low speed, and the charge is discharged from the gate by the second discharge path Ldb connecting the gate and the emitter of the switching element S * # via the second discharge resistor 28b. The

  Here, the specified time TA is set from the viewpoint of reducing the surge voltage and switching loss that occur when the switching element S * # is switched from the on state to the off state. Specifically, for example, the specified time TA is set so that the discharge rate can be changed at a timing immediately before the occurrence of the surge voltage.

  In addition, what is necessary is just to time-measure the elapsed time after switching to OFF operation command by the timer function with which the drive control part 34 is provided. Further, the charging switching element 26 is turned off during the period in which the discharging process is performed. Further, the first discharge path Lda and the second discharge path Ldb correspond to a plurality of discharge paths connected to the gate.

  By the way, the present inventors faced the problem that the change timing of the discharge rate by the active gate control deviates from an appropriate timing capable of reducing the surge voltage and the switching loss. Hereinafter, this problem will be described with reference to FIG.

  FIG. 4 shows transitions of the gate voltage Vge, the collector current Ic, and the collector-emitter voltage Vce when the switching element S * # is switched to the off state. Specifically, FIG. 4A shows a transition when the collector current immediately before the switching element S * # is turned off is large (Ic = 400 A), and FIG. 4B shows the transition of the collector current Ic. The transition of the small case (30A) is shown.

  Incidentally, in FIGS. 4A and 4B, the time scale (horizontal axis scale) is the same as each other, and the amount per unit length on the drawing (vertical length) regarding the gate voltage Vge and the collector-emitter voltage Vce. The axis scale is also the same. Also, the vertical scale for the collector current Ic in FIG. 4A is larger than the vertical scale for the collector current Ic in FIG.

  In the illustrated example, the operation signal g * # is switched to the OFF operation signal at time t1. Here, the larger the collector current Ic when the switching element S * # is turned on, the higher the mirror voltage when the switching element S * # is subsequently switched to the off state. Here, FIG. 4A shows the mirror voltage when the collector current Ic is large as “Vmα”, and FIG. 4B shows the mirror voltage when the collector current Ic is small as “Vmβ”. It was.

  As the mirror voltage increases, the gate charging current increases, and the end timing of the mirror period is advanced. As a result, the value Tα when the collector current Ic is large is the collector time with respect to the time from when the operation signal g * # is switched to the OFF operation signal until the appropriate discharge rate change timing (timing immediately before the occurrence of the surge voltage). It becomes shorter than the value Tβ when the current is small.

  For this reason, for example, when the specified time TA is adapted when the collector current Ic is small, the change timing of the discharge rate is delayed and the surge voltage increases when the actual collector current Ic becomes larger than the collector current Ic at the time of adaptation. There is a risk.

  In order to solve such a problem, in the present embodiment, a variable setting process for variably setting the specified time TA based on the sense voltage Vse having a correlation with the collector current Ic is performed.

  FIG. 5 shows the procedure of the variable setting process. This process is executed by the drive control unit 34. Since the drive control unit 34 according to the present embodiment is hardware, the above processing is actually executed by a logic circuit.

  In this series of processes, first, in step S10, whether or not the logical product of the condition that the operation signal g * # is an ON operation command and the condition that the gate voltage Vge is the upper limit voltage VH is true. Judging.

  If an affirmative determination is made in step S10, the process proceeds to step S12, and the sense voltage Vse in a period in which the sense voltage Vse is in a steady state is acquired. Here, as shown in FIG. 6, the period in which the steady state is set is a timing at which the operation signal g * # is switched to the OFF operation command from a timing later than the timing at which the gate voltage Vge reaches the upper limit voltage VH. Period (time t2 to t3). 6A shows the transition of the operation signal g * #, FIG. 6B shows the transition of the gate voltage Vge, FIG. 6C shows the transition of the collector current Ic, and FIG. 6 (d) shows the transition of the sense voltage Vse.

  According to the process of this step, the grasping accuracy of the collector current Ic can be improved. That is, immediately after the operation signal g * # is switched to the ON operation signal, the transition of the sense voltage Vse becomes a transitional state, so that the relationship between the sense voltage Vse and the collector current Ic deviates from the initially assumed relationship, for example. There is a possibility that the grasping accuracy of the current Ic may be lowered.

  Returning to the description of FIG. 5, in the following step S14, the higher the acquired sense voltage Vse, the shorter the specified time TA used when the switching element S * # is turned off next time. Incidentally, the specified time TA may be set using, for example, a map in which the sense voltage Vse and the specified time TA are specified.

  When a negative determination is made in step S10 or when the process of step S14 is completed, this series of processes is temporarily terminated.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) A variable setting process is performed in which the specified time TA is set shorter as the sense voltage Vse is higher. For this reason, it can be avoided that the change timing of the discharge rate deviates from an appropriate timing capable of reducing the surge voltage and the switching loss. Thereby, the surge voltage and switching loss which arise when switching element S * # is switched to an OFF state can be reduced suitably.

  (2) The specified time TA is set using the sense voltage Vse in a period in which the sense voltage Vse is in a steady state. For this reason, the grasping accuracy of the collector current Ic can be enhanced, and the setting accuracy of the specified time TA can be enhanced. Thereby, it can avoid more suitably that the change timing of a discharge rate shifts | deviates from the said appropriate timing.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the present embodiment, the temperature of the switching element S * # detected by the temperature sensitive diode SD * # (hereinafter, temperature detection value TD) is added to the setting of the specified time TA by the variable setting process. This is done in view of the positive correlation between the temperature detection value TD and the temperature of the sense resistor 32, and is to avoid a decrease in the accuracy of grasping the collector current Ic. That is, as shown in FIG. 7, in a situation where the collector current Ic is constant, the higher the temperature of the sense resistor 32, the higher the resistance value of the sense resistor 32, and thus the sense voltage Vse becomes higher. As a result, there is a concern that the accuracy of grasping the collector current Ic based on the sense voltage Vse is lowered.

  FIG. 8 shows a procedure of variable setting processing according to the present embodiment. This process is executed by the drive control unit 34. Since the drive control unit 34 according to the present embodiment is hardware, the above processing is actually executed by a logic circuit. In FIG. 8, the same processes as those shown in FIG. 5 are denoted by the same reference numerals for the sake of convenience.

  In the series of processes, when the process of step S12 is completed, the process proceeds to step S14a, and the specified time TA is variably set based on the temperature detection value TD and the sense voltage Vse. Specifically, the specified time TA is set shorter as the temperature detection value TD is lower or the sense voltage Vse is higher.

  When a negative determination is made in step S10 or when the process of step S14a is completed, this series of processes is temporarily terminated.

  Thus, in this embodiment, the accuracy of grasping the collector current Ic can be increased by adding the temperature detection value TD to the setting of the specified time TA. As a result, the setting accuracy of the specified time TA can be further increased, and as a result, it is possible to more suitably avoid the change timing of the discharge speed from the appropriate timing.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  -"Temperature detection means" is not limited to a temperature sensitive diode, but may be, for example, a resistor (temperature measuring resistor).

  The “setting unit” is not limited to one that variably sets the specified time TA based on the sense voltage Vse. For example, a means for directly detecting the collector current Ic such as a shunt resistor provided in the collector current distribution path may be provided, and the specified time TA may be set shorter as the detected collector current Ic is larger.

  The “active gate control means” is not limited to switching the discharge rate to two stages, but may be one that switches to N stages (N is an integer of 3 or more). In this case, “N−1” timings for changing the discharge rate are set. Specifically, in such a configuration, for example, “N−1” prescribed periods that are different from each other are set with reference to the reference timing described in the first embodiment, and discharge paths having different resistance values are set as “ This can be realized by providing “N−1”.

  -"Reference timing" is not restricted to what was illustrated to the said 1st Embodiment. For example, the gate voltage Vge lowering start timing (time t3 in FIG. 6) may be used as the reference timing. Further, for example, the end timing of the period during which the sense voltage Vse is in a steady state (the rising timing of the sense voltage Vse; time t3 in FIG. 6) may be used as the reference timing. In this case, for example, the process of masking the sense voltage Vse for grasping the reference timing for a predetermined time after the operation signal g * # is switched to the on operation command is performed, and then the timing at which the sense voltage rapidly rises is set as the reference timing. You only have to figure it out.

  The “active gate control means” is not limited to the one exemplified in the first embodiment, and for example, the following may be adopted.

  By switching the operation signal g * # to the off operation command, both the first discharge switching element 30a and the second discharge switching element 30b are turned on, and the charge discharge rate is increased. Thereafter, one of the first discharge switching element 30a and the second discharge switching element 30b is switched to the off operation at a timing when the specified time TA has elapsed after the operation signal g * # is switched to the off operation command. Then, change the discharge speed to low speed. In the case of the above configuration, the resistance values of the first discharge resistor 28a and the second discharge resistor 28b may be the same or different from each other.

  Further, the “active gate control means” is not limited to the one that changes the resistance value of the discharge path, and may be the one described in (A) and (B) below, for example.

  (A) An energization operation type element (for example, a MOSFET) capable of switching the connection between the emitter and a portion having a lower potential than the emitter and the gate is provided in the discharge path connected to the gate. In such a configuration, the element is operated to connect the gate to a location where the potential is lower than that of the emitter, instead of connecting the gate and the emitter only in the initial stage of the discharge process where the discharge rate is desired to be high. Thereafter, the discharge rate is changed to a low rate by changing the operating state of the element in order to connect the gate to the emitter.

  (B) A discharge path connected to the gate includes a first element (for example, a MOSFET) that is turned on and off to open and close the path and a resistor. A power source is connected to the gate via a predetermined electrical path, and a second element (for example, MOSFET) that is turned on and off to open and close the electrical path is provided in the electrical path. In such a configuration, the first element is turned on at the start of the discharge process, and the second element is turned off only in the initial stage of the discharge process where it is desired to increase the discharge rate. Then, the second element is switched to the on operation. According to such a change in the operation state of the first and second elements, a current flows from the power source to the resistor in the discharge path, and a current flowing from the gate to the resistor decreases. As a result, the discharge of the gate charge is prevented, and the discharge rate is changed from the high rate to the low rate.

  In each of the above embodiments, the circuit configuration in which the sense terminal St is connected to the emitter of the switching element S * # via the sense resistor 32 is adopted, but the present invention is not limited to this. For example, instead of the emitter, a circuit configuration connected to a member (for example, a power source) having the same potential as the emitter may be employed. In this case, the potential of the power source is variably set according to the actual potential of the emitter.

  The “switching element” is not limited to the IGBT but may be a MOSFET, for example.

  -The application object of this invention is not restricted to the switching element which comprises a vehicle-mounted power converter circuit (inverter IV or converter CV). Further, the application target of the present invention is not limited to the switching elements constituting the power conversion circuit.

  28a ... first discharge resistor, 28b ... second discharge resistor, 30a ... first discharge switching element, 30b ... second discharge switching element, Lda ... first discharge path, Ldb ... Second discharge path, S * # (* = c, u, v, w: # = p, n)... Switching element.

Claims (5)

The switching element (S * #: * = c, u, v, w: # = p, n) is switched from the OFF state to the ON state by being an ON operation command, and the switching is performed by being an OFF operation command. In the switching element drive circuit that switches the element from the on state to the off state,
Wherein in order to switch off operation command and is the the switching element by from the ON state to the OFF state, the discharge means for discharging electric charge from the switching control terminal of the switching element (Lda, Ldb, 28a, 28b , 30a, 30b) When,
The discharge rate of the electric charge is adjusted at a timing during which a specified time (TA) elapses from a reference timing included in the period from when the electric discharge is started by the electric discharge means to completion. Active gate control means for changing from high speed to low speed;
Setting means for setting the specified time shorter as the current flowing between the input and output terminals of the switching element when the switching element is turned on is larger;
A switching element drive circuit comprising: The switching element includes a sense terminal (St) that outputs a minute current having a correlation with a current flowing between the input and output terminals.
The output terminal of the switching element or a member having the same potential as the output terminal and the sense terminal are connected via a sense resistor (32),
2. The switching element drive circuit according to claim 1, wherein the setting means sets the specified time to be shorter as a sense voltage (Vse), which is a potential difference between both ends of the sense resistor, is higher.   3. The switching element according to claim 2, wherein the setting means sets the specified time using the sense voltage when the voltage (Vge) of the switching control terminal is set to the upper limit value (VH). Drive circuit. Temperature detecting means (SD * #) for detecting a temperature correlated with the temperature of the sense resistor;
4. The switching element drive circuit according to claim 2, wherein the setting means further comprises means for setting the prescribed time longer as the temperature (TD) detected by the temperature detection means is higher. The discharging means includes
A plurality of discharge paths (Lda, Ldb) connected to the open / close control terminal and discharging the charge;
Open / close elements (30a, 30b) provided in each of the plurality of discharge paths and energized to open and close the discharge paths;
A resistor (28a, 28b) provided in each of the plurality of discharge paths;
With
The active gate control means changes the discharge rate of the charge from a high speed to a low speed by changing at least one operation state of the switching element. A switching element driving circuit according to claim 1.