JP6194664B2 - Serial transmission device and serial transmission system - Google Patents

Description

  The present invention relates to a serial transmission device and a serial transmission system for serial data communication.

  Wiring the parallel bus on the board is becoming more difficult, and the timing management between the signal lines of the parallel bus becomes more difficult as the communication speed increases. When inter-board communication is performed via a bus, it is expensive to use a parallel bus harness, and thus the bus must be serialized.

  For example, Patent Document 1 discloses a configuration in which error correction is performed by serializing a parallel bus and adding an error correction code to serial data for each access (command).

  However, in the method using the error correction code, there is a problem that the amount of communication data increases and the latency is increased by executing the encoding process and the decoding process.

  An object of the present invention is to provide a serial transmission device that corrects an error of a parallel signal subjected to serial-parallel conversion without using an error correction code.

A serial transmission device according to one aspect of the present invention is provided.
A serial-parallel conversion circuit for serial-parallel conversion of serial signals into parallel signals;
A serial transmission device comprising an error correction circuit that performs error correction processing on the parallel signal,
The error correction circuit performs error correction on the parallel signal by executing an error correction process for removing a change in the value of the parallel signal so that the value of the parallel signal does not change for a predetermined time period. A parallel signal is output.

  ADVANTAGE OF THE INVENTION According to this invention, the serial transmission apparatus which corrects an error without using an error correction code | cord | chord can be provided for the parallel signal by which the serial-parallel conversion was carried out.

It is a block diagram which shows the structure of the differential serial transmission system 10-1 which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-2 which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-3 which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-4 which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-5 which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-6 which concerns on Embodiment 6 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-7 which concerns on Embodiment 7 of this invention. It is a block diagram which shows the structure of differential serial transmission system 10-8A which concerns on Embodiment 8A of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-8B which concerns on Embodiment 8B of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-9 which concerns on Embodiment 9 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-10 which concerns on Embodiment 10 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-11 which concerns on Embodiment 11 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-12 which concerns on Embodiment 12 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-13 which concerns on Embodiment 13 of this invention. It is a block diagram which shows the structure of the differential serial transmission system 10-1 of FIG. 1, and its peripheral device. It is a timing chart which shows operation | movement of the differential serial transmission apparatus 1-1 of FIG. It is a timing chart which shows operation | movement of the differential serial transmission apparatus 2-1 when the differential serial transmission apparatus 2-1 of FIG. 1 receives the reception serial signal of FIG. 15A. 3 is a timing chart showing the operation of the error correction circuit 32 of FIG. 4 is a timing chart showing an operation of the differential serial transmission device 1-3 of FIG. 3. 16 is a timing chart illustrating an operation of the differential serial transmission device 2-3 when the differential serial transmission device 2-3 of FIG. 3 receives the reception serial signal of FIG. 16A. 16 is a timing chart showing the operation of the error correction circuit 32a of FIG. 3 when the differential serial transmission device 2-3 of FIG. 3 receives the received serial signal of FIG. 16A. FIG. 5 is a circuit diagram showing a configuration of an error correction circuit for each signal line 32b in FIG. 4; 6 is a timing chart showing the operation of the signal line error correction circuit 32b of FIG. It is a timing chart which shows operation | movement of the differential serial transmission apparatus 2-7 of FIG. It is a timing chart which shows operation | movement of the differential serial transmission apparatus 2-7 of FIG. It is a timing chart which shows operation | movement of the differential serial transmission apparatus 2-7 of FIG. It is a timing chart which shows operation | movement of the differential serial transmission apparatus 2-7 of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
FIG. 14 is a block diagram showing the configurations of the differential serial transmission system 10-1 and its peripheral devices according to Embodiment 1 of the present invention. In FIG. 14, the memory controller 5 is connected to the memory 6 via the differential serial transmission system 10-1. Here, the memory 6 includes, for example, chips 6a and 6b such as DRAM. The differential serial transmission system 10-1 includes differential serial transmission devices 1-1 and 2-1 that are connected to each other via differential serial transmission lines 3 and 4 that use, for example, a high-speed serial data communication system. Is done. The memory controller 5 is connected to the differential serial transmission device 1-1 via a data bus 7a, an address bus 7b, and a control signal bus 7c. Further, the differential serial transmission device 2-1 is connected to the memory 6 through a data bus 8a, an address bus 8b, and a control signal bus 8c. The high-speed serial data communication method is a communication method that complies with standards such as PCI (Peripheral Component Interconnect) Express, USB 3.0 (Universal Serial Data Bus Version 3.0), and the like.

  FIG. 1 is a block diagram showing a configuration of the differential serial transmission system 10-1 of FIG. In FIG. 1, a differential serial transmission device 1-1 includes a parallel bus interface circuit 11, a parallel / serial conversion circuit 12A, a serial / parallel conversion circuit 12B, an error correction circuit 13, a transmission differential driver 14, and a reception. And a differential receiver 15. The differential serial transmission device 2-1 includes a parallel bus interface circuit 33, a parallel / serial conversion circuit 31 </ b> A, a serial / parallel conversion circuit 31 </ b> B, an error correction circuit 32, a transmission differential driver 35, and a reception differential receiver 34. And is configured.

  In FIG. 1, a data bus 7 a, an address bus 7 b, and a control signal bus 7 c from the memory controller 5 are connected to a parallel bus interface circuit 11. Here, the control signal bus 7c transmits control signals including chip select signals CS0_N and CS1_N, a write enable signal WE_N, and a read enable signal RE_N respectively corresponding to the chips 6a and 6b of FIG.

  In the differential serial transmission device 1-1 of FIG. 1, the parallel bus interface circuit 11 includes data DATA, address ADDR (address data) input from the memory controller 5 via the data bus 7a, the address bus 7b, and the control signal bus 7c. ) And the control signal are combined into a parallel interface signal (parallel signal). The parallel bus interface circuit 11 outputs the synthesized parallel interface signal to the parallel / serial conversion circuit 12A. Further, the parallel bus interface circuit 11 outputs the data DATA included in the parallel interface signal from the error correction circuit 13 to the memory controller 5 via the data bus 7a. The parallel-serial conversion circuit 12A performs parallel-serial conversion of the parallel interface signal from the parallel bus interface circuit 11 into a serial signal, and outputs the serial signal to the transmission differential driver 14 by a single end method. The transmission differential driver 14 converts the input serial signal into a differential serial signal and transmits the differential serial signal to the reception differential receiver 34 of the differential serial transmission device 2-1 via the differential serial transmission line 3.

  The reception differential receiver 15 receives a differential serial signal transmitted from the differential serial transmission device 2-1 via the differential serial transmission line 4, converts the differential serial signal into a single-ended serial signal, and then performs serial-parallel conversion. Output to the circuit 12B. The serial / parallel conversion circuit 12 </ b> B serial-parallel converts the serial signal from the reception differential receiver 15 into a parallel interface signal and outputs the parallel interface signal to the error correction circuit 13. The error correction circuit 13 performs error correction processing on the input parallel interface signal, and outputs the error-corrected parallel interface signal to the parallel bus interface circuit 11. The error correction process will be described later in detail with reference to FIGS. 15A, 15B and 15C.

  In FIG. 1, a data bus 8 a, an address bus 8 b, and a control signal bus 8 c from the parallel bus interface circuit 33 are connected to the memory 6. Here, the control signal bus 8c transmits a control signal including chip select signals CS0_N and CS1_N, a write enable signal WE_N, and a read enable signal RE_N.

  In the differential serial transmission device 2-1 of FIG. 1, the reception differential receiver 34 receives a differential serial signal transmitted from the differential serial transmission device 1-1 via the differential serial transmission line 3. The reception differential receiver 34 converts the received differential serial signal into a single-ended serial signal and outputs it to the serial-parallel conversion circuit 31B. The serial / parallel conversion circuit 31 </ b> B serial-parallel converts the serial signal from the reception differential receiver 34 into a parallel interface signal and outputs the parallel interface signal to the error correction circuit 32. The error correction circuit 32 executes error correction processing on the input parallel interface signal and outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33. The error correction process will be described later in detail with reference to FIGS. 15A, 15B and 15C. The parallel bus interface circuit 33 performs predetermined signal conversion on the input parallel interface signal and separates it into data DATA, an address ADDR, and a control signal. The parallel bus interface circuit 33 also outputs the separated data DATA, address ADDR, and control signal to the memory 6 via the data bus 8a, address bus 8b, and control signal bus 8c, respectively. The parallel bus interface circuit 33 outputs data DATA input from the memory 6 via the data bus 8a to the parallel / serial conversion circuit 31A as a parallel interface signal. The parallel-serial conversion circuit 31A performs parallel-serial conversion of the parallel interface signal from the parallel bus interface circuit 33 into a serial signal, and outputs the serial signal to the transmission differential driver 35 by a single end method. The transmission differential driver 35 converts an input serial signal into a differential serial signal, and transmits the differential serial signal to the reception differential receiver 15 of the differential serial transmission device 1-1 via the differential serial transmission line 4.

  The operation of the differential serial transmission system 10-1 configured as described above will be described below. The differential serial transmission device 1-1 is set to a master mode which is an operation mode in which the parallel bus interface circuit 11 operates to receive signals from the data bus 7a, the address bus 7b, and the control signal bus 7c. The differential serial transmission device 2-1 operates in a slave mode, which is an operation mode in which the parallel bus interface circuit 33 operates so that signals can be output to the memory 6 via the data bus 8a, the address bus 8b, and the control signal bus 8c. It is set to be.

  FIG. 15A is a timing chart showing the operation of the differential serial transmission device 1-1 of FIG. In FIG. 15A, the chip select signal CS0_N output from the memory controller 5 is held so as to be asserted for a time period of a predetermined number of assert cycles of, for example, 6 cycles with respect to the sampling clock. Further, the address ADDR output from the memory controller 5 is held so as to indicate a constant address value for a time period of a predetermined hold cycle number, for example, 8 cycles. The parallel-serial conversion circuit 12A performs parallel-serial conversion of the parallel interface signal including the chip select signal CS0_N and the address ADDR in FIG. 15A into a serial signal. Specifically, the parallel-serial conversion circuit 12A samples the parallel interface signal in synchronization with the sampling clock of FIG. 15A, which is an internal sampling clock, for example, and generates sampling parallel data. The parallel / serial conversion circuit 12A converts the sampling parallel data into a serial signal. The transmission differential driver 14 converts the serial signal subjected to parallel-serial conversion into a transmission serial signal, and outputs the serial signal to the reception differential receiver 34 of the differential serial transmission device 2-1 via the differential serial transmission line 3. Here, the received serial signal received via the differential serial transmission line 3 may include an error generated in the differential serial transmission line 3 as shown in FIG. 15A.

  FIG. 15B is a timing chart showing the operation of the differential serial transmission device 2-1 when the differential serial transmission device 2-1 of FIG. 1 receives the received serial signal of FIG. 15A. 15B, the serial-parallel conversion circuit 31B in FIG. 1 samples the serial signal from the reception differential receiver 34 in synchronization with the sampling lock in FIG. 15B, which is an internal sampling clock, for example. As shown in FIG. 15B, sampling parallel data generated by sampling may include an error. Further, FIG. 15B shows an address ADDR included in the parallel interface signal after serial / parallel conversion by the serial / parallel conversion circuit 31B and a chip select signal CS0_N in the control signal. The chip select signal CS0_N of FIG. 15B contains an error to negate by changing by one cycle within a six cycle time period to be held to assert. Further, the address ADDR in FIG. 15B changes by one cycle within the time period of eight cycles to be held so as to indicate a constant address value in the access period, and is different from the address value to be held. Including errors as shown.

  FIG. 15C is a timing chart showing the operation of the error correction circuit 32 of FIG. In FIG. 15C, the error correction circuit 32 performs error correction processing for removing the change in the value of the chip select signal CS0_N with respect to the chip select signal CS0_N so that the value does not change for the time period of the prescribed number of assert cycles. Run. Next, the error correction circuit 32 outputs the error-corrected chip select signal CS0_N to the parallel bus interface circuit 33. Specifically, for example, the error correction circuit 32 counts the number of cycles in a time period in which the chip select signal CS0_N is asserted. Here, there are cases where the chip select signal CS0_N changes and is negated when the counted number of cycles is less than the prescribed 6 assertion cycle number. In this case, the error correction circuit 32 corrects the value of the cycle before the change has occurred by asserting the chip select signal CS0_N in the cycle in which the change has occurred. As a result, the change in the value of the chip select signal CS0_N is removed, and the error-corrected chip select signal CS0_N becomes the same signal as the transmitted chip select signal CS0_N in FIG. 15A. Note that the error correction circuit 32 executes an error correction process for the chip select signal CS1_N, similarly to the error correction process for the chip select signal CS0_N.

  In FIG. 15C, the error correction circuit 32 executes an error correction process for removing the change in the address value for the address ADDR so that the address value does not change for the time period of the specified number of hold cycles. Next, the error correction circuit 32 outputs the error-corrected address ADDR to the parallel bus interface circuit 33. Specifically, for example, the error correction circuit 32 counts the number of cycles in a time period in which the address ADDR indicates a constant address value. Here, there are cases where the address value changes when the counted number of cycles is less than the prescribed 8 hold cycle number. In this case, as shown in FIG. 15C, the error correction circuit 32 corrects the address ADDR so as to indicate the address value of the cycle before the change occurs in the cycle in which the change has occurred. As a result, the change in the value of the address ADDR is removed, and the address ADDR after error correction becomes the same signal as the transmitted address ADDR in FIG. 15A. As described above, the error correction circuit 32 does not change for each signal of the parallel interface signal for a time period of the number of cycles in which the value should be kept constant (hereinafter referred to as a specified number of cycles). Error correction processing for removing the change in the value of each signal is executed. Next, the error correction circuit 32 outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33. Here, the prescribed number of cycles includes, for example, the prescribed number of assert cycles of the chip select signals CS0_N and CS1_N, the prescribed number of hold cycles of the address ADDR, and the like.

  As described above, the differential serial transmission system 10-1, the memory controller 5, and the memory 6 operate as follows. For example, when executing a write process, the memory controller 5 asserts a write enable signal WE_N, asserts a chip select signal CS0_N, and outputs an address ADDR and data DATA to the parallel bus interface circuit 11. At this time, the error correction circuit 32 performs the above-described error correction processing on the chip select signal CS0_N and the address ADDR included in the parallel interface signal from the serial / parallel conversion circuit 31B. The memory 6 puts the chip 6a corresponding to the chip select signal CS0_N after error correction into a writable operation state, and stores the input data DATA at the address ADDR after error correction.

  For example, when executing a read process, the memory controller 5 asserts a read enable signal RE_N, asserts a chip select signal CS1_N, and outputs an address ADDR to the parallel bus interface circuit 11. At this time, as described above, the error correction circuit 32 executes error correction processing on the chip select signal CS1_N and the address ADDR included in the parallel interface signal from the serial / parallel conversion circuit 31B. The memory 6 puts the chip 6b corresponding to the chip select signal CS1_N after the error correction into an readable state, reads the data DATA of the address ADDR after the error correction, and sends it to the parallel bus interface circuit 33 via the data bus 8a. Output.

  The error correction circuit 13 in the differential serial transmission device 1-1 in FIG. 1 does not change the data DATA so that the value does not change for a time period of a specified cycle number of the data DATA that should be kept constant. An error correction process for removing a change in the value of DATA is executed. Next, the error correction circuit 13 outputs the error-corrected data DATA to the parallel bus interface circuit 11. The memory 6 outputs only data DATA to the parallel bus interface circuit 33 via the data bus 8a, so that the parallel interface signal input to the error correction circuit 13 includes only data DATA.

  According to the differential serial transmission device 1-1, 2-1 according to the first embodiment of the present invention configured as described above, the differential serial transmission device 1-1, 2-1 converts the parallel interface signal into a parallel interface signal. Error correction circuits 13 and 32 for executing error correction processing are provided. Here, the error correction circuits 13 and 32 execute error correction processing for removing the change of the parallel interface signal so that the value of the parallel interface signal does not change for a predetermined time period. The parallel interface signal is output.

  According to the above configuration, the error correction circuit 32 removes the change in the value of each signal of the parallel interface signal after serial-parallel conversion so that the value does not change for a specified time period. Perform correction processing. Therefore, the error correction circuit 32 can execute error correction processing on each signal of the parallel interface signal including the chip select signals CS0_N and CS1_N and the address ADDR without using any of the error correction code and the cyclic redundancy check code. . Further, the error correction circuit 13 can perform error correction on the data DATA without using any of the error correction code and the cyclic redundancy check code.

  Further, since the error correction process executed by the error correction circuit 32 is simpler than the process using the error correction code or the cyclic redundancy check code, the signal transfer efficiency can be improved as compared with the conventional technique. The latency can be reduced. Further, the error correction circuit 13 has the same effect as the error correction circuit 32.

  Furthermore, according to the above configuration, there is no need to further provide an additional circuit for adding the error correction code or the cyclic redundancy check code to the transmission serial signal in the differential serial transmission apparatuses 1-1 and 2-1. For this reason, the increase in the circuit scale for error correction in the differential serial transmission apparatuses 1-1 and 2-1 can be suppressed only to the increase in the error correction circuits 13 and 32 on the receiving side having a simple configuration.

  In the first embodiment described above, the error correction circuit 32 performs error correction processing on the chip select signals CS0_N and CS1_N and the address ADDR. However, the present invention is not limited to this, and the error correction circuit 32 performs error correction processing on each signal of the parallel interface signal including the write enable signal WE_N, the control signal including the read enable signal RE_N, and the data DATA. May be.

  In the first embodiment described above, the error correction circuits 13 and 32 execute error correction processing for each input signal so that the value does not change for a time period of a specified number of cycles. However, the present invention is not limited to this, and the error correction circuits 13 and 32 may execute error correction processing on each input signal so that the value does not change for a specified time period.

Embodiment 2. FIG.
FIG. 2 is a block diagram showing a configuration of the differential serial transmission system 10-2 according to the second embodiment of the present invention. In FIG. 2, the differential serial transmission system 10-2 includes differential serial transmission devices 1-2 and 2-2. The differential serial transmission system 10-2 is different from the differential serial transmission system 10-1 of FIG. 1 in the following points.
(1) The differential serial transmission device 1-2 further includes an access setting register 13A as compared with the differential serial transmission device 1-1, and further includes an error correction circuit 13a instead of the error correction circuit 13. about.
(2) The differential serial transmission device 2-2 further includes an access setting register 32A as compared with the differential serial transmission device 2-1, and an error correction circuit 32a instead of the error correction circuit 32. about.
Hereinafter, differences will be described.

  In the differential serial transmission device 2-2 in FIG. 2, the access setting register 32A holds the data of the prescribed number of cycles of the first embodiment used for error correction processing so that it can be set and changed. Data of a prescribed number of cycles is output to the error correction circuit 32a. Here, the prescribed number of cycles includes the prescribed number of assert cycles of the chip select signals CS0_N and CS1_N, the prescribed number of hold cycles of the address ADDR, and the like. The error correction circuit 32a in FIG. 2 receives a specified number of cycles from the access setting register 32A and uses it for error correction processing. The error correction circuit 32a removes a change in the value of each signal of the parallel interface signal subjected to serial / parallel conversion so that the value of the signal does not change for a time period of a prescribed number of cycles. Execute. Next, the error correction circuit 32 a outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33.

  In the differential serial transmission device 1-2 in FIG. 2, the access setting register 13A holds data having a specified cycle number of the data DATA of the first embodiment used for error correction processing so that it can be set and changed. Further, the access setting register 13A outputs data having a specified number of cycles of the held data DATA to the error correction circuit 13a. The error correction circuit 13a in FIG. 2 receives a specified cycle number of the data DATA from the access setting register 13A and uses it for error correction processing. The error correction circuit 13a performs error correction processing for removing the change in the value of the data DATA so that the value of the data DATA of the parallel interface signal subjected to the serial / parallel conversion does not change only for the time period of the specified number of cycles. Run. Next, the error correction circuit 13 a outputs the error-corrected data DATA to the parallel bus interface circuit 11.

  According to the differential serial transmission system 10-2 according to the second embodiment of the present invention configured as described above, the access setting registers 13A and 32A that hold the predetermined time period and output to the error correction circuits 13a and 32a. Is further provided.

  According to the said structure, it has an effect similar to the said Embodiment 1. FIG. In addition, the specified number of cycles held in the access setting registers 13A and 32A can be arbitrarily changed by register setting, for example, by the user according to, for example, the differential serial transmission system 10-2 or its use environment.

  Further, since the error correction circuits 13a and 32a execute error correction processing using a specified number of cycles that is the access timing set in the access setting registers 13A and 32A, the latency can be reduced as compared with the prior art. .

Embodiment 3. FIG.
FIG. 3 is a block diagram showing a configuration of the differential serial transmission system 10-3 according to the third embodiment of the present invention. In FIG. 3, the differential serial transmission system 10-3 includes differential serial transmission devices 1-3 and 2-3. The differential serial transmission system 10-3 differs from the differential serial transmission system 10-1 of FIG. 1 in the following points.
(1) The differential serial transmission device 1-3 further includes an access information history storage unit 16 as compared with the differential serial transmission device 1-1, and the error correction circuit shown in FIG. The circuit 13a is provided.
(2) The differential serial transmission device 2-3 further includes an access information history accumulating unit 36 as compared with the differential serial transmission device 2-1, and the error correction circuit shown in FIG. The circuit 32a is provided.
Hereinafter, differences will be described.

  In the differential serial transmission device 2-3 of FIG. 3, the parallel bus interface circuit 33 separates the received parallel interface signal into data DATA, an address ADDR, and a control signal and outputs them to the memory 6. At this time, the parallel bus interface circuit 33 counts the number of cycles in a time period in which each signal such as the chip select signals CS0_N and CS1_N and the address ADDR included in the parallel interface signal has a constant value. Next, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the access information history storage unit 36 as access information. The access information history storage unit 36 receives the number of cycles counted for each input signal, and stores the maximum number of cycles for each signal as the access information history among the sequentially input cycle numbers. The following operations are performed. That is, the access information history accumulating unit 36 compares the number of cycles input for each signal with the maximum number of cycles held, and the number of cycles input is larger than the maximum number of cycles held. At this time, the number of input cycles is updated as the maximum number of cycles. On the other hand, the access information history accumulating unit 36 does not perform update for each signal when the number of input cycles is equal to or less than the maximum number of cycles held. The access information history accumulating unit 36 outputs the maximum number of cycles for each held signal to the error correction circuit 32a. The maximum cycle number includes, for example, the maximum assert cycle number that is the maximum cycle number of the chip select signals CS0_N and CS1_N, the maximum hold cycle number that is the maximum cycle number of the address ADDR, and the like.

  The error correction circuit 32a executes error correction processing as follows using the maximum number of cycles included in the access information history received from the access information history storage unit 36 as the specified number of cycles. In other words, the error correction circuit 32a sets the value of each signal so that the value of each signal of the received parallel interface signal does not change only for the time period of the specified number of cycles received from the access information history storage unit 36. An error correction process is performed to remove the change. Next, the error correction circuit 32 a outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33.

  In the differential serial transmission device 1-3 of FIG. 3, the parallel bus interface circuit 11 outputs data DATA included in the received parallel interface signal to the memory controller 5. At this time, the parallel bus interface circuit 11 counts the number of cycles in a time period in which the data DATA has a constant value, and outputs the counted number as access information to the access information history storage unit 16. The access information history accumulating unit 16 receives the number of cycles input, and performs the following operation in order to accumulate the maximum number of cycles as the access information history among the number of cycles of the sequentially input data DATA. That is, the access information history accumulating unit 16 compares the number of cycles of the input data DATA with the maximum number of cycles of the stored data DATA. Next, when the number of cycles of the input data DATA is larger than the maximum number of cycles of the stored data DATA, the access information history storage unit 16 sets the number of cycles of the input data DATA to the maximum number of cycles of the data DATA. Update as. On the other hand, the access information history storage unit 16 does not update when the number of cycles of the input data DATA is equal to or less than the maximum number of cycles of the data DATA being held. The access information history accumulating unit 16 outputs the maximum number of cycles of the held data DATA to the error correction circuit 32a.

  The error correction circuit 13a executes error correction processing as follows using the maximum number of cycles of the data DATA, which is the access information history received from the access information history storage unit 16, as the prescribed number of cycles. In other words, the error correction circuit 13a removes the change in the value of the data DATA so that the value of the data DATA does not change only for the time period of the specified number of cycles received from the access information history storage unit 16. Execute the process. Next, the error correction circuit 13 a outputs the error-corrected parallel interface signal to the parallel bus interface circuit 11.

  FIG. 16A is a timing chart showing the operation of the differential serial transmission device 1-3 of FIG. FIG. 16B is a timing chart showing the operation of the differential serial transmission device 2-3 when the differential serial transmission device 2-3 of FIG. 3 receives the received serial signal of FIG. 16A. FIG. 16C is a timing chart showing the operation of the error correction circuit 32a of FIG. As shown in FIG. 16A, the received serial signal may include an error similar to that in FIG. 15A. In this case, as shown in FIGS. 16B and 16C, the chip select signal CS0_N and the address ADDR included in the parallel interface signal input to the error correction circuit 32a each contain the same error as in FIG. 15B.

  In FIG. 16C, the access information history accumulating unit 36 in FIG. 3 accumulates, for example, the maximum number of assert cycles of the chip select signal CS0_N, which is 6 cycles, as an access information history, and outputs it to the error correction circuit 32a. The error correction circuit 32a changes the value of the chip select signal CS0_N with respect to the chip select signal CS0_N of FIG. 16C including an error so that the value does not change only for a time period of 6 cycles which is the prescribed number of assert cycles. Execute the error correction process to be removed.

  In FIG. 16C, the access information history accumulating unit 36 in FIG. 3 accumulates, for example, the maximum hold cycle number of the address ADDR, which is eight cycles, as an access information history, and outputs it to the error correction circuit 32a. The error correction circuit 32a removes a change in the address value so that the address value does not change for a time period of 8 cycles, which is the specified number of hold cycles, with respect to the address ADDR in FIG. Execute.

  According to the configuration of the differential serial transmission system 10-3 according to the third embodiment of the present invention configured as described above, the parallel bus interface circuits 11 and 33 have constant error-corrected parallel interface signal values. A certain time period is counted, and the elapsed time period is output. Further, the differential serial transmission devices 1-3 and 2-3 store the maximum time period as the access information history in the measured time period and output it to the error correction circuits 13 a and 32 a, respectively. 36. Here, the error correction circuits 13a and 32a remove the change in the value of the parallel interface signal so that the value of the parallel interface signal does not change only for the maximum time period with respect to the parallel interface signal subjected to serial / parallel conversion. Execute the process.

  According to the said structure, it has an effect similar to the said Embodiment 1. FIG. Further, the error correction circuits 13a and 32a execute simple error correction processing based on the access information history at the control timing that is the maximum number of cycles. Therefore, the latency can be reduced as compared with an error correction process using an error correction code or a cyclic redundancy check code.

  Further, the error correction circuits 13a and 32a in FIG. 3 execute the error correction process using the maximum number of cycles based on the actual access information history as a specified time period. Therefore, the specified time period can be changed according to the actual system without setting it by software or the like.

  In the third embodiment described above, each of the parallel bus interface circuits 11 and 33 counts the number of cycles in a time period in which each signal of the parallel interface signal has a constant value. However, the present invention is not limited to this, and each of the parallel bus interface circuits 11 and 33 may measure a time period in which each signal of the parallel interface signal has a constant value. In this case, each of the parallel bus interface circuits 11 and 33 outputs the time period counted for each signal to the access information history accumulating units 16 and 36 as access information.

  In the third embodiment, the access information history accumulating units 16 and 36 output data indicating the maximum number of cycles of each signal of the parallel interface signal to the error correction circuits 13a and 32a, respectively. However, the present invention is not limited to this, and each of the access information history accumulating units 16 and 36 receives, for each signal of the parallel interface signal, data indicating the longest time period in which the signal has a constant value as the error correction circuit 13a. , 32a. In this case, for example, the error correction circuits 13a and 32a may perform the error correction process using the longest time period for each input signal as a specified time period for each signal.

Embodiment 4 FIG.
FIG. 4 is a block diagram showing a configuration of a differential serial transmission system 10-4 according to the fourth embodiment of the present invention. In FIG. 4, the differential serial transmission system 10-4 includes differential serial transmission devices 1-4 and 2-4. The differential serial transmission system 10-4 is different from the differential serial transmission system 10-1 of FIG. 1 in the following points.
(1) The differential serial transmission device 1-4 includes an error correction circuit 13b for each signal line in place of the error correction circuit 13 as compared with the differential serial transmission device 1-1.
(2) The differential serial transmission device 2-4 includes an error correction circuit 32b for each signal line instead of the error correction circuit 32, as compared with the differential serial transmission device 2-1.
Hereinafter, differences will be described.

  FIG. 17 is a circuit diagram showing a configuration of the signal line error correction circuit 32b of FIG. In FIG. 17, the signal line error correction circuit 32b includes signal correction circuits 37A, 37B, and 37C provided for each signal line of the parallel interface signal input from the serial / parallel conversion circuit 31B of FIG. . Here, the signal lines of the chip select signals CS0_N and CS1_N from the serial / parallel conversion circuit 31B are connected to the signal correction circuits 37A and 37B, respectively. A plurality of signal lines of the address ADDR from the serial / parallel conversion circuit 31B are connected to the signal correction circuit 37C.

  In FIG. 17, the signal correction circuit 37 </ b> A includes D flip-flop circuits 51, 52, 53, an AND gate 54, a NOR gate 55, an OR gate 56, and a multiplexer 57. For example, the sampling clock shown in FIG. 18 is supplied to each clock terminal of the D flip-flop circuits 51, 52, and 53. The chip select signal CS0_N in the parallel interface signal input from the serial / parallel conversion circuit 31B is output to the D flip-flop circuit 51, the AND gate 54, and the NOR gate 55. The D flip-flop circuit 51 outputs an output signal to the D flip-flop circuit 52, the AND gate 54, and the NOR gate 55. The D flip-flop circuit 52 outputs an output signal to the A terminal of the AND gate 54, the NOR gate 55, and the multiplexer 57. The AND gate 54 performs an AND operation on the received three signals and outputs a signal indicating the operation result to the OR gate 56. Further, the NOR gate 55 performs a NOR operation on the three received signals and outputs a signal indicating the calculation result to the OR gate 56. The OR gate 56 performs a logical OR operation on the signals from the AND gate 54 and the NOR gate 55, and outputs a signal indicating the operation result to the selection terminal of the multiplexer 57. The multiplexer 57 outputs a signal input to the A terminal to the D flip-flop circuit 53 when the output signal from the OR gate 56 is at a high level. The multiplexer 57 outputs a signal input to the B terminal to the D flip-flop circuit 53 when the output signal from the OR gate 56 is at a low level. The D flip-flop circuit 53 feeds back the output signal to the B terminal of the multiplexer 57 and outputs the output signal to the parallel bus interface circuit 33. The signal correction circuit 37B has the same configuration as the signal correction circuit 37A of FIG. Further, the signal correction circuit 37C includes a plurality of circuits provided for each signal line of the address bus of the address ADDR and having the same configuration as the signal correction circuit 37A.

  FIG. 18 is a timing chart showing the operation of the signal line error correction circuit 32b of FIG. 4 configured as described above. 18, the signal correction circuit 37A in FIG. 17 outputs the received chip select signal CS0_N to the parallel bus interface circuit 33 as it is when the chip select signal CS0_N is continuously asserted for a time period of three cycles or more. . However, the value of the chip select signal CS0_N may change so as to be negated, for example, only for a time period of one cycle within a time period of three cycles. In this case, the signal correction circuit 37A asserts the output signal of the chip select signal CS0_N in the cycle in which the change has occurred as in the previous cycle in which the change has occurred. In this way, the signal correction circuit 37A changes the value of the chip select signal CS0_N so that the value of the chip select signal CS0_N does not change only for a time period of a prescribed number of assert cycles, for example, 3 cycles. Execute the error correction process to be removed. Next, the signal correction circuit 37A outputs the error-corrected chip select signal CS0_N to the parallel bus interface circuit 33.

  Further, the signal correction circuit 37B operates in the same manner as the signal correction circuit 37A and executes error correction processing on the chip select signal CS1_N. Here, the error correction circuit 37B removes the change in the value of the chip select signal CS1_N so that the value does not change for the time period of the prescribed number of assert cycles that is 3 cycles with respect to the chip select signal CS1_N. Perform correction processing.

  Further, the plurality of circuits provided for each signal line of the address bus of the address ADDR in the signal correction circuit 37C operate in the same manner as the signal correction circuit 37A, and each signal of the plurality of signal lines of the address bus of the address ADDR is applied. An error correction process is executed for this. Here, the signal correction circuit 37C does not change the signal of each signal line so that the value of the signal of each signal line of the address bus of the address ADDR does not change only for a time period of a specified hold cycle number of 3 cycles. Error correction processing is performed to remove the change in the value of. As described above, the error correction circuit 32b for each signal line performs error correction processing on each signal of the input parallel interface signal, and outputs the parallel interface signal after error correction to the parallel bus interface circuit 33.

  The error correction circuit 13b for each signal line of the differential serial transmission device 1-4 of FIG. 4 is provided for each signal line of the data bus of data DATA and has a plurality of circuits having the same configuration as the signal correction circuit 37A of FIG. It is configured with. Here, a plurality of signal lines in the data bus of the data DATA included in the parallel interface signal from the serial / parallel conversion circuit 12B are connected to the error correction circuit 13b for each signal line. The error correction circuit 13b for each signal line changes the signal of each signal line so that the value of the signal of each signal line of the data bus of the data DATA does not change for a time period of a specified number of cycles of 3 cycles. An error correction process for removing the change in value is executed. Next, the signal line error correction circuit 13 b outputs the error-corrected data DATA to the parallel bus interface circuit 11.

  According to the configuration of the differential serial transmission system 10-4 according to the fourth embodiment of the present invention configured as described above, the parallel interface signal subjected to serial / parallel conversion includes a plurality of signals. Further, the error correction circuits 13b and 32b are errors that remove the change in the value of each signal of the parallel interface signal so that the value of each signal of the parallel interface signal does not change for a predetermined time period. Perform correction processing.

  According to the said structure, it has an effect similar to the said Embodiment 1. FIG. Further, the signal line error correction circuit 32b of FIG. 17 has a simple circuit configuration, and when the value of the input signal changes within the time period of the specified number of cycles, the output value is independent of the current input value. Do not change. As described above, the error correction circuit 32b for each signal line is a circuit configured to perform a calculation in a corresponding single signal by the signal correction circuits 37A, 37B, and 37C of FIG. 17 provided on the signal line. Therefore, the circuit scale of the differential serial transmission device 2-4 can be reduced as compared with the prior art. Further, the differential serial transmission device 1-4 has the same operational effects as the differential serial transmission device 2-4.

  In the fourth embodiment described above, the error correction circuit 13b, 32b for each signal line performs error correction processing so that the value of the signal input for each signal line does not change only within the time period of the specified number of cycles of 3 cycles. Execute. However, the present invention is not limited to this, and the error correction circuits 13b and 32b for each signal line are changed only within a time period of a specified number of cycles of 2 cycles or 4 cycles or more. You may comprise so that the error correction process which is not made may be performed.

Embodiment 5. FIG.
FIG. 5 is a block diagram showing a configuration of a differential serial transmission system 10-5 according to the fifth embodiment of the present invention. In FIG. 5, the differential serial transmission system 10-5 includes differential serial transmission devices 1-3 and 2-5. The differential serial transmission system 10-5 differs from the differential serial transmission system 10-3 of FIG. 1 in the following points.
(1) Compared to the differential serial transmission device 2-3 of FIG. 3, the differential serial transmission device 2-5 replaces the access information history storage unit 36 with the access information history storage unit 36A for CS0 and the access for CS1. An information history storage unit 36B is provided, and an error correction circuit 32c is provided instead of the error correction circuit 32a.
Hereinafter, differences will be described.

  In the differential serial transmission device 2-5 of FIG. 5, the parallel bus interface circuit 33 separates the received parallel interface signal into data DATA, an address ADDR, and a control signal and outputs them to the memory 6. At this time, the parallel bus interface circuit 33 counts the number of cycles in a time period in which each signal such as the chip select signals CS0_N and CS1_N and the address ADDR included in the parallel interface signal has a constant value. When the chip select signal CS0_N is asserted, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the CS0 access information history accumulating unit 36A as CS0 access information. Further, when the chip select signal CS1_N is asserted, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the CS1 access information history storage unit 36B as CS1 access information.

  The CS0 access information history accumulating unit 36A performs the following operation in order to accumulate the maximum number of cycles for each signal as the CS0 access information history among the number of cycles sequentially input. That is, the CS0 access information history accumulating unit 36A compares the number of cycles input for each signal with the maximum number of cycles held, and the number of cycles input exceeds the maximum number of cycles held. When it is larger, the input cycle number is updated as the maximum cycle number. On the other hand, the access information history accumulating unit 36A for CS0 does not perform update for each signal when the number of cycles input is equal to or less than the maximum number of cycles held. The CS0 access information history accumulating unit 36A outputs the maximum number of cycles held for each signal to the error correction circuit 32c. Here, the maximum cycle number includes, for example, the maximum assert cycle number that is the maximum cycle number of the chip select signals CS0_N and CS1_N, the maximum hold cycle number that is the maximum cycle number of the address ADDR, and the like.

  The CS1 access information history storage unit 36B has the same configuration as the CS0 access information history storage unit 36A. The CS1 access information history accumulating unit 36B operates in the same manner as the CS0 access information history accumulating unit 36A. The CS1 access information history accumulating unit 36B sets the maximum number of cycles for each signal in the CS1 access information sequentially input. Accumulated as access information history. The CS1 access information history accumulating unit 36B outputs to the error correction circuit 32c the maximum number of cycles for each signal, which is the stored CS1 access information history.

  The error correction circuit 32c receives the maximum number of cycles for each signal of the parallel interface signal from each of the CS0 access information history storage unit 36A and the CS1 access information history storage unit 36B. When the chip select signal CS0_N included in the input parallel interface signal is asserted, the error correction circuit 32c uses the maximum number of cycles for each signal of the received CS0 access information history to correct the error as follows. Execute the process. That is, the error correction circuit 32c removes the change of the value of each signal of the parallel interface signal so that the value does not change only for the time period of the maximum number of cycles received from the CS0 access information history storage unit 36A. Execute error correction processing. When the chip select signal CS1_N included in the input parallel interface signal is asserted, the error correction circuit 32c uses the maximum number of cycles for each signal of the received CS1 access information history as follows. Perform error correction processing. That is, the error correction circuit 32c removes the change in the value of each signal of the parallel interface signal so that the value does not change only for the time period of the maximum number of cycles received from the access information history storage unit 36B for CS1. Execute error correction processing. The error correction circuit 32 c outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33.

  According to the configuration of the differential serial transmission system 10-5 according to the fifth embodiment of the present invention configured as described above, the same operational effects as those of the third embodiment are obtained. In addition, the error correction circuit 32c performs error correction processing using the access information history accumulated for each of the chip select signals CS0_N and CS1_N. Therefore, it is possible to change the timing and method for removing serial data communication errors for each of the chip select signals CS0_N and CS1_N.

  In addition, the error correction circuit 32c executes error correction processing using the maximum number of cycles of each signal, which is the access information history accumulated by the CS0 access information history accumulation unit 36A and the CS1 access information history accumulation unit 36B. For this reason, the prescribed maximum number of cycles can be changed according to the actual system without being set by software or the like.

  In the fifth embodiment described above, two access information history storage units (36A, 36B) are provided in the differential serial transmission device 2-5. However, the present invention is not limited to this. For example, three or more access information history storage units may be provided in the differential serial transmission device 2-5 according to the number of signal lines of the chip select signal.

Embodiment 6. FIG.
FIG. 6 is a block diagram showing a configuration of a differential serial transmission system 10-6 according to the sixth embodiment of the present invention. In FIG. 6, the differential serial transmission system 10-6 includes differential serial transmission devices 1-3 and 2-6. 6, the differential serial transmission system 10-6 is different from the differential serial transmission system 10-3 in FIG. 3 in the following points.
(1) Compared to the differential serial transmission apparatus 2-3 of FIG. 3, the differential serial transmission apparatus 2-6 replaces the access information history storage section 36 with the access information history storage section 36C for AS0 and the access for AS1. An information history storage unit 36D is provided, and the error correction circuit 32d of FIG. 5 is provided instead of the error correction circuit 32a.
Here, the AS0 access information history storage unit 36C and the AS1 access information history storage unit 36D store the maximum number of cycles for each signal of access to the prescribed address areas AS0 and AS1 provided in the memory 6, respectively. . Hereinafter, differences will be described.

  In the differential serial transmission device 2-6 of FIG. 6, the parallel bus interface circuit 33 separates the received parallel interface signal into data DATA, address ADDR, and control signal and outputs them to the memory 6. At this time, the parallel bus interface circuit 33 counts the number of cycles in a time period in which each signal such as the chip select signals CS0_N and CS1_N and the address ADDR included in the parallel interface signal has a constant value. Next, when the address ADDR is included in the address area AS0, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the AS0 access information history storage unit 36C as AS0 access information. When the address ADDR is included in the address area AS1, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the AS1 access information history accumulating unit 36D as AS1 access information.

  The AS0 access information history accumulating unit 36C performs the following operation in order to accumulate the maximum number of cycles for each signal among the sequentially inputted number of cycles as the AS0 access information history. That is, the AS0 access information history accumulating unit 36C compares the number of cycles input for each signal with the maximum number of cycles held, and the number of cycles input is greater than the maximum number of cycles held. When it is larger, the input cycle number is updated as the maximum cycle number. On the other hand, the AS0 access information history accumulating unit 36C does not perform update for each signal when the number of input cycles is equal to or less than the maximum number of cycles held. The AS0 access information history accumulating unit 36C outputs the held maximum number of cycles for each signal to the error correction circuit 32d. Here, the maximum cycle number includes, for example, the maximum assert cycle number of the chip select signals CS0_N and CS1_N, the maximum hold cycle number of the address ADDR, and the like.

  The AS1 access information history storage unit 36D has the same configuration as the AS0 access information history storage unit 36C. The AS1 access information history accumulating unit 36D operates in the same manner as the AS0 access information history accumulating unit 36C. The AS1 access information history accumulating unit 36D determines the maximum number of cycles for each signal among the number of cycles in the sequentially input AS1 access information. Accumulated as access information history. The AS1 access information history accumulating unit 36D outputs the held maximum number of cycles for each signal to the error correction circuit 32d.

  The error correction circuit 32d receives the maximum number of cycles for each signal of the parallel interface signal from each of the AS0 access information history storage unit 36C and the AS1 access information history storage unit 36D. When the address ADDR of the input parallel interface signal is included in the address area AS0, the error correction circuit 32d performs error correction processing as follows using the maximum number of cycles for each signal of the received access information history for AS0. Execute. That is, in this case, the error correction circuit 32d is an error that removes the change in the value of each signal so that the value of each signal of the parallel interface signal does not change for the time period of the maximum number of cycles received. Perform correction processing. Further, when the address ADDR of the input parallel interface signal is included in the address area AS1, the error correction circuit 32d uses the maximum number of cycles for each signal of the received access information history for CS1 as described below. Perform correction processing. That is, in this case, the error correction circuit 32d removes a change in the value of each signal so that the value of each signal of the parallel interface signal does not change only for the time period of the maximum number of received cycles. Execute the process. The error correction circuit 32 d outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33.

  The differential serial transmission system 10-6 according to the sixth embodiment of the present invention configured as described above has the same operational effects as those of the third embodiment. Further, the error correction circuit 32d executes error correction processing using the access information history accumulated for each of the address areas AS0 and AS1. For this reason, it is possible to change the timing and method for removing the serial data communication error for each of the address areas AS0 and AS1. In addition, an optimum error correction corresponding to the plurality of address areas AS0 and AS1 can be performed. Furthermore, the prescribed number of cycles can be changed without setting by software according to the working system of each address area AS0, AS1.

  In the sixth embodiment described above, the two access information history accumulation units 36C and 36D are provided in the differential serial transmission device 2-6. However, the present invention is not limited to this, and for example, three or more access information history storage units may be provided in the differential serial transmission device 2-6 according to the number of specified address areas provided in the memory 6. .

Embodiment 7. FIG.
FIG. 7 is a block diagram showing a configuration of a differential serial transmission system 10-7 according to the seventh embodiment of the present invention. In FIG. 7, the differential serial transmission system 10-7 includes differential serial transmission devices 1-7 and 2-7. The differential serial transmission system 10-7 is different from the differential serial transmission system 10-3 of FIG. 3 in the following points.
(1) The differential serial transmission device 1-7 includes an access information history storage unit 16a instead of the access information history storage unit 16 as compared with the differential serial transmission device 1-3, and a history storage enable register Further provided 17A.
(2) Compared to the differential serial transmission device 2-3, the differential serial transmission device 2-7 includes an access information history storage unit 36a instead of the access information history storage unit 36, and a history storage enable register 38A was further provided.
Hereinafter, differences will be described.

  In FIG. 7, the history accumulation enable register 17 </ b> A sends a control signal indicating whether the access information history accumulation unit 16 a accumulates the access information history, that is, “accumulation on” or “accumulation off”, to the memory 6. Received from a controlling CPU (not shown) and stored. Further, the history accumulation enable register 38A receives from the CPU a control signal indicating whether or not to accumulate access information history by the access information history accumulation unit 36a, that is, “accumulation on” or “accumulation off”, and stores it. . The history accumulation enable registers 17A and 38A output the stored control signals to the access information history accumulation units 16a and 36a as history accumulation enable signals, respectively.

  In the differential serial transmission device 2-7 of FIG. 7, the access information history accumulating unit 36a receives the number of cycles counted for each signal as the access information from the parallel bus interface circuit 33 as the access information. . The access information history accumulating unit 36a performs the following operation for accumulating the access information history in the same manner as the access information history accumulating unit 36 in FIG. That is, when “accumulation is on”, the access information history accumulating unit 36a accumulates the maximum number of cycles for each signal as the access information history among the number of cycles sequentially input. Next, the access information history accumulating unit 36a outputs the maximum number of cycles for each held signal to the error correction circuit 32a. Here, the maximum cycle number includes the maximum assert cycle number that is the maximum cycle number of the chip select signals CS0_N and CS1_N, the maximum hold cycle number that is the maximum cycle number of the address ADDR, and the like. Further, when “accumulation off”, the access information history accumulating unit 36a does not accumulate the access information history and outputs the maximum number of cycles for each held signal to the error correction circuit 32a.

  In the differential serial transmission device 1-7 of FIG. 7, the access information history accumulating unit 16a receives from the parallel bus interface circuit 11 the counted number of data DATA cycles as in the third embodiment as access information. The access information history accumulation unit 16a performs the following operation for accumulating the access information history in the same manner as the access information history accumulation unit 16 of FIG. That is, when “accumulation is on”, the access information history accumulation unit 16a accumulates the maximum number of cycles of the data DATA as the access information history among the number of cycles of the sequentially input data DATA. Next, the access information history accumulating unit 16a outputs the maximum number of cycles of the held data DATA to the error correction circuit 13a. Further, the access information history accumulating unit 16a does not accumulate the access information history when “accumulation off”, and outputs the maximum number of cycles of the retained data DATA to the error correction circuit 13a.

  According to the differential serial transmission system 10-7 according to the seventh embodiment of the present invention configured as described above, the history accumulation enable registers 17A and 38A are further provided. Here, the history storage enable registers 17A and 38A store a control signal indicating whether or not the access information history storage units 16a and 36a execute the storage of the access information history, and store them in the access information history storage units 16a and 36a. Output.

  According to the said structure, it has an effect similar to the said Embodiment 3. FIG. The access information history accumulation by the access information history accumulation units 16a and 36a can be controlled via the history accumulation enable registers 17A and 38A by a control signal from the CPU. For this reason, for example, a time period in which the entire differential serial transmission system 10-7 is not operating and an error is unlikely to occur can be set as the access history accumulation period. Therefore, the access information history accumulating units 16a and 36a can accumulate the maximum number of cycles as the access information history within an optimum time period in which the transmitted signal is not affected by the error. Therefore, the error correction circuits 13a and 32a can execute an optimum error correction process on the parallel interface signal.

  In the seventh embodiment, the history accumulation enable registers 17A and 38A hold the value of the “accumulation on” or “accumulation off” control signal in accordance with the control signal received from the CPU. However, the present invention is not limited to this, and the history accumulation enable registers 17A and 38A may hold the value of the control signal in accordance with a control signal received from another control circuit or the like that is not limited to the CPU.

Embodiment 8A.
FIG. 8A is a block diagram showing a configuration of a differential serial transmission system 10-8A according to Embodiment 8A of the present invention. In FIG. 8A, the differential serial transmission system 10-8A includes differential serial transmission devices 1-8A and 2-8A. The differential serial transmission system 10-8A is different from the differential serial transmission system 10-3 of FIG. 3 in the following points.
(1) Compared to the differential serial transmission device 1-3, the differential serial transmission device 1-8A includes an error correction circuit 13e instead of the error correction circuit 13, and further includes an error correction enable register 17B. Was it.
(2) The differential serial transmission apparatus 2-8A includes an error correction circuit 32e instead of the error correction circuit 32, and further includes an error correction enable register 38B, as compared with the differential serial transmission apparatus 2-3. Was it.
Hereinafter, differences will be described.

  In FIG. 8A, an error correction enable register 17B determines whether or not to execute error correction processing by the error correction circuit 13e from a CPU (not shown) that controls the memory 6, that is, “error correction on” or “error correction off”. ”Is received and stored. Further, the error correction enable register 38B receives and stores a control signal indicating whether or not to execute error correction processing by the error correction circuit 32e, that is, "error correction on" or "error correction off", from the CPU. . The error correction enable registers 17B and 38B output the stored control signals as error correction enable signals to the error correction circuits 13e and 32e, respectively.

  In the differential serial transmission device 2-8A of FIG. 8A, the error correction circuit 32e receives the parallel interface signal from the serial / parallel conversion circuit 31B. Further, the error correction circuit 32e receives the maximum number of cycles for each signal of the parallel interface signal from the access information history accumulating unit 36 as a prescribed number of cycles for each signal. In the error correction period in which “error correction is turned on”, the error correction circuit 32e does not change the value of each signal of the parallel interface signal for a time period of a specified number of cycles to be input. An error correction process is performed to remove the signal change. Further, when “error correction is off”, the error correction circuit 32 e does not execute the error correction process and outputs the input parallel interface signal to the parallel bus interface circuit 33 as it is.

  In the differential serial transmission device 1-8A of FIG. 8A, the error correction circuit 13e receives a parallel interface signal including data DATA from the serial / parallel conversion circuit 12B. Further, the error correction circuit 13e receives the maximum number of cycles of the data DATA of the parallel interface signal from the access information history storage unit 16 as a specified number of cycles of the data DATA. When “error correction is on”, the error correction circuit 13e removes the change in the data DATA so that the value of the data DATA does not change for a time period of a specified number of cycles of the input data DATA. Perform error correction processing. Further, when “error correction is off”, the error correction circuit 13 e does not execute the error correction process and outputs the input parallel interface signal to the parallel bus interface circuit 11 as it is.

  The differential serial transmission device 10-8A according to the embodiment 8A of the present invention configured as described above further includes error correction enable registers 17B and 38B. Here, the error correction enable registers 17B and 38B store a control signal indicating whether or not the error correction circuits 13e and 32e execute error correction processing, and output the control signals to the error correction circuits 13e and 32e.

  According to the said structure, it has an effect similar to the said Embodiment 3. FIG. In addition, an error correction period that is a time period during which the error correction circuits 13e and 32e execute error correction processing can be set by control by the CPU. For this reason, for example, by executing error correction processing within a time period in which error correction is required because the error occurrence probability is higher than a predetermined threshold value, address ADDR, memory 6 control signal, data DATA, etc. Signal quality can be improved. For example, when the error occurrence probability is lower than a predetermined threshold value, the error correction enable registers 17B and 38B can be set to “error correction off”. As a result, the error correction circuits 13e and 32e can stop the error correction processing during a time period in which error correction is not required, and thus power consumption required for data transmission can be suppressed. In particular, the average power consumption during operation of the differential serial transmission devices 1-8A and 2-8A can be reduced.

  Further, the controller such as a CPU controls the error correction enable registers 17B and 38B so as to exclude a time period during which error correction is unnecessary from the error correction period, thereby preventing a decrease in latency efficiency.

  In the embodiment 8A, the error correction enable registers 17B and 38B are provided in the differential serial transmission system 10-8A. However, the present invention is not limited to this, and in addition to the error correction enable registers 17B and 38B, the history accumulation enable registers 17A and 38A of FIG. 7 of the seventh embodiment may be further provided in the differential serial transmission system 10-8A. Good.

  In the embodiment 8A, the differential serial transmission devices 1-8A and 2-8A include the access information history storage units 16 and 36, respectively. However, the present invention is not limited to this, and the information history storage units 16 and 36 may be deleted in the differential serial transmission devices 1-8A and 2-8A, respectively.

Embodiment 8B.
FIG. 8B is a block diagram showing a configuration of a differential serial transmission system 10-8B according to Embodiment 8B of the present invention. In FIG. 8B, the differential serial transmission system 10-8B includes differential serial transmission devices 1-8B and 2-8B. The differential serial transmission system 10-8B is different from the differential serial transmission system 10-8A of FIG. 8A in the following points.
(1) The differential serial transmission device 1-8B includes the access information history storage unit 16a of FIG. 7 instead of the access information history storage unit 16 as compared with the differential serial transmission device 1-8A. 7 history accumulation enable register 17A.
(2) Compared to the differential serial transmission apparatus 2-8A, the differential serial transmission apparatus 2-8B includes the access information history accumulation unit 36a of FIG. 7 instead of the access information history accumulation unit 36. 7 history accumulation enable register 38A.

  In the differential serial transmission apparatus 2-8B of FIG. 8B, the access information history accumulating unit 36a determines the maximum number of cycles for each signal accumulated according to the control signal input from the CPU via the history accumulation enable register 38A. To 32e. In the differential serial transmission apparatus 1-8B, the access information history storage unit 16a sets the maximum number of cycles of the data DATA stored in accordance with the control signal input from the CPU via the history storage enable register 17A to the error correction circuit 32e. Output.

  FIG. 19A is a timing chart illustrating operations of the differential serial transmission devices 1-8B and 2-8B. In FIG. 19A, when the differential serial transmission system 10-8B is activated, each access information history accumulating unit 16a, 36a starts accumulating access information history, and an access history accumulating period is started. When a predetermined time has elapsed since the activation of the differential serial transmission system 10-8B, the control signal from the CPU is "accumulated off" and the access information history accumulating units 16a and 36a stop accumulating access information history. . At this time, in the error correction circuits 13a and 32a, the control signal from the CPU is “error correction on”, and the error correction circuits 13a and 32a start executing the error correction processing. Thereafter, in the error correction period until the end of the operation of the differential serial transmission system 10-8A, the error correction circuits 13e and 32e execute error correction processing.

  FIG. 19B is another timing chart showing the operations of the differential serial transmission devices 1-8B and 2-8B. In FIG. 19B, when the differential serial transmission system 10-8B is activated, the access information history accumulating units 16a and 36a start accumulating access information history, and an access history accumulating period is started. When a predetermined time has elapsed since the activation of the differential serial transmission system 10-8B, the control signal from the CPU is "error correction turned on", and the error correction circuits 13a and 32a start executing error correction processing. When a predetermined time has passed since the error correction function was turned on, the control signal from the CPU is “accumulated off”, and the access information history accumulating units 16a and 36a stop accumulating access information history. Thereafter, the error correction circuits 13a and 32a execute error correction processing in the access history accumulation period until the operation of the differential serial transmission system 10-8B is completed.

  FIG. 19C is still another timing chart showing the operations of the differential serial transmission devices 1-8B and 2-8B. In FIG. 19C, the differential serial transmission system 10-8B performs the following operation so that “accumulation on” and “error correction on” are alternately repeated at predetermined time intervals. That is, when the differential serial transmission system 10-8B is started up, “accumulation is turned on”, and the access information history accumulating units 16a and 36a start accumulating access information history. When a predetermined time has elapsed since the activation of the differential serial transmission system 10-8B, the access information history accumulating units 16a and 36a stop accumulating access information history when the accumulation is turned off, and the access history accumulation period is Interrupted. At this time, the control signal is “error correction ON”, and the error correction circuits 13a and 32a start executing the error correction processing. When a predetermined time has passed since this time, the control signal is “error correction off”, and the error correction circuits 13a and 32a stop executing the error correction processing. At this time, the control signal is “accumulated on” and the access information history accumulating units 16a and 36a start accumulating the access information history again. As described above, the differential serial transmission system 10-8B alternately repeats “accumulation on” and “error correction on” as described above until the operation of the differential serial transmission system 10-8B ends. Thereby, accumulation of access information history and error correction processing are executed alternately.

  FIG. 19D is still another timing chart showing the operations of the differential serial transmission devices 1-8B and 2-8B. In FIG. 19D, when the differential serial transmission system 10-8B is activated, the control signal is “accumulated on”, and the access information history accumulating units 16a and 36a start accumulating access information history. When a predetermined time has elapsed since the activation of the differential serial transmission system 10-8B, the control signal is “accumulated off”, and the access information history accumulating units 16a and 36a stop accumulating access information history. At this time, the control signal is “error correction ON”, and the error correction circuits 13a and 32a execute error correction processing in the error correction period until the operation of the differential serial transmission system 10-8B is completed. When a predetermined time elapses after the control signal is turned “error correction on”, the control signal is turned “storage on” again, and the access information history storage units 16a and 36a start storing access information history. Thereafter, during the access history storage period, the access information history storage units 16a and 36a intermittently store the access information history at predetermined time intervals during the error correction period until the end of the operation of the differential serial transmission system 10-8B. .

  The differential serial transmission system 10-8B configured as described above has the same operational effects as those of the seventh embodiment and the eighth embodiment. Further, the access history accumulation period and the error correction period can be independently controlled by the CPU and the external circuit.

Embodiment 9. FIG.
FIG. 9 is a block diagram showing a configuration of a differential serial transmission system 10-9 according to the ninth embodiment of the present invention. In FIG. 9, the differential serial transmission system 10-9 includes differential serial transmission devices 1-3 and 2-9. The differential serial transmission system 10-9 is different from the differential serial transmission system 10-3 of FIG. 1 in the following points.
(1) The differential serial transmission device 2-9 is different from the differential serial transmission device 2-3 in FIG. 3 in that it replaces the access information history storage unit 36 with the WE access information history storage unit 36W and the RE access. An information history storage unit 36R is provided, and an error correction circuit 32f is provided instead of the error correction circuit 32a.
Hereinafter, differences will be described.

  In the differential serial transmission device 2-9 of FIG. 9, the parallel bus interface circuit 33 separates the received parallel interface signal into data DATA, an address ADDR, and a control signal, and outputs them to the memory 6. At this time, the parallel bus interface circuit 33 counts the number of cycles in a time period in which each signal such as the chip select signals CS0_N and CS1_N and the address ADDR included in the parallel interface signal has a constant value. When the write enable signal WE_N is asserted, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the WE access information history storage unit 36W as WE access information. Further, when the read enable signal RE_N is asserted, the parallel bus interface circuit 33 outputs the number of cycles counted for each signal to the RE access information history accumulating unit 36R as RE access information.

  The WE access information history accumulating unit 36W performs the following operation in order to accumulate the maximum cycle number for each signal as the WE access information history among the cycle numbers sequentially input. That is, the WE access information history accumulating unit 36W compares the number of cycles input for each signal with the maximum number of cycles held, and the number of cycles input exceeds the maximum number of cycles held. When it is larger, the input cycle number is updated as the maximum cycle number. On the other hand, the WE access information history accumulating unit 36W does not perform update for each signal when the number of cycles input is equal to or less than the maximum number of cycles held. The WE access information history accumulating unit 36W outputs the held maximum number of cycles for each signal to the error correction circuit 32f. Here, the maximum cycle number includes, for example, the maximum assert cycle number of the chip select signals CS0_N and CS1_N, the maximum hold cycle number of the address ADDR, and the like.

  The RE access information history storage unit 36R has the same configuration as the WE access information history storage unit 36W. The RE access information history accumulating unit 36R operates in the same manner as the WE access information history accumulating unit 36W, and sets the maximum number of cycles for each signal among the numbers of cycles in the sequentially input RE access information. Accumulated as access information history. The RE access information history accumulating unit 36R outputs the maximum number of cycles for each signal, which is the stored RE access information history, to the error correction circuit 32f.

  The error correction circuit 32f receives the maximum number of cycles for each signal of the parallel interface signal from each of the WE access information history storage unit 36W and the RE access information history storage unit 36R. When the write enable signal WE_N included in the input parallel interface signal is asserted, the error correction circuit 32f uses the maximum number of cycles for each signal of the received WE access information history to perform error correction as follows. Execute the process. That is, in this case, the error correction circuit 32f changes the value of each signal of the parallel interface signal so that the value does not change only for the time period of the maximum number of cycles received from the WE access information history storage unit 36W. Execute error correction processing to remove. When the read enable signal RE_N included in the input parallel interface signal is asserted, the error correction circuit 32f uses the maximum number of cycles for each signal of the received RE access information history as follows. Perform error correction processing. That is, in this case, the error correction circuit 32f sets the value of each value of the parallel interface signal so that the value does not change only for the time period of the maximum number of cycles received from the RE access information history storage unit 36R. Execute error correction processing to remove changes. The error correction circuit 32 f outputs the error-corrected parallel interface signal to the parallel bus interface circuit 33.

  The differential serial transmission system 10-9 according to the ninth embodiment of the present invention configured as described above has the same operational effects as those of the third embodiment. Further, the WE access information history accumulating unit 36W and the RE access information history accumulating unit 36R accumulate access histories for writing and reading access, respectively. Therefore, the WE access information history storage unit 36W and the RE access information history storage unit 36R can determine the prescribed number of cycles for error correction processing according to the type of access. Therefore, the error correction circuit 36f can change the timing and method of serial error correction for each such access type (write, read), and can execute an optimum error correction process for each access type. .

Embodiment 10 FIG.
FIG. 10 is a block diagram showing a configuration of a differential serial transmission system 10-10 according to the tenth embodiment of the present invention. In FIG. 10, the differential serial transmission system 10-10 includes differential serial transmission devices 1-10 and 2-10. The differential serial transmission system 10-10 differs from the differential serial transmission system 10-7 of FIG. 7 in the following points.
(1) The history accumulation enable registers 17A and 38A are deleted.
Hereinafter, differences will be described.

  In FIG. 10, the access information history storage unit 36a in the differential serial transmission apparatus 2-10 receives "storage on" or "storage off" from an external circuit (not shown) instead of the history storage enable register 38A of FIG. A history accumulation enable signal indicating the above is received. Further, in the differential serial transmission apparatus 1-10, the access information history storage unit 16a receives a history storage enable indicating “storage on” or “storage off” from an external circuit instead of the history storage enable register 17A of FIG. Receive a signal.

  As shown in the timing charts of FIGS. 19A to 19D, for example, the access information history accumulating units 16a and 36a store the access information history according to the control on the access information history accumulating units 16a and 36a by the history accumulation enable signal from an external circuit, for example. Perform accumulation.

  According to the differential serial transmission system 10-10 according to the tenth embodiment of the present invention configured as described above, the access information history accumulation units 16a and 36a receive the history accumulation enable signal. Here, the history storage enable signal indicates whether or not the access information history storage units 16a and 36a execute access information history storage. The access information history storage units 16a and 36a control the execution of access information history storage based on the history storage enable signal.

  According to the said structure, it has the same effect as Embodiment 3. The access information history accumulating units 16a and 36a can accumulate the maximum number of cycles of each signal as the access information history in a time period in which the error occurrence probability is lower than a predetermined threshold, for example, according to control from the external circuit. Therefore, the error correction circuits 13a and 32a can execute an optimum error correction process on the parallel interface signal.

  In the tenth embodiment, the access information history storage units 16 and 36 receive a history storage enable signal from an external circuit. However, the present invention is not limited to this. For example, the access information history storage units 16A, 16B, 36A, 36B in FIG. 5, the access information history storage units 16C, 16D, 36C, 36D in FIG. 6, or the access information history in FIG. The storage unit access information history storage units 16R, 16W, 36R, and 36W may receive a history storage enable signal from an external circuit and control execution of access information history storage based on the history storage enable signal. .

Embodiment 11. FIG.
FIG. 11 is a block diagram showing a configuration of a differential serial transmission system 10-11 according to the eleventh embodiment of the present invention. In FIG. 11, the differential serial transmission system 10-11 includes differential serial transmission devices 1-11, 11-11. The differential serial transmission system 10-11 differs from the differential serial transmission system 10-8A of FIG. 8A in the following points.
(1) The error correction enable registers 17B and 38B are deleted.
Hereinafter, differences will be described.

  In FIG. 11, an error correction circuit 32e in the differential serial transmission apparatus 2-11 receives an error correction indicating whether “error correction is on” or “error correction is off” from an external circuit instead of the error correction enable register 38B in FIG. 8A. Receive an enable signal. In the differential serial transmission apparatus 1-11, the error correction circuit 13e receives an error correction enable signal indicating whether the error correction is on or error correction off from an external circuit instead of the error correction enable register 17B in FIG. 8A. Receive a signal.

  For example, as shown in the timing charts of FIGS. 19A to 19D, the error correction circuits 13e and 32e execute error correction processing according to control by an error correction enable signal from an external circuit, for example.

  According to the differential serial transmission system 10-11 according to the eleventh embodiment of the present invention configured as described above, the error correction circuits 13e and 32e receive the error correction enable signal. Here, reception of the error correction enable signal indicates whether or not the error correction circuits 13e and 32e execute error correction processing. The error correction circuits 13e and 32e control the execution of error correction processing based on the error correction enable signal.

  According to the said structure, it has an effect similar to the said Embodiment 3. FIG. Further, the error correction circuits 13e and 32e can execute error correction processing according to an error correction enable signal from an external circuit, for example, when the error occurrence probability is higher than a predetermined threshold value. As a result, the signal quality of the parallel interface signal can be kept good in the error correction circuits 13 and 32 within a time period in which error correction is necessary. Furthermore, the power consumption for the operation of the differential serial transmission devices 1-11, 11-11 can be suppressed within a time period that does not require error correction.

  In the eleventh embodiment, the error correction circuits 13 and 32 in FIG. 11 execute error correction processing in accordance with an error correction enable signal from an external circuit. However, the present invention is not limited to this, and the error correction circuits of FIGS. 1 to 7, 8A, 8B, 9 and 10 may be configured to execute error correction processing in accordance with an error correction enable signal from an external circuit.

Embodiment 12 FIG.
FIG. 12 is a block diagram showing a configuration of the differential serial transmission devices 1-12 and 2-12 according to the twelfth embodiment of the present invention. In FIG. 12, the differential serial transmission system 10-12 includes differential serial transmission devices 1-12 and 2-12. 12, the differential serial transmission system 10-12 according to the twelfth embodiment is different from the differential serial transmission system 10-7 in FIG. 7 in the following points.
(1) The differential serial transmission device 1-12 further includes a selector 16M between the history storage enable register 17A and the access information history storage unit 16a as compared with the differential serial transmission device 1-7.
(2) The differential serial transmission device 2-12 further includes a selector 36M between the history storage enable register 38A and the access information history storage unit 36a, as compared with the differential serial transmission device 2-7.
Hereinafter, differences will be described.

  In the differential serial transmission device 2-12 of FIG. 12, the selector 36M receives a control signal from the history accumulation enable register 38A and a history accumulation enable signal from an external circuit (not shown). The selector 36M selectively selects one of the control signal from the history accumulation enable register 38A and the history accumulation enable signal from the external circuit based on the selection control signal transmitted from the CPU that controls the memory 6. To the access information history accumulating unit 36a.

  In the differential serial transmission apparatus 1-12 of FIG. 12, the selector 16M receives a control signal from the history accumulation enable register 17A and a history accumulation enable signal from an external circuit. The selector 16M selectively accesses one of the control signal from the history accumulation enable register 17A and the history accumulation enable signal from the external circuit based on the selection control signal transmitted from the CPU. The information is output to the information history storage unit 16a.

  As described above, the access information history accumulating units 16a and 36a accumulate the access information history according to the signals from the selectors 16M and 36M, as shown in the timing charts of FIGS. 19A to 19D, for example.

  The differential serial transmission system 10-12 according to the twelfth embodiment of the present invention configured as described above further includes selectors 16M and 36M. The selectors 16M and 36M are provided between the history storage enable registers 17A and 38A and the access information history storage units 16a and 36a, respectively. Each of the selectors 16M and 36M selectively accesses one of the control signal from the history accumulation enable registers 17A and 38A and the history accumulation enable signal from the external circuit according to the input selection control signal. The data is output to the storage units 16a and 36a.

  According to the above configuration, one of the signals from the history accumulation enable registers 17A and 38A and the history accumulation enable signal input from the external circuit via a signal line of a different system from the external circuit is accessed. Whether to output to the information history storage units 16 and 36 can be selected. As a result, the access information history accumulating units 16 and 36 can accumulate an access information history that is more suitable for error correction processing than the seventh embodiment.

Embodiment 13. FIG.
FIG. 13 is a block diagram showing a configuration of a differential serial transmission system 10-13 according to the thirteenth embodiment of the present invention. In FIG. 13, the differential serial transmission system 10-13 includes differential serial transmission devices 1-13 and 2-13. 13, the differential serial transmission system 10-13 according to the thirteenth embodiment is different from the differential serial transmission system 10-8A in FIG. 8A in the following points.
(1) The differential serial transmission device 1-13 further includes a selector 16N between the error correction enable register 17B and the error correction circuit 13e as compared with the differential serial transmission device 1-8A.
(2) The differential serial transmission device 2-13 further includes a selector 36N between the error correction enable register 38B and the error correction circuit 32e, as compared with the differential serial transmission device 2-8A.
Hereinafter, differences will be described.

  In the differential serial transmission device 2-13 of FIG. 13, the selector 36N receives a control signal from the error correction enable register 38B and an error correction enable signal from an external circuit (not shown). The selector 36N selects one of the control signal from the error correction enable register 38B and the error correction enable signal from the external circuit based on a selection control signal transmitted from the CPU that controls the memory. Is output to the error correction circuit 32e.

  In the differential serial transmission apparatus 1-13 in FIG. 13, the selector 16N receives a control signal from the error correction enable register 17B and an error correction enable signal from an external circuit. The selector 16N selectively performs error correction on either one of the control signal from the error correction enable register 17B and the error correction enable signal from the external circuit based on the selection control signal transmitted from the CPU. Output to the circuit 13e.

  As described above, the error correction circuits 13e and 32e respectively accumulate access information histories according to the signals from the selectors 16N and 36N, as shown in the timing charts of FIGS. 19A to 19D, for example.

  The differential serial transmission system 10-13 according to the thirteenth embodiment of the present invention configured as described above further includes selectors 16N and 36N. The selectors 16N and 36N are provided between the error correction enable registers 17B and 38B and the error correction circuits 13e and 32e, respectively. Each of the selectors 16N and 36N selectively selects one of the control signal from the error correction enable registers 17B and 38B and the error correction enable signal from the external circuit according to the selection control signal. , 32e.

  According to the above configuration, either the signal from the error correction enable register 17B, 38B or the error correction enable signal input from the external circuit via a signal line different from the serial signal is used for error correction. Whether to output to the circuits 13 and 32 can be selected. For this reason, for example, the error correction period can be controlled at a desired timing.

  In the thirteenth embodiment, the error correction circuits 13 and 32 are, for example, within a time period in which the error occurrence probability is higher than a predetermined threshold according to the error correction enable registers 17B and 38B or an error correction enable signal from the outside. Error correction processing can be executed. Therefore, power consumption can be suppressed by stopping the operation of the error correction circuits 13 and 32 during a time period in which error correction is not required.

  Further, the error correction period is set to ON or OFF, for example, at a desired timing by an error correction enable signal from the error correction enable registers 17B and 38B or an external circuit. Therefore, accumulation can be performed in an optimum section corresponding to the current software load state and communication state, and optimum error correction can be performed.

  In the thirteenth embodiment, the selectors 16N and 36N are provided in the differential serial transmission system 10-13. However, the present invention is not limited to this, and the selectors 16N and 36N are connected to the differential serial transmission systems 10-3, 10-5 to 10-7 shown in FIGS. , 10-8A, 10-8B, 10-9, 10-10, and 10-12.

1-1 to 1-4, 1-7, 1-8A, 1-8B, 1-10 to 1-13, 2-1 to 2-7, 2-8A, 2-8B, 2-9 to 2- 13 ... Differential serial transmission device,
3, 4 ... differential serial transmission line,
5 ... Memory controller,
6 ... Memory,
6a, 6b ... chip,
7a, 8a ... data bus,
7b, 8b ... Address bus,
7c, 8c ... control signal bus,
10-1 to 10-7, 10-8A, 10-8B, 10-9 to 10-13... Differential serial transmission system,
11, 33 ... parallel bus interface circuit,
12A, 31A ... parallel-serial conversion circuit,
12B, 31B ... serial parallel conversion circuit,
13, 13a, 13e, 32, 32a, 32c to 32e ... error correction circuit,
13A, 32A ... access setting register,
13b, 32b ... error correction circuit for each signal line,
14, 35 ... Transmission differential driver,
15, 34 ... reception differential receiver,
16, 16a, 36, 36a ... access information history storage unit,
16M, 16N, 36M, 36N ... selector,
16R, 36R ... RE access information history storage unit,
16W, 36W... WE access information history storage unit,
16A, 36A ... access information history for CS0,
16B, 36B ... access information history for CS1,
16C, 36C ... AS0 access information history storage unit,
16D, 36D... AS1 access information history storage unit,
17A, 38A ... History accumulation enable register,
17B, 38B: Error correction enable register.

JP 2002-116961 A

Claims (9)

A serial-parallel conversion circuit for serial-parallel conversion of serial signals into parallel signals;
A serial transmission device comprising an error correction circuit that performs error correction processing on the parallel signal,
The error correction circuit performs error correction on the parallel signal by executing an error correction process for removing a change in the value of the parallel signal so that the value of the parallel signal does not change for a predetermined time period. Output parallel signal ,
The serial transmission device further includes
A parallel bus interface circuit that performs predetermined signal conversion on the error-corrected parallel signal and outputs the parallel signal, and measures the time period in which the value of the error-corrected parallel signal is constant, A parallel bus interface circuit that outputs a time period;
An access information history storage unit that stores the maximum time period as an access information history in the timed time period and outputs the access information history to the error correction circuit;
The error correction circuit executes an error correction process for removing the change in the value of the parallel signal so that the value of the parallel signal does not change only for the maximum time period with respect to the parallel signal subjected to the serial-parallel conversion. A serial transmission device characterized by that. The access information history storage unit further includes a history storage enable register that stores a control signal indicating whether or not to execute the storage of the access information history and outputs the control signal to the access information history storage unit. The serial transmission device according to claim 1 . A control signal from the history storage enable register and a history storage enable signal input from an external circuit according to a selection control signal provided between the history storage enable register and the access information history storage unit. 3. The serial transmission device according to claim 2 , further comprising a first selector that selectively outputs any one of the signals to the access information history storage unit. The error correction circuit stores a control signal indicating whether to perform the error correction process, according to claim 1 to 3, characterized in that further comprising an error correction enable register to be output to the error correction circuit The serial transmission apparatus as described in any one of them. Any one of a control signal from the error correction enable register and an error correction enable signal input from an external circuit is provided between the error correction enable register and the error correction circuit and is input according to a selection control signal input. 5. The serial transmission device according to claim 4 , further comprising a second selector for selectively outputting one of the signals to the error correction circuit. The access information history storage unit receives a history storage enable signal that is input from an external circuit and indicates whether the access information history storage unit executes the storage of the access information history. serial transmission apparatus of claim 1 for controlling execution of storing the access information history based on the history accumulation enable signal.   2. The serial transmission apparatus according to claim 1, further comprising an access setting register that holds the predetermined time period and outputs the held time period to the error correction circuit. The error correction circuit receives an error correction enable signal input from an external circuit , the error correction enable signal indicating whether or not the error correction circuit executes the error correction processing, and the error correction enable signal The serial transmission device according to claim 1, wherein execution of the error correction processing is controlled based on the information. A first serial transmission device for transmitting a predetermined serial signal;
A serial transmission system comprising: the serial transmission device according to any one of claims 1 to 8 , wherein the second serial transmission device receives the transmitted serial signal.

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