CN116980362B - Multitasking method and device for SPI architecture - Google Patents
Multitasking method and device for SPI architecture Download PDFInfo
- Publication number
- CN116980362B CN116980362B CN202311241240.6A CN202311241240A CN116980362B CN 116980362 B CN116980362 B CN 116980362B CN 202311241240 A CN202311241240 A CN 202311241240A CN 116980362 B CN116980362 B CN 116980362B
- Authority
- CN
- China
- Prior art keywords
- data
- transmitted
- sequence
- sequence data
- priority
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000005540 biological transmission Effects 0.000 claims abstract description 135
- 238000012545 processing Methods 0.000 claims description 44
- 230000001960 triggered effect Effects 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 14
- 238000004891 communication Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 238000004590 computer program Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/6275—Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2425—Traffic characterised by specific attributes, e.g. priority or QoS for supporting services specification, e.g. SLA
- H04L47/2433—Allocation of priorities to traffic types
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
Abstract
The application relates to the technical field of data transmission and discloses a multitasking method for an SPI architecture. Under the condition that a data transmission instruction sent by an external trigger source is received, determining the priority stored in a register corresponding to sequence data to be transmitted; determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted; and sending each task to be sent to the corresponding chip selection device. According to the data transmission instruction of the external trigger source, the priority stored in the register corresponding to the transmission sequence number is directly read, data transmission is carried out based on the priority, priority judgment and data transmission are carried out only through hardware, the problem that hardware is frequently interrupted due to the fact that the priority judgment is carried out through software is avoided, the load rate of a processor is effectively reduced, and the data transmission efficiency is improved. The application also discloses a multitasking device for SPI architecture.
Description
Technical Field
The present disclosure relates to the field of data communication technologies, for example, to a method and an apparatus for processing multiple tasks in an SPI architecture.
Background
The software architecture of the automobile controller is mostly developed based on an automobile open system architecture (Automotive Open System Architecture, AUTOSAR), in which an SPI (Serial Peripheral Interface ) driver is abstracted into a data structure of a Sequence (Sequence), a task (Job) and a Channel (Channel), and a series of operations of the SPI are set as a Sequence, one Sequence contains one or more Job(s) therein, and one Job contains one or more Channel(s). For one Sequence may be set to an internal Job that allows higher priority Sequence inserted Job after completion of execution.
In the related art, software is required to perform priority judgment on data to be transmitted, and then send sequence data with higher priority.
In the process of implementing the embodiment of the present application, it is found that at least the following problems exist in the related art:
the judgment of the priority of the software is realized by relying on hardware SPI interruption, and in the scene of high real-time performance, frequent interruption and software scheduling can increase the running burden of the system, thereby reducing the transmission efficiency of the data transmission system.
It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.
The embodiment of the application provides a multitasking method and device for SPI architecture, so as to improve data transmission efficiency.
In some embodiments, the method comprises: under the condition that a data transmission instruction sent by an external trigger source is received, determining the priority stored in a register corresponding to sequence data to be transmitted; determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted; and sending each task to be sent to the corresponding chip selection device.
Optionally, the method further comprises: under the condition of receiving the newly added sequence data, comparing the priority of the newly added sequence data with the priority of the current sequence data to obtain a comparison result of the priority; the current sequence data is sequence data sent at the current moment; and determining a task to be transmitted at the next moment according to the comparison result.
Optionally, determining the task to be sent at the next moment according to the comparison result includes: under the condition that the comparison result represents that the priority of the newly added sequence data is higher than the priority of the current sequence data, determining that the task to be sent at the next moment is all the tasks to be sent in the newly added sequence data; and under the condition that the comparison result indicates that the priority of the current sequence data is higher than that of the newly added sequence data, determining that the task to be sent at the next moment is the task to be sent which is not sent in the current sequence data.
Optionally, the method further comprises: before comparing the priority of newly added sequence data with the priority of current sequence data, determining whether the current transmission task is completed; and after the current sending task is completed, comparing the priority of the newly added sequence data with the priority of the current sequence data.
Optionally, determining the sequence data to be transmitted further comprises: acquiring address information contained in a data transmission instruction; and reading data corresponding to the address information from the memory as sequence data to be transmitted according to the address information contained in the data transmission instruction.
Optionally, the method further comprises: receiving data to be written sent by chip selection equipment; and writing the data to be written into the memory according to the chip selection information of the data to be written.
In some embodiments, the apparatus comprises: the priority determining module is configured to determine the priority stored in the register corresponding to the sequence data to be transmitted under the condition that a data transmission instruction transmitted by an external trigger source is received; the to-be-transmitted task determining module is configured to determine to-be-transmitted tasks in each to-be-transmitted sequence data according to the sequence from high to low of the priority stored in the register corresponding to the to-be-transmitted sequence data; and the sending module is configured to send each task to be sent to the corresponding chip selection device.
In some embodiments, the apparatus comprises: a data transmission channel, a data processing unit and a serial data interface unit, wherein: the data transmission channel is connected with the data processing unit and is configured to send sequence data to be sent to the data processing unit under the condition that a data sending instruction sent by an external trigger source is received; a data processing unit, connected with the serial data interface unit, configured to: receiving sequence data to be transmitted, and determining the priority stored in a register corresponding to the sequence data to be transmitted; determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted; and the serial data interface unit is connected with the plurality of chip selection devices and is configured to receive the task to be sent and send the task to be sent to the corresponding chip selection device.
In some embodiments, the controller comprises: a controller main body; the above-described multitasking device for SPI architecture is mounted to the controller main body.
The multitasking method and device for SPI architecture provided by the embodiment of the application can realize the following technical effects:
according to the data transmission instruction of the external trigger source, the priority stored in the register corresponding to the transmission sequence number is directly read, data transmission is carried out based on the priority, priority judgment and data transmission are carried out only through hardware, the problem that hardware is frequently interrupted due to the fact that priority judgment is carried out through software is avoided, the load rate of a processor is effectively reduced, and the data transmission efficiency is improved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:
FIG. 1 is a schematic diagram of a transmission task in an AUTOSAR architecture;
FIG. 2 is a flow chart of a method for serial data transmission by software in the related art;
FIG. 3 is a flowchart of a method for performing multi-tasking on SPI architecture according to one embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of a multi-task processing device for SPI architecture according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a configuration of a further multi-tasking device for SPI architecture according to one embodiment of the present disclosure;
fig. 6 is a schematic diagram of a multi-task processing device for SPI architecture in a practical application scenario provided in the present embodiment;
FIG. 7 is a schematic diagram of a multi-tasking device for SPI architecture according to one embodiment of the present disclosure;
FIG. 8 is a schematic diagram of another multi-tasking device for SPI architecture provided by an embodiment of the present application;
fig. 9 is a schematic diagram of a controller according to an embodiment of the present application.
Detailed Description
For a more complete understanding of the features and technical content of the embodiments of the present application, reference should be made to the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings, which are for purposes of illustration only and not intended to limit the embodiments of the present application. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.
The terms first, second and the like in the description and in the claims of the embodiments and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present application described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The term "plurality" means two or more, unless otherwise indicated.
In the embodiment of the present application, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.
The serial peripheral interface (Serial Peripheral Interface, SPI) is widely used in automotive controllers, such as control power chips, transceiver chips, and high-low side drive chips, and thus the SPI controller is commonly implemented in mainstream automotive microcontroller chips. The SPI controller mainly realizes SPI protocol, namely serial-parallel conversion transmitting and receiving of data, software or DMA writes data into a transmitting shift register during transmitting, the data is serially output onto a data bus, serial data on the data bus is converted into data with specified bit width during receiving, the data is stored in a receiving data register, and the corresponding data is read by the software or the DMA.
The software architecture of the automobile controller is mostly developed based on the automobile open system architecture (Automotive Open System Architecture, AUTOSAR). Fig. 1 is a schematic diagram of a transmission task in an AUTOSAR architecture. In the AUTOSAR architecture, an SPI driver is abstracted into a data structure of a Sequence (Sequence), a task (Job) and a Channel (Channel), and a series of SPI operations are set into one Sequence, wherein one Sequence internally comprises one or more Jobs, and one Job comprises one or more channels. For one Sequence may be set to an internal Job that allows higher priority Sequence inserted Job after completion of execution. As shown in fig. 2, in the related art, when processing different priority sending tasks by software, the existing SPI controller architecture needs to determine the priority of the current transmitting task by software after each Job ends, and the Job in the Sequence with the highest priority is sent. Judging the current task priority through software needs to be realized by relying on hardware SPI interrupt, but the number of hardware interrupts is strictly limited in a scene with high real-time performance such as a chassis, and frequent software scheduling SPI tasks can increase the running load of a system.
Based on this, the embodiment of the application provides a serial data transmission method and a controller architecture supporting hardware transmission task priority scheduling, and based on supporting a general SPI protocol, each Job can automatically transmit the Job of the highest priority Sequence in the current task to be transmitted after the completion of Job transmission through a Job priority processing module of AUTOSAR. Supporting hardware triggering, the serial data transmission controller (i.e., SPI controller) can automatically carry sequences stored in the memory to the shift register. The system load generated by software scheduling is reduced and the system operation efficiency is improved while the periodic SPI task scheduling is realized.
In conjunction with fig. 3, an embodiment of the present application provides a method for processing multiple tasks in an SPI architecture, where the method is applied to a multi-task processing controller in the SPI architecture, and a schematic diagram of a serial data transmission controller is shown in fig. 4, where one end of the serial data transmission controller is connected to a memory, and the other end of the serial data transmission controller is connected to a plurality of chip selection devices, and in a data transmission stage, the serial data transmission controller reads data to be transmitted in a specified location in the memory, determines a transmission sequence after processing, and transmits the data to the corresponding chip selection devices. In the data receiving stage, the serial data transmission controller receives data to be written sent by the chip selection device and writes the data to be written into the memory. As shown in fig. 3, the method specifically includes:
s301: and under the condition that a data transmission instruction sent by an external trigger source is received, determining the priority stored in a register corresponding to the sequence data to be transmitted.
Wherein the external trigger source is a trigger source for triggering related processing instructions through hardware, such as a timer. The serial data transmission controller may receive a data transmission instruction when the set time of each timer has arrived, so as to trigger transmission and/or reception of serial data.
S302: and determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted.
The priority of the Sequence data sequences is stored in a register, specifically, the priority of each Sequence can be identified by a three-bit binary number, which characterizes the priorities of 0-6, with the lowest priority corresponding to number 0 and the highest priority corresponding to number 6. Of course, other manners may be adopted for setting the priority according to the user requirement, and the embodiment of the present application does not limit the specific form of the priority.
S303: and sending each task to be sent to the corresponding chip selection device.
Each Sequence includes one or more jobs therein, each Job stored in a buffer. As an example, each Job's corresponding data structure occupies 32 bits, where 16 bits are the data itself and the other 16 bits are configuration information including the timing format of the Job data currently being transmitted, including the corresponding chip select signal, sampling edges, data bit width, data size end, etc.
Specifically, each Sequence data (Sequence) includes one or more tasks (jobs) to be sent, and the priorities of all jobs are the same as those of the sequences to which the jobs belong, that is, the priorities of all jobs in the same Sequence are the same, so after determining the Sequence with the highest priority, all jobs in the Sequence are sent in turn.
According to the method provided by the embodiment of the application, the priority stored in the register corresponding to the transmission sequence number is directly read according to the data transmission instruction of the external trigger source, and data transmission is performed based on the priority, and priority judgment and data transmission are performed only through hardware, so that the problem that hardware is frequently interrupted due to the fact that the priority judgment is performed by means of software is avoided, the load rate of a processor is effectively reduced, and the data transmission efficiency is improved.
Optionally, before determining the priority of the register storage corresponding to the sequence data to be sent, the method further includes: and reading data corresponding to the address information from the memory as data to be transmitted according to the address information contained in the data transmission instruction.
Optionally, the method further comprises: under the condition of receiving the newly added sequence data, comparing the priority of the newly added sequence data with the priority of the current sequence data to obtain a comparison result of the priority; the current sequence data is sequence data sent at the current moment; and determining a task to be transmitted at the next moment according to the comparison result.
Specifically, in a period, new sequence data is also received, for example, the external trigger source is a timer triggered every 5ms, when 5ms arrives, the existing sequence data is S1, S2, S3, where the priority of S3 is highest, the priority of S1 is second lowest, and after comparing the priorities of S1, S2 and S3, it is determined that the sending order of the sequence data is from high to low, that is, S3, S1 and S2. All jobs in S3 are sent first in turn, all jobs in S1 are sent again, and all jobs in S2 are sent last. However, in the process of transmitting jobs, new Sequence data S4 is received, and since each Job cannot be interrupted in the process of transmitting, after the current Job is transmitted, the priorities of the new S4 and the currently transmitted sequences are determined, and according to the comparison result, it is determined which Job in the Sequence is the next Job to be transmitted. Therefore, the task to be processed is guaranteed to be the task with the highest priority at each moment, and the accuracy of data transmission is guaranteed.
Optionally, the method further comprises: before comparing the priority of newly added sequence data with the priority of current sequence data, determining whether the current transmission task is completed; and after the current sending task is completed, comparing the priority of the newly added sequence data with the priority of the current sequence data.
Specifically, since the Job in the current transmission cannot be interrupted, priority comparison needs to be performed after the current Job is transmitted, and the transmission time of the current Job can be determined according to the data length. Therefore, the priority can be judged again without interrupting Job in transmission, data transmission errors caused by interruption of Job are avoided, and the accuracy of data transmission is improved.
Optionally, determining the task to be sent at the next moment according to the comparison result includes: and under the condition that the comparison result indicates that the priority of the newly added sequence data is higher than that of the current sequence data, determining the task to be sent at the next moment as all the tasks to be sent in the newly added sequence data. And under the condition that the comparison result indicates that the priority of the current sequence data is higher than that of the newly added sequence data, determining that the task to be sent at the next moment is the task to be sent which is not sent in the current sequence data.
Continuing the previous example, if the Sequence to which the Job currently transmitted belongs is S2, comparing the priorities of the newly added S4 and S2 after the current Job is transmitted, if the comparison result shows that the priority of the newly added S4 is higher than that of the newly added S2, not continuing to transmit the rest of Jobs in S2, transmitting all Jobs in S4, and after all Jobs in S4 are transmitted, transmitting the rest of Jobs in S2.
If the comparison result indicates that the priority of S2 is higher than the priority of newly added S4, then Job remaining in S2 continues to be sent.
Therefore, the data transmitted at present can be guaranteed to be the data with the highest priority all the time, and the accuracy of data transmission is further improved.
It should be noted that, after all sequences are sent in one timing period, the data transmission task in the timing period is completed.
Optionally, determining the sequence data to be transmitted further comprises: acquiring address information contained in a data transmission instruction; and reading data corresponding to the address information from the memory as sequence data to be transmitted according to the address information contained in the data transmission instruction.
In the actual working process, software or DMA can write the transmission data into the memory, and read the data from the memory through the data transmission channel and store the data in the transmission buffer queue. The data bit width of the TxFIFO is 32 bits, and the high 16 bits of the TxFIFO data are set as control bits in order to support the application scenario of the AUTOSAR. The time sequence format of the current transmitted data is controlled, and the time sequence format comprises a corresponding chip selection signal, a sampling edge, a data bit width, a data size end, whether the data is forbidden after the transmission is completed or not and the like. The other 16 bits store the data itself. And meanwhile, supporting a Job mode, wherein software can configure the transmission data length of the current Job, and hardware can configure a trigger interrupt after judging that Job transmission is completed.
Optionally, the method further comprises: receiving data to be written sent by chip selection equipment; and writing the data to be written into the memory according to the chip selection information of the data to be written.
In specific operation, in combination with the Job mode of the SPI controller, a user stores data to be transmitted into the RAM of the system through software (e.g., APP), configures an external trigger source, e.g., configures a timer triggered by a period of 5ms, each timer triggers a Sequence transmission of the SPI once, a transmission channel corresponding to the data transmission channel 601 loads data in the RAM into a Sequence transmission buffer according to a configured address, and the priority processing module 6023 determines priorities of all sequences currently cached, determines a Sequence with the highest priority, and transmits all Job in the Sequence. For example, the external trigger source is set to be a timer with a period of 5ms, after reaching 5ms, data corresponding to the configured address is read to the Sequence sending buffer, that is, four sequences of S1, S2, S3 and S4 are read, and Job in S2 is sent in Sequence after judging that the priority of the four sequences is highest in the current Sequence is S2. Each Job transmission is completed, it is automatically detected whether the currently transmitted Sequence is the highest priority in the Sequence transmission buffer, if not, the Job of the highest priority Sequence is transmitted, and if the current Sequence is the highest priority, the remaining Job in the Sequence is continuously transmitted. If all Sequence transmissions are complete, the Idle state is restored. Similarly, the Sequence receiving buffer area can select a receiving channel in the data transmission channel 601 according to the chip selection information corresponding to the current transmission data to store the data into the system RAM of the corresponding address, and the whole data transmission process can realize periodical SPI Sequence triggering and task scheduling without the participation of software. The receiving Sequence and the sending Sequence are supported not by software, but by periodic triggering of a timer, and the hardware interrupt is not relied on, so that the load rate of a CPU is effectively reduced.
Referring to fig. 5, a multi-task processing device 500 for SPI architecture according to an embodiment of the present application includes a data transmission channel 501, a data processing unit 502, and a serial data interface unit 503, where:
a data transmission channel 501 connected to the data processing unit 502 and configured to transmit sequence data to be transmitted to the data processing unit 502 when receiving a data transmission instruction transmitted by an external trigger source;
a data processing unit 502, connected to the sequence data interface unit 503, configured to:
receiving sequence data to be transmitted, and determining the priority stored in a register corresponding to the sequence data to be transmitted;
determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted;
the serial data interface unit 503 is connected to the plurality of chip selection devices, and is configured to receive the task to be sent, and send the task to be sent to the corresponding chip selection device.
According to the multitasking device for the SPI architecture, which is provided by the embodiment of the application, according to the data transmission instruction of the external trigger source, the priority stored in the register corresponding to the transmission sequence number is directly read, data transmission is carried out based on the priority, priority judgment and data transmission are carried out only through hardware, the problem that hardware is frequently interrupted due to the fact that the priority judgment is carried out by means of software is avoided, the load rate of a processor is effectively reduced, and the data transmission efficiency is improved.
Referring to fig. 6, a multi-task processing device 600 for SPI architecture in a practical application scenario is provided. The right half of fig. 6 implements the data serial-parallel conversion function required by the generic SPI protocol. 8 chip select devices are supported in the master mode, and each chip select device can independently set a data communication format.
In the multitasking device 600 for SPI architecture in fig. 6, a data transmission channel 601, a data processing unit 602, and a serial data interface unit 603 are included, and the secondary modules included in each module and the functional description of each module are shown in table 1 below.
TABLE 1
Optionally, the data transmission channel 601 includes a data transmission channel; the reading and sending the sequence data to be sent from the memory comprises the following steps: the data transmission channel reads data corresponding to the address information from the memory as data to be transmitted according to the address information contained in the data transmission instruction; the data transmission channel transmits data to be transmitted to the data processing unit.
In the actual working process, software or DMA can write the transmission data into the memory, and read the data from the memory through the data transmission channel and store the data in the transmission buffer queue. The data bit width of the TxFIFO is 32 bits, and the high 16 bits of the TxFIFO data are set as control bits in order to support the application scenario of the AUTOSAR. The time sequence format of the current transmitted data is controlled, and the time sequence format comprises a corresponding chip selection signal, a sampling edge, a data bit width, a data size end, whether the data is forbidden after the transmission is completed or not and the like. The other 16 bits store the data itself. And meanwhile, supporting a Job mode, wherein software can configure the transmission data length of the current Job, and hardware can configure a trigger interrupt after judging that Job transmission is completed.
Optionally, the data processing unit 602 includes:
the trigger control logic module 6021 is configured to respond to the trigger condition and issue a data transmission instruction to the data transmission channel;
a sequence transmission buffer 6022 configured to receive the sequence data to be transmitted by the data transmission channel;
the priority processing module 6023 is configured to determine the sequence data to be sent with the highest priority in the sequence sending buffer, and send the tasks to be sent in the sequence data to be sent with the highest priority to the task processing module in sequence;
the task processing module 6024 is configured to send the received task to be sent to the serial data interface unit.
Optionally, the priority handling module 6023 is further configured to: in response to receiving newly added sequence data which newly enters a sequence sending buffer zone, comparing the priority of the newly added sequence data with the priority of the current sequence data to obtain a comparison result; the current sequence data is sequence data sent at the current moment; and sending the task to be sent at the next moment to the task processing module according to the comparison result.
Optionally, in response to receiving newly added sequence data newly entering the sequence sending buffer, comparing priorities of the newly added sequence data and current sequence data to obtain a comparison result, including: before comparing the priority of newly added sequence data with the priority of current sequence data, determining whether the current transmission task is completed; and after the current sending task is completed, comparing the priority of the newly added sequence data with the priority of the current sequence data.
Optionally, sending the task to be sent at the next moment to the task processing module according to the comparison result includes: and under the condition that the comparison result represents that the priority of the newly added sequence data is higher than that of the current sequence data, sequentially sending all tasks to be sent in the newly added sequence data to the task processing module. And continuously transmitting the task to be transmitted which is not transmitted in the current sequence data under the condition that the comparison result indicates that the priority of the current sequence data is higher than that of the newly added sequence data.
Optionally, the sequence data interface unit 603 includes: a transmission buffer configured to receive and store a task to be transmitted;
the transmission buffer includes: a data content storage area configured to store data content of a task to be transmitted; and the configuration information storage area is configured to store a chip selection signal, a sampling edge, a data bit width and a data size end of a task to be sent.
Optionally, the sequence data interface unit further comprises: a receiving buffer configured to receive data to be written from the chip select device and transmit to the data processing unit; the data processing unit further includes: and the sequence data receiving buffer zone is configured to write the data to be written into the memory through a data receiving channel in the data transmission channel according to the chip selection information of the data to be written.
In specific operation, in combination with the Job mode of the SPI controller, a user stores data to be transmitted into the RAM of the system through software (e.g., APP), configures an external trigger source, e.g., configures a timer triggered by a period of 5ms, each timer triggers a Sequence transmission of the SPI once, a transmission channel corresponding to the data transmission channel 601 loads data in the RAM into a Sequence transmission buffer according to a configured address, and the priority processing module 6023 determines priorities of all sequences currently cached, determines a Sequence with the highest priority, and transmits all Job in the Sequence. For example, the external trigger source is set to be a timer with a period of 5ms, after reaching 5ms, data corresponding to the configured address is read to the Sequence sending buffer, that is, four sequences of S1, S2, S3 and S4 are read, and Job in S2 is sent in Sequence after judging that the priority of the four sequences is highest in the current Sequence is S2. Each Job transmission is completed, it is automatically detected whether the currently transmitted Sequence is the highest priority in the Sequence transmission buffer, if not, the Job of the highest priority Sequence is transmitted, and if the current Sequence is the highest priority, the remaining Job in the Sequence is continuously transmitted. If all Sequence transmissions are complete, the Idle state is restored. Similarly, the Sequence receiving buffer area can select a receiving channel in the data transmission channel 601 according to the chip selection information corresponding to the current transmission data to store the data into the system RAM of the corresponding address, and the whole data transmission process can realize periodical SPI Sequence triggering and task scheduling without the participation of software. The receiving Sequence and the sending Sequence are supported not by software, but by periodic triggering of a timer, and the hardware interrupt is not relied on, so that the load rate of a CPU is effectively reduced.
Referring to fig. 7, a multi-task processing device 700 for SPI architecture according to an embodiment of the present application includes:
a priority determining module 701, configured to determine a priority stored in a register corresponding to the sequence data to be transmitted, when receiving a data transmission instruction sent by an external trigger source;
the task to be sent determining module 702 is configured to determine the task to be sent in each sequence data to be sent according to the order of the priority stored in the register corresponding to the sequence data to be sent from high to low;
and a sending module 703 configured to send each task to be sent to a corresponding chip-selecting device.
According to the device provided by the embodiment of the application, the priority stored in the register corresponding to the transmission sequence number is directly read according to the data transmission instruction of the external trigger source, and data transmission is performed based on the priority, and priority judgment and data transmission are performed only through hardware, so that the problem that hardware is frequently interrupted due to the fact that the priority judgment is performed by means of software is avoided, the load rate of a processor is effectively reduced, and the data transmission efficiency is improved.
Referring to FIG. 8, an embodiment of the present application provides a multitasking device 800 for SPI architecture, including a processor (processor) 100 and a memory (memory) 101. Optionally, the apparatus may further comprise a communication interface (Communication Interface) 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other via the bus 103. The communication interface 102 may be used for information transfer. Processor 100 may invoke logic instructions in memory 101 to perform the multitasking method for the SPI architecture of the above-described embodiments.
Further, the logic instructions in the memory 101 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product.
The memory 101 is a computer readable storage medium, and may be used to store a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present application. Processor 100 executes functional applications and data processing by running program instructions/modules stored in memory 101, i.e., implements the multitasking method for the SPI architecture of the above-described embodiments.
The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. Further, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.
As shown in conjunction with fig. 9, an embodiment of the present application provides a controller 900, including: controller body, and multitasking 700 for SPI architecture as described above (800). A multitasking device 700 (800) for the SPI architecture is mounted to the controller body. The mounting relationships described herein are not limited to being placed within the controller, but include mounting connections to other components of the controller, including but not limited to physical, electrical, or signal transmission connections, etc. Those skilled in the art will appreciate that the multitasking device 700 (800) for the SPI architecture may be adapted to a feasible controller body, thereby implementing other feasible embodiments.
Embodiments of the present application provide a computer-readable storage medium storing computer-executable instructions configured to perform the multitasking method for SPI architecture of the above embodiments.
The present application provides a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the multitasking method for SPI architecture of the above embodiments.
The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.
The technical solutions of the embodiments of the present application may be embodied in the form of a software product, where the software product is stored in a storage medium, and includes one or more instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium may be a non-transitory storage medium including: a plurality of media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or a transitory storage medium.
The above description and the drawings illustrate embodiments of the present application sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.
Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled person may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present application. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (8)
1. A method of multitasking for an SPI architecture comprising:
under the condition that a data transmission instruction sent by an external trigger source is received, carrying the sequence data to be transmitted stored in a memory to a corresponding register, and determining the priority stored in the register corresponding to the sequence data to be transmitted, wherein the external trigger source is a timer triggered periodically;
determining whether a current transmission task is completed, and comparing the priority of the sequence data newly added into the register with the priority of the current sequence data after the current transmission task is completed, wherein the current sequence data is the sequence data transmitted at the current moment;
determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted;
and sending each task to be sent to the corresponding chip selection device.
2. The method according to claim 1, wherein determining the task to be transmitted at the next time based on the comparison result comprises:
under the condition that the comparison result represents that the priority of the newly added sequence data is higher than the priority of the current sequence data, determining that the task to be sent at the next moment is all the tasks to be sent in the newly added sequence data;
and under the condition that the comparison result indicates that the priority of the current sequence data is higher than that of the newly added sequence data, determining that the task to be sent at the next moment is the task to be sent which is not sent in the current sequence data.
3. The method of claim 1, further comprising determining the sequence data to be transmitted as follows:
acquiring address information contained in a data transmission instruction;
and reading data corresponding to the address information from the memory as sequence data to be transmitted according to the address information contained in the data transmission instruction.
4. A method according to any one of claims 1 to 3, further comprising:
receiving data to be written sent by chip selection equipment;
and writing the data to be written into the memory according to the chip selection information of the data to be written.
5. A multitasking apparatus for SPI architecture comprising:
the priority determining module is configured to carry the sequence data to be transmitted stored in the memory to the corresponding register under the condition that a data transmission instruction transmitted by the external trigger source is received, and determine the priority stored in the register corresponding to the sequence data to be transmitted, wherein the external trigger source is a periodically triggered timer;
the to-be-transmitted task determining module is configured to determine whether the current transmission task is completed, and compare the sequence data newly added into the register with the priority of the current sequence data after the current transmission task is completed, wherein the current sequence data is the sequence data transmitted at the current moment; determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted;
and the sending module is configured to send each task to be sent to the corresponding chip selection device.
6. A multitasking apparatus for SPI architecture comprising a data transmission channel, a data processing unit and a serial data interface unit, wherein:
the data transmission channel is connected with the data processing unit and is configured to send the sequence data to be sent stored in the memory to the data processing unit under the condition of receiving a data sending instruction sent by an external trigger source, wherein the external trigger source is a periodically triggered timer;
a data processing unit, connected with the serial data interface unit, configured to:
receiving sequence data to be transmitted, and determining the priority stored in a register corresponding to the sequence data to be transmitted;
determining whether a current transmission task is completed, and comparing newly received sequence data to be transmitted with the priority of the current sequence data after the current transmission task is completed, wherein the current sequence data is the sequence data transmitted at the current moment;
determining tasks to be transmitted in each sequence data to be transmitted according to the sequence from high to low of the priority stored in the register corresponding to the sequence data to be transmitted;
and the serial data interface unit is connected with the plurality of chip selection devices and is configured to receive the task to be transmitted from the data processing unit and transmit the task to be transmitted to the corresponding chip selection device.
7. The apparatus of claim 6, wherein the data processing unit comprises:
the trigger control logic module is configured to respond to the trigger condition and send a data sending instruction to the data transmission channel;
a sequence transmission buffer configured to receive sequence data to be transmitted, which is transmitted by the data transmission channel;
the priority processing module is configured to determine the sequence data to be transmitted with the highest priority in the sequence transmission buffer area, and sequentially transmit the tasks to be transmitted in the sequence data to be transmitted with the highest priority to the task processing module;
and the task processing module is configured to send the received task to be sent to the sequence data interface unit.
8. The apparatus of claim 6, wherein the sequence data interface unit comprises:
a transmission buffer configured to receive and store a task to be transmitted;
the transmission buffer includes:
a data content storage area configured to store data content of a task to be transmitted;
and the configuration information storage area is configured to store a chip selection signal, a sampling edge, a data bit width and a data size end of a task to be sent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311241240.6A CN116980362B (en) | 2023-09-25 | 2023-09-25 | Multitasking method and device for SPI architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311241240.6A CN116980362B (en) | 2023-09-25 | 2023-09-25 | Multitasking method and device for SPI architecture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116980362A CN116980362A (en) | 2023-10-31 |
| CN116980362B true CN116980362B (en) | 2024-02-27 |
Family
ID=88480025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311241240.6A Active CN116980362B (en) | 2023-09-25 | 2023-09-25 | Multitasking method and device for SPI architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116980362B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6381532B1 (en) * | 2000-09-20 | 2002-04-30 | Visteon Global Technologies, Inc. | Queued port data controller for microprocessor-based engine control applications |
| CN103955410A (en) * | 2014-05-23 | 2014-07-30 | 苏州国芯科技有限公司 | Interruption control method based on multiple interrupt source priority ordering |
| CN108762905A (en) * | 2018-05-24 | 2018-11-06 | 苏州乐麟无线信息科技有限公司 | A kind for the treatment of method and apparatus of multitask event |
| CN113031927A (en) * | 2021-03-26 | 2021-06-25 | 苏州挚途科技有限公司 | Data input and output method, device and system |
| CN113448902A (en) * | 2020-03-25 | 2021-09-28 | 意法设计与应用股份有限公司 | Processing system, integrated circuit, device and method with queued serial peripheral interface |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8737415B2 (en) * | 2010-07-02 | 2014-05-27 | Telefonaktiebolaget L M Ericsson (Publ) | Prioritization of data packets |
-
2023
- 2023-09-25 CN CN202311241240.6A patent/CN116980362B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6381532B1 (en) * | 2000-09-20 | 2002-04-30 | Visteon Global Technologies, Inc. | Queued port data controller for microprocessor-based engine control applications |
| CN103955410A (en) * | 2014-05-23 | 2014-07-30 | 苏州国芯科技有限公司 | Interruption control method based on multiple interrupt source priority ordering |
| CN108762905A (en) * | 2018-05-24 | 2018-11-06 | 苏州乐麟无线信息科技有限公司 | A kind for the treatment of method and apparatus of multitask event |
| CN113448902A (en) * | 2020-03-25 | 2021-09-28 | 意法设计与应用股份有限公司 | Processing system, integrated circuit, device and method with queued serial peripheral interface |
| CN113031927A (en) * | 2021-03-26 | 2021-06-25 | 苏州挚途科技有限公司 | Data input and output method, device and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116980362A (en) | 2023-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108228492B (en) | Multi-channel DDR interleaving control method and device | |
| CN1552028B (en) | Method and apparatus for distributed direct memory access for systems on chip | |
| EP2097828B1 (en) | Dmac to handle transfers of unknown lengths | |
| CN108932108B (en) | Method for scheduling and executing commands of flash memory and device using the same | |
| US11010094B2 (en) | Task management method and host for electronic storage device | |
| CN101506783B (en) | Method and apparatus for conditional broadcast of barrier operations | |
| US20020049874A1 (en) | Data processing device used in serial communication system | |
| CN1159657C (en) | Bus system and its data transmitting method | |
| CN111290983A (en) | USB transmission equipment and transmission method | |
| CN112181887B (en) | Data transmission method and device | |
| CN107066413B (en) | Method for processing data of multiple bus devices and bus system thereof | |
| KR20150039142A (en) | Serial peripheral interface with control logic for system performance improvement, and method therefor | |
| CN113064709B (en) | Task scheduling method and system suitable for MCU chip | |
| CN116980362B (en) | Multitasking method and device for SPI architecture | |
| US20080147906A1 (en) | DMA Transferring System, DMA Controller, and DMA Transferring Method | |
| CN102708079B (en) | Be applied to the method and system of the control data transmission of microcontroller | |
| KR20170117326A (en) | Direct memory access control device for at least one processing unit having a random access memory | |
| CN111427806A (en) | Method for sharing serial port by dual-core AMP system, storage medium and intelligent terminal | |
| WO2011052282A1 (en) | Vehicle-mounted network device | |
| CN102385555B (en) | Caching system and method of data caching | |
| US8799530B2 (en) | Data processing system with a host bus adapter (HBA) running on a PCIe bus that manages the number enqueues or dequeues of data in order to reduce bottleneck | |
| US6654861B2 (en) | Method to manage multiple communication queues in an 8-bit microcontroller | |
| CN111124987B (en) | PCIE-based data transmission control system and method | |
| CN113672536B (en) | Data storage system, storage module and data storage method | |
| CN117033276B (en) | Bus communication method, system, electronic device and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |