JP6189396B2 - Video signal processing apparatus and video signal processing method - Google Patents

Description

  The present invention relates to a video signal processing apparatus and a video signal processing method for converting an input analog video signal into a digital video signal and outputting the digital video signal.

  2. Description of the Related Art Conventionally, a video signal processing device that converts an analog video signal input from a video signal source such as a PC into a digital video signal and outputs the digital video signal generated by A / D converting the analog video signal, A data enable signal (hereinafter referred to as a “DE signal”) that is generated based on a horizontal synchronization signal (Hsync) and a vertical synchronization signal (Vsync) input from a signal source and a horizontal synchronization signal and a vertical synchronization signal and indicates a valid period of video data. Is output to the display device.

  Here, when A / D converting an analog video signal, a sampling clock synchronized with the analog video signal is necessary. In a normal case, a phase-locked loop circuit (hereinafter referred to as “PLL circuit”) is provided, and horizontal synchronization is performed. A sampling clock synchronized with the signal is generated. However, when the phase of the sampling clock (hereinafter referred to as “sampling phase”) is not appropriate, there is a problem that the video displayed on the display device flickers.

  Therefore, in order to solve the above problems, a clock generation unit that generates a clock synchronized with the input synchronization signal, a delay unit that delays the clock by 2 to 3 ns per stage, and shifts the phase are connected in multiple stages, and obtained from there. A clock phase shift unit that receives a plurality of sampling clocks and a selection signal and selects a sampling clock, an A / D conversion unit that A / D converts an input video signal, and a frame memory that stores a digitally converted video signal in units of frames Unit, generating a selection signal, reading video data from the frame memory unit, and performing various calculations, calculating the maximum address of the video data difference between adjacent pixels of one scanning line in an arbitrary sampling clock, When another sampling clock is selected, reading the data at that address is repeated a predetermined number of times, A video signal processing circuit for variation of the sampling clock of the optimum phase of the sampling clock with the smallest has been proposed (e.g., see Patent Document 1).

JP 2000-152030 A

However, the prior art has the following problems.
First, the video signal processing circuit of Patent Document 1 stores the maximum value of variation of two adjacent pixels in one scanning line, and optimizes the sampling phase when the maximum value of variation is minimized. When good video data continues, it is judged that the sampling phase is optimal even though it is originally inadequate as the sampling phase, and the video displayed on the display device may not be improved. There is a problem.

  Further, as described above, the conventional video signal processing apparatus generates the DE signal based on the horizontal synchronization signal and the vertical synchronization signal input from the video signal source, but the effective period of the video data in the analog video signal And the effective period of the video data in the digital video signal indicated by the DE signal may cause a problem that the video displayed on the display device may deviate from the display range of the display device. is there.

  That is, although the sampling phase is inappropriate, the phase shift determined to be the optimum sampling phase, or the position where the display position of the video displayed on the display device deviates from the display range of the display device There is a problem that an image displayed on the display device is disturbed due to the shift.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a video signal processing device and a video signal processing method capable of suppressing disturbance of a video displayed on a display device. To do.

  The video signal processing apparatus according to the present invention is based on an A / D converter that converts an analog video signal input from a video signal source into a digital video signal in accordance with a sampling clock, and a horizontal synchronization signal from the video signal source. A clock generation unit that generates a sampling clock, a digital video signal, a phase adjustment unit that selects an optimal sampling phase based on the horizontal synchronization signal and the vertical synchronization signal, and corrects the sampling clock, The phase adjustment unit determines two locations where the difference between the data values of two consecutive pixels in the horizontal direction is large in one frame of the video data of the digital video signal, in descending order, and for two consecutive two pixels, One for the previous pixel and the other for the subsequent pixel to determine the variance for the following frames, The sampling phase of the / D conversion unit is changed, and again, for two consecutive two pixels, one is for the previous pixel and the other is for the subsequent pixel to obtain the variance for the following multiple frames. The sampling phase of the A / D conversion unit is repeated a variable number of times, and the sampling phase with the smallest obtained variance is selected as the optimum sampling phase.

  The video signal processing method according to the present invention is based on an A / D converter that converts an analog video signal input from a video signal source into a digital video signal according to a sampling clock, and a horizontal synchronization signal from the video signal source. A clock generation unit that generates a sampling clock, and a phase adjustment unit that selects an optimal sampling phase based on the digital video signal, the horizontal synchronization signal, and the vertical synchronization signal, and corrects the sampling clock. A video signal processing method executed by a video signal processing apparatus, wherein, in one frame of video data of a digital video signal, two locations where the difference between the data values of two consecutive pixels in the horizontal direction is increased are determined in descending order. And two consecutive two pixels, one for the previous pixel and the other for the subsequent pixel. On the other hand, the step of obtaining the variance for each of a plurality of subsequent frames and the sampling phase of the A / D conversion unit are changed, and two consecutive two pixels are again compared to the previous pixel, the other is the latter The process of obtaining the variance for a plurality of subsequent frames for each pixel is repeated a variable number of times of the sampling phase of the A / D converter, and the sampling phase with the smallest obtained variance is set as the optimum sampling phase. And a step of selecting.

According to the video signal processing apparatus and the video signal processing method according to the present invention, in one frame of video data of a digital video signal, two locations where the difference between the data values of two consecutive pixels in the horizontal direction is increased in descending order. Determine the variance for the following multiple frames for two consecutive two pixels, one for the previous pixel and the other for the subsequent pixel, and change the sampling phase of the A / D converter Then, again for two consecutive two pixels, one is for the previous pixel and the other is for the subsequent pixel. And the sampling phase with the smallest obtained variance is selected as the optimum sampling phase .
For this reason, it is possible to suppress the disturbance of the image displayed on the display device.

It is a block block diagram which shows the video signal processing apparatus which concerns on Embodiment 1 of this invention with a display apparatus. It is explanatory drawing which shows the function of the phase adjustment part of the video signal processing apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process of the phase adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is explanatory drawing which shows the relationship between the effective range of the video data in an analog video signal, and the effective range of the video data in the digital video signal which DE signal shows regarding the video signal processing apparatus which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows the function of the position adjustment part of the video signal processing apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows the process of the position adjustment part of the video signal processing apparatus concerning Embodiment 1 of this invention.

  Hereinafter, preferred embodiments of a video signal processing apparatus and a video signal processing method according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals. . In the present invention, the phase shift of the sampling phase and the position shift of the display position are adjusted using a signal input from the video signal source.

Embodiment 1 FIG.
FIG. 1 is a block configuration diagram showing a video signal processing apparatus according to Embodiment 1 of the present invention together with a display apparatus. In FIG. 1, the video signal processing apparatus 10 includes an A / D conversion unit 11, a clock generation unit 12, a phase adjustment unit 13, an enable signal generation unit 14, and a position adjustment unit 15.

  The video signal processing apparatus 10 receives an analog video signal, a horizontal synchronization signal, and a vertical synchronization signal from a video signal source such as a PC, and displays a digital video signal, a horizontal synchronization signal, a vertical synchronization signal, and a DE signal. 20 is output.

  Here, the video signal processing device 10 is configured by, for example, a CPU (Central Processing Unit), a CPU and a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Integral Integrate Integral Integrate Integrative Integrate).

  The A / D converter 11 converts the analog video signal from the video signal source into a digital video signal according to the sampling clock from the phase adjuster 13 and outputs the digital video signal. The clock generation unit 12 includes a PLL circuit, and generates and outputs a sampling clock based on the horizontal synchronization signal from the video signal source.

  The phase adjustment unit 13 selects an optimum sampling phase based on the digital video signal from the A / D conversion unit 11 and the horizontal synchronization signal and the vertical synchronization signal from the video signal source, and outputs from the clock generation unit 12. By correcting the sampling clock and outputting it to the A / D converter 11, the phase shift of the sampling phase is adjusted.

  Specifically, the phase adjustment unit 13 determines two locations where the difference between the data values of two consecutive pixels in the horizontal direction (on one line) becomes large in one frame of the video data of the digital video signal in descending order. decide. Further, the phase adjusting unit 13 distributes a plurality of (for example, 5 frames) distributions of the two consecutive pixels, one for the previous pixel and the other for the subsequent pixel. Ask.

  In addition, the phase adjustment unit 13 changes the sampling phase of the A / D conversion unit 11 and again for these two consecutive two pixels, one for the previous pixel and the other for the subsequent pixel. Find the variance for each successive frame. The phase adjustment unit 13 repeats this process a variable number of times (for example, 64 times) of the sampling phase of the A / D conversion unit 11, and selects the sampling phase with the smallest variance as the optimum sampling phase.

  FIG. 2 is an explanatory diagram showing the function of the phase adjustment unit of the video signal processing apparatus according to Embodiment 1 of the present invention. Note that the video signal processing apparatus 10 receives video data of a still image that is not black and not monochrome as an analog video signal.

  First, the phase adjustment unit 13 determines that the difference between the data values (R / G / B individual) of two pixels continuous in the horizontal direction within one frame is the largest and the second largest is the first frame. decide. At this time, the data values of two consecutive pixels are targeted for both large to small and small to large.

  Subsequently, the phase adjustment unit 13 determines the first two determined consecutive pixels as the coordinates of the previous pixel, and the second consecutive two pixels as the coordinates of the subsequent pixel. Thus, the distribution of the video data is obtained at each coordinate (FIG. 2 (a)).

  Next, the phase adjustment unit 13 changes the sampling phase of the A / D conversion unit 11 and again obtains the distribution of video data for five frames for these two consecutive two pixels. Subsequently, the phase adjustment unit 13 repeats this processing a variable number of times (here, 64 times) of the sampling phase of the A / D conversion unit 11, and selects the sampling phase with the smallest variance as the optimum sampling phase ( FIG. 2 (b)).

  Here, the case where the sampling phase is at the change point on the front side of the video data will be described with reference to FIG. At this time, for the previous pixel, either the video data to be sampled or the video data one pixel before is sampled. Therefore, depending on the size of the data one pixel before, the time variation of the sampled data may be large or small. That is, the dispersion may increase.

  For the subsequent pixels, either the sampling target video data or the video data one pixel before that should have a large data difference is sampled. Therefore, the time change of the sampled data is large and the variance is large.

  Next, a case where the sampling phase is at the change point on the rear side of the video data will be described with reference to FIG. At this time, for the previous pixel, either the video data to be sampled or the video data that is supposed to have a large data difference after one pixel is sampled. Therefore, the time change of the sampled data is large and the variance is large.

  For the subsequent pixels, either the sampling target video data or the video data after one pixel is sampled. Therefore, depending on the size of the data one pixel before, the time variation of the sampled data may be large or small. That is, the dispersion may increase.

  On the other hand, as shown in FIG. 2E, when the sampling phase is optimum, the temporal change of the sampled data is small and the variance is small for both the previous pixel and the subsequent pixel. Become.

FIG. 3 is a flowchart showing processing of the video signal processing apparatus according to Embodiment 1 of the present invention.
In FIG. 3, first, the phase adjustment unit 13 sets a variable i to an initial value 1 (step S101).

  Subsequently, the phase adjustment unit 13 selects the sampling phase (CLKsample i) of the variable i = 1 (Step S102), executes A / D conversion (Step S103), and data of two pixels continuous in the horizontal direction. Two locations where the difference between the values becomes large are determined in descending order (step S104).

  Next, the phase adjustment unit 13 selects a sampling phase (CLKsample i) with a variable i = 1 (step S105), executes A / D conversion (step S106), and outputs video data for five consecutive frames. Reading (step S107), the variance for five consecutive frames is obtained (step S108).

Subsequently, the phase adjustment unit 13 determines whether or not the variable i is 64 (step S109).
If it is determined in step S109 that the variable i is not 64 (that is, No), the phase adjustment unit 13 substitutes i + 1 for the variable i (step S110), and proceeds to step S105.

  On the other hand, if it is determined in step S109 that the variable i is 64 (that is, Yes), the phase adjustment unit 13 selects the sampling phase (CLKsample i) that minimizes the variance as the optimum sampling phase. (Step S111), and the process of FIG.

  In this way, the phase adjustment unit 13 uses two adjacent pixels, and selects the sampling phase when the variance of the previous pixel is the minimum and the subsequent pixel is the minimum as the optimal sampling phase. . Thereby, an analog video signal can be sampled at an optimal timing.

  Returning to FIG. 1, the enable signal generation unit 14 is a DE signal indicating the valid period of the video data based on the horizontal and vertical synchronization signals from the video signal source and the DE feedback signal from the position adjustment unit 15. Is generated and output.

  The position adjustment unit 15 converts the DE signal based on the digital video signal from the A / D conversion unit 11, the horizontal and vertical synchronization signals from the video signal source, and the DE signal from the enable signal generation unit 14. By outputting a DE feedback signal for correction to the enable signal generation unit 14, the displacement of the display position is adjusted.

  That is, the position adjustment unit 15 confirms the data values (R / G / B individual) of one pixel at the four corners in the image among the video data of one frame of the digital video signal, and the data value is 0 ( It is determined whether or not all the video data has been captured at the current timing depending on whether the display is black) or other than 0 (display is not black).

  FIG. 4 is a diagram illustrating the relationship between the effective range of video data in the digital video signal indicated by the DE signal and the effective range of video data in the analog video signal, according to the video signal processing apparatus according to the first embodiment of the present invention. FIG.

  In FIG. 4, the effective range of the video data in the digital video signal indicates the display area displayed on the display device 20, and the effective range of the video data in the analog video signal indicates the ideal display position of the video data. Yes.

  Here, the start position of the DE signal (hereinafter referred to as “DE start position”) and the pulse width of the DE signal (hereinafter referred to as “DE pulse width”) are changed, and the output period of the DE signal is set. V blank period back porch (hereinafter abbreviated as “back porch”) and V blank period front porch (hereinafter abbreviated as “front porch”) for changing the display position of video data 20 can be made to coincide with the display area displayed at 20. The DE start position, DE pulse width, back porch and front porch can be set by a register.

  Specifically, the position adjusting unit 15 first and last data of the first DE signal after the vertical synchronization signal (Vsync), that is, the upper left data A and the upper right data B of the effective range of the video data in the digital video signal. And the first and last data of the last DE signal before the vertical synchronization signal (Vsync), that is, the lower left data C and the lower right data D of the effective range of the video data in the digital video signal are confirmed.

  FIG. 5 is an explanatory diagram showing the function of the position adjustment unit of the video signal processing apparatus according to Embodiment 1 of the present invention. The video signal processing apparatus 10 receives video data of a still image that is not black as an analog video signal.

  First, when all the data ABCD is 0 (1 in FIG. 5), the position adjustment unit 15 calculates an error between the DE signal and the display position from the coordinates that are the first non-zero data value in the display area. Detect and change DE start position, back porch and front porch so that data A is not 0.

  Further, when the data of A or C is 0 and the data of B or D is not 0 (2-1 in FIG. 5), the position adjustment unit 15 uses A or C to shift the display position to the left. The DE start position is increased until the C data becomes other than 0. At this time, the DE pulse width does not change.

  In addition, when the data of B or D is 0 and the data of A or C is not 0 (2-2 in FIG. 5), the position adjustment unit 15 uses A or The DE start position is decreased until the C data becomes other than 0. At this time, the DE pulse width does not change.

  In addition, when the data of A is 0 and the data of C is not 0 (3-1 in FIG. 5), the position adjustment unit 15 determines that the data of A is other than 0 in order to shift the display position upward. Increase the back porch until At this time, the front porch is reduced by the same value at the same time.

  Further, when the C data is 0 and the A data is not 0 (3-2 in FIG. 5), the position adjustment unit 15 sets the A data to 0 in order to shift the display position downward. Reduce the back porch until it becomes. At this time, the front porch is increased by the same value at the same time.

  Further, when the C data is 0 (4-1 in FIG. 5), the position adjusting unit 15 sets the C length to match the vertical length of the display area and the vertical length of the display position. Increase the front porch until the data is non-zero.

  In addition, when the C data is not 0 (4-2 in FIG. 5), the position adjusting unit 15 sets the C data to match the vertical length of the display area with the vertical length of the display position. The front pouch is reduced until the V becomes zero before the V blank period.

  Further, when the data of B is 0 (5-1 in FIG. 5), the position adjusting unit 15 sets the horizontal length of the display area and the horizontal length of the display position in order to match the B length. Decrease the DE pulse width until the data is non-zero.

  Further, when the B data is not 0 (5-2 in FIG. 5), the position adjustment unit 15 sets the B data to match the horizontal length of the display area with the horizontal length of the display position. The DE pulse width is increased until becomes zero.

6 to 16 are flowcharts showing processing of the position adjustment unit of the video signal processing apparatus according to Embodiment 1 of the present invention. Since all the operations in this flowchart are the position adjustment unit 15, description thereof is omitted.
6 to 16, first, the presence or absence of data at the four corners of the display area being displayed is confirmed (step S201).

Subsequently, it is determined whether any of the data at the four corners is non-zero (not zero) (step S202).
If it is determined in step S202 that any of the four corner data is not non-zero (ie, No), the valid data start coordinates are confirmed (step S203), and the display position is valid upward. The data is moved by the data start coordinate (line) (step S204), the display position is moved to the left by the valid data start coordinate (pixel) (step S205), and the process proceeds to step S201.

  On the other hand, if it is determined in step S202 that any of the data at the four corners is non-zero (that is, Yes), it is determined whether the upper left and lower left are 0 and the upper right or lower right is non-zero. (Step S206).

  If it is determined in step S206 that the upper left and lower left are 0 and the upper right or lower right is non-zero (ie, Yes), the display position is moved to the left by one pixel (step S207) The presence or absence of data at the four corners of the display area is confirmed (step S208).

Next, it is determined whether or not upper left and lower left are 0 (step S209).
If it is determined in step S209 that the upper left and the lower left are 0 (that is, Yes), the process proceeds to step S207.

  On the other hand, if it is determined in step S209 that the condition that the upper left and the lower left are 0 is not satisfied (that is, No), it is determined whether the upper left is 0 (step S210). In addition, when it becomes No in step S209, the left end of a display area and the left end of a display position correspond.

  If it is determined in step S210 that the upper left is 0 (that is, Yes), the display position is moved upward by one line (step S211), and the presence / absence of data at the four corners of the display area being displayed is determined. After confirming (step S212), the process proceeds to step S210.

  On the other hand, if it is determined in step S210 that the condition that the upper left is 0 is not satisfied (ie, No), the display position is moved down one line (step S213), and the four corners of the display area being displayed are displayed. Is confirmed (step S214), and it is determined whether the upper left is 0 (step S215).

If it is determined in step S215 that the condition that the upper left is 0 is not satisfied (that is, No), the process proceeds to step S213.
On the other hand, if it is determined in step S215 that the upper left is 0 (that is, Yes), the display position is moved upward by one line (step S216). As a result, the upper left of the display area matches the upper left of the display position.

Subsequently, the presence or absence of data at the four corners of the display area being displayed is confirmed (step S217), and it is determined whether the lower left is 0 (step S218).
If it is determined in step S218 that the lower left is 0 (that is, Yes), front porch + 1 is substituted for the front porch (step S219), and the process proceeds to step S217.

  On the other hand, if it is determined in step S218 that the condition that the lower left is 0 is not satisfied (ie, No), front porch-1 is substituted for the front porch (step S220), and the four corners of the display area being displayed are displayed. Is checked (step S221), and it is determined whether the lower left is 0 (step S222).

If it is determined in step S222 that the condition that the lower left is 0 is not satisfied (ie, No), the process proceeds to step S220.
On the other hand, if it is determined in step S222 that the lower left is 0 (that is, Yes), front porch + 1 is substituted for the front porch (step S223). As a result, the upper left and lower left of the display area coincides with the upper left and lower left of the display position.

Next, the presence or absence of data at the four corners of the display area being displayed is checked (step S224), and it is determined whether or not the upper right is 0 (step S225).
If it is determined in step S225 that the upper right is 0 (that is, Yes), DE pulse width-1 is substituted for the DE pulse width (step S226), and the process proceeds to step S224.

  On the other hand, if it is determined in step S225 that the condition that the upper right is 0 is not satisfied (that is, No), DE pulse width + 1 is substituted for DE pulse width (step S227), and the display area being displayed is displayed. The presence or absence of data at the four corners is confirmed (step S228), and it is determined whether or not the upper right is 0 (step S229).

If it is determined in step S229 that the condition that the upper right is 0 is not satisfied (that is, No), the process proceeds to step S227.
On the other hand, if it is determined in step S229 that the upper right is 0 (that is, Yes), DE pulse width −1 is substituted for the DE pulse width (step S230), and the process ends. As a result, the top / bottom / left / right of the display area matches the top / bottom / left / right of the display position.

  On the other hand, if it is determined in step S206 that the upper left and lower left are 0 and the upper right or lower right is non-zero (ie, No), the upper left or lower left is non-zero and the upper right and lower right is 0. It is determined whether or not (step S231).

  If it is determined in step S231 that the upper left or lower left is non-zero and the upper right and lower right are 0 (that is, Yes), the display position is moved to the right by one pixel (step S232), The presence or absence of data at the four corners of the display area is confirmed (step S233).

Subsequently, it is determined whether or not the upper left and lower left are 0 (step S234).
If it is determined in step S234 that the condition that the upper left and the lower left are 0 is not satisfied (that is, No), the process proceeds to step S232.

  On the other hand, if it is determined in step S234 that the upper left and lower left are 0 (that is, Yes), the display position is moved to the left by one pixel (step S235). As a result, the left end of the display area matches the left end of the display position.

  Next, the upper left and lower left of the display area coincide with the upper left and lower left of the display area and the upper left and lower left of the display position coincide with each other by the above-described processing of steps S210 to 230. And the top, bottom, left and right of the display position match.

  On the other hand, if it is determined in step S231 that the upper left or lower left is non-zero and the upper right and lower right are not 0 (ie, No), the upper left and upper right are non-zero and the lower left and lower right are zero. It is determined whether or not (step S236).

  If it is determined in step S236 that the upper left and upper right are non-zero and the lower left and lower right are 0 (ie, Yes), the display position is moved to the right by one pixel (step S237) The presence or absence of data at the four corners of the display area is confirmed (step S238), and it is determined whether or not the upper left is 0 (step S239).

If it is determined in step S239 that the condition that the upper left is 0 is not satisfied (that is, No), the process proceeds to step S237.
On the other hand, if it is determined in step S239 that the upper left is 0 (ie, Yes), the display position is moved to the left by one pixel (step S240). As a result, the left end of the display area matches the left end of the display position.

Subsequently, the presence or absence of data at the four corners of the display area being displayed is confirmed (step S241), and it is determined whether the upper left is 0 (step S242).
If it is determined in step S242 that the upper left is 0 (that is, Yes), the display position is moved downward by one line (step S243), and the process proceeds to step S241.

  On the other hand, if it is determined in step S242 that the condition that the upper left is 0 is not satisfied (ie, No), the display position is moved upward by one line (step S244). As a result, the upper left of the display area matches the upper left of the display position.

Next, the presence or absence of data at the four corners of the display area being displayed is checked (step S245), and it is determined whether the lower left is 0 (step S246).
If it is determined in step S246 that the lower left is 0 (that is, Yes), the front porch + 1 is substituted for the front porch (step S247), and the process proceeds to step S245.

  On the other hand, if it is determined in step S246 that the condition that the lower left is 0 is not satisfied (that is, No), at this stage, the upper left and lower left of the display area coincide with the upper left and lower left of the display position. By the processing of steps S224 to 230, the up / down / left / right of the display area matches the up / down / left / right of the display position.

  On the other hand, if it is determined in step S236 that the upper left and upper right are non-zero and the lower left and lower right are not 0 (ie, No), the upper left and upper right are 0 and the lower left and lower right are non-zero. It is determined whether or not (step S248).

  If it is determined in step S248 that the upper left and upper right are 0 and the lower left and lower right are non-zero (that is, Yes), the display position is moved to the right by one pixel (step S249), The presence or absence of data at the four corners of the display area is confirmed (step S250), and it is determined whether the lower left is 0 (step S251).

If it is determined in step S251 that the condition that the lower left is 0 is not satisfied (that is, No), the process proceeds to step S249.
On the other hand, if it is determined in step S251 that the lower left is 0 (ie, Yes), the display position is moved to the left by one pixel (step S252). As a result, the left end of the display area matches the left end of the display position.

Subsequently, the presence or absence of data at the four corners of the display area being displayed is confirmed (step S253), and it is determined whether the upper left is 0 (step S254).
If it is determined in step S254 that the upper left is 0 (that is, Yes), the display position is moved upward by one line (step S255), and the process proceeds to step S253.

  On the other hand, if it is determined in step S254 that the condition that the upper left is 0 is not satisfied (that is, No), at this stage, the upper left of the display area matches the upper left of the display position, and steps S245 to 247 are performed. Through the processing, the upper left and lower left of the display area coincide with the upper left and lower left of the display position, and the upper and lower left and right of the display area and the upper and lower left and right of the display position coincide with each other through the processing of steps S224 to 230.

  On the other hand, if it is determined in step S248 that the upper left and upper right are 0 and the lower left and lower right are non-zero (ie, No), the display position is moved to the right by one pixel (step S256). ), The presence or absence of data at the four corners of the display area being displayed is confirmed (step S257), and it is determined whether the upper left and the lower left are 0 (step S258).

If it is determined in step S258 that the condition that the upper left and lower left are 0 is not satisfied (ie, No), the process proceeds to step S256.
On the other hand, if it is determined in step S258 that the upper left and lower left are 0 (that is, Yes), the display position is moved to the left by one pixel (step S259). As a result, the left end of the display area matches the left end of the display position.

  Next, the display position is moved downward by one line (step S260), the presence or absence of data at the four corners of the display area being displayed is checked (step S261), and it is determined whether the upper left is zero. (Step S262).

If it is determined in step S262 that the condition that the upper left is 0 is not satisfied (that is, No), the process proceeds to step S260.
On the other hand, if it is determined in step S262 that the upper left is 0 (that is, Yes), the display position is moved upward by one line (step S263). As a result, the upper left of the display area matches the upper left of the display position.

  Subsequently, the upper left and lower left of the display area and the upper left and lower left of the display position coincide with each other by the processing of steps S245 to 247 described above, and the upper and lower left and right of the display area and the upper and lower left and right of the display position are processed by the processing of steps S224 to 230. Matches.

  In this way, the position adjustment unit 15 checks the data value of one pixel at the four corners in the image from the video data for one frame of the digital video signal, and whether the data value is 0 or not. In response, the start position and pulse width of the DE signal, and the V blank period back porch and the V blank period front porch of the DE signal are changed. Thereby, it is possible to capture all input data when sampling an analog signal.

As described above, according to the first embodiment, in one frame of video data of a digital video signal, two locations where the difference between the data values of two consecutive pixels in the horizontal direction is increased are determined in descending order. With respect to two consecutive pixels, one is for the previous pixel and the other is for the subsequent pixel, the variances for the following multiple frames are obtained, the sampling phase of the A / D converter is changed, and 2 again For two consecutive pixels, one is for the previous pixel, and the other is for the subsequent pixel. The process for obtaining the variance for a plurality of subsequent frames is repeated a number of times for the sampling phase of the A / D converter. The sampling phase with the smallest obtained variance is selected as the optimum sampling phase.
Further, according to the first embodiment, among the video data for one frame of the digital video signal, the data value of one pixel at the four corners in the image is confirmed, and whether the data value is 0 or other than 0. In response, the start position and pulse width of the DE signal, and the V blank period back porch and the V blank period front porch of the DE signal are changed.
Therefore, it is possible to suppress the disturbance of the video displayed on the display device.

  DESCRIPTION OF SYMBOLS 10 Video signal processing apparatus, 11 A / D conversion part, 12 Clock generation part, 13 Phase adjustment part, 14 Enable signal generation part, 15 Position adjustment part, 20 Display apparatus.

Claims (3)

An A / D converter that converts an analog video signal input from a video signal source into a digital video signal in accordance with a sampling clock;
A clock generation unit that generates the sampling clock based on a horizontal synchronization signal from the video signal source;
A phase adjustment unit that selects an optimal sampling phase based on the digital video signal and the horizontal and vertical synchronization signals and corrects the sampling clock; and
The phase adjusting unit is
In one frame of the video data of the digital video signal, two locations where the difference between the data values of two consecutive pixels in the horizontal direction is increased are determined in descending order,
Regarding the two consecutive two pixels, one is for the previous pixel, and the other is for the subsequent pixel, and the variance for the following multiple frames is obtained.
The sampling phase of the A / D conversion unit is changed, and again for the two consecutive two pixels, dispersion is performed for a plurality of subsequent frames, one for the previous pixel and the other for the subsequent pixel. The process to obtain is repeated a variable number of times of the sampling phase of the A / D converter,
A video signal processing apparatus that selects a sampling phase with the smallest obtained variance as an optimum sampling phase. An enable signal generating unit that generates a DE signal indicating an effective period of video data based on a horizontal synchronization signal and a vertical synchronization signal from the video signal source and a DE feedback signal;
A DE feedback signal for correcting the DE signal based on the digital video signal from the A / D conversion unit, the horizontal and vertical synchronization signals, and the DE signal from the enable signal generation unit. A position adjusting unit that outputs the enable signal to the enable signal generating unit,
The position adjusting unit is
Among the video data for one frame of the digital video signal, check the data value of one pixel at the four corners in the image,
The start position and pulse width of the DE signal, and the V blank period back porch and the V blank period front porch of the DE signal are changed according to whether the data value is 0 or non-zero. 2. A video signal processing apparatus according to 1. An A / D converter that converts an analog video signal input from a video signal source into a digital video signal in accordance with a sampling clock;
A clock generation unit that generates the sampling clock based on a horizontal synchronization signal from the video signal source;
A video executed by a video signal processing device comprising: a phase adjustment unit that selects an optimal sampling phase and corrects the sampling clock based on the digital video signal and the horizontal synchronization signal and the vertical synchronization signal A signal processing method comprising:
Determining two locations in descending order of the difference between the data values of two consecutive pixels in the horizontal direction in one frame of the video data of the digital video signal;
For the two consecutive two pixels, one for the previous pixel and the other for the subsequent pixel, determining the variance for the following multiple frames respectively;
The sampling phase of the A / D conversion unit is changed, and again for the two consecutive two pixels, dispersion is performed for a plurality of subsequent frames, one for the previous pixel and the other for the subsequent pixel. Repeating the process of obtaining the sampling phase of the A / D conversion unit a variable number of times;
Selecting the sampling phase with the smallest obtained variance as the optimum sampling phase;
A video signal processing method comprising:

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