JP4114630B2 - Video signal processing device - Google Patents

Description

  The present invention realizes optimum image display by correctly adjusting the frequency and phase of the dot clock even when the image is displayed only in a part of the effective area or in the case of a video signal of a format other than the standard in the video signal processing apparatus. It is about the technology aiming to do.

  In recent years, a matrix display device represented by a liquid crystal has been developed as a display device replacing a cathode ray tube. In addition, the signal level of the PC video signal input to the liquid crystal display device changes with the dot cycle, and it matches the dot cycle when displayed on the matrix display device or when signal processing is performed by writing to the memory. A sampling clock signal is required.

  However, since few personal computers have this sampling clock signal output terminal, it is necessary to reproduce the sampling clock signal by multiplying the horizontal synchronizing signal by a PLL circuit or the like. Therefore, a method for automatically adjusting the frequency and phase of the sampling clock is considered.

  FIG. 8 is a diagram showing a conventional liquid crystal display device disclosed in Patent Document 1. In FIG.

  In FIG. 8, 101 is an A / D conversion means, 102 is a PLL means, 103 is a clock phase automatic adjustment means, 104 is a counter, 105 is an image detection means, 106 is a pulse generation means, and 107 is a control means.

  Next, the operation will be described. The input image signal is converted into digital image data by the A / D conversion means 101, and the start position and end position of the image are detected by the image detection means 105. The control means 107 calculates the difference between the start position and the end position of the detected image, obtains the frequency division ratio from the calculation result, and reproduces the dot clock by the PLL means 102.

  Next, the phase of the dot clock is adjusted. In the dot clock phase adjustment, the clock phase automatic adjustment unit 103 detects the phase of the image signal and the dot clock as a voltage. At this time, the detected voltage increases as the phase difference increases. This voltage is sent to the control means 107, and the phase of the clock is adjusted by the PLL means 102 from the control means 107. After the clock phase is adjusted, the image start position is detected again from the image detection means. The start position detection result is sent to the control means 107, and the control means 107 adjusts the position by controlling the pulse generation means from the start position.

As described above, the size, clock phase, and position can all be automatically adjusted by performing automatic size adjustment, automatic clock phase adjustment, and automatic position adjustment in this order.
Japanese Patent Laid-Open No. 11-175033 JP 2000-305503 A

  However, with the conventional technology, the start and end positions of the image cannot be detected correctly unless the image is displayed on the entire effective area or on both ends of the screen, so the dot clock frequency cannot be calculated correctly, and the sampling clock signal There has been a problem that frequency adjustment and phase adjustment of the above cannot be performed.

  The present invention has been made to solve the above-described problems, and the frequency and phase of the dot clock are used even when the image is displayed only in a part of the effective area or in the case of a video signal of a format other than the standard. It is related to the technology that aims to adjust the image correctly and realize the optimal image display state.

  In order to solve the above problems, in the video signal processing apparatus of the present invention, a signal discrimination circuit for discriminating the scanning frequency and effective resolution of the video source from the input synchronization signal, and the input video source into a digital signal in real time. An A / D converter for conversion, a PLL circuit for generating a sampling clock signal for digitizing the video signal from an input synchronization signal, a phase control circuit for controlling the phase of the sampling clock signal, and a phase of the sampling clock And a luminance difference detection circuit between adjacent pixels that detects a luminance difference between adjacent pixels while changing the frequency of the sampling clock according to a method for obtaining the optimal phase distribution state of the sampling clock in each adjacent pixel. , If the image shows only a part of the valid area or a format other than the standard Even when the video signal, it is possible to properly adjust the frequency and phase of the dot clock.

  As described above, according to the present invention, in the video signal processing apparatus, even when the image is displayed only in a part of the effective area or in the case of a video signal of a format other than the standard, erroneous discrimination due to noise is avoided and the dot clock is avoided. It is possible to realize an optimal image display state by correctly adjusting the frequency and phase of the image.

(Embodiment 1)
Hereinafter, an embodiment of the invention described in claim 1 of the present invention will be described with reference to FIGS. 1 to 6. FIG. 6 is an example of a video display system using a liquid crystal projector 13 and is input from a signal source 11. 6 is converted into a digital signal in an optimal sampling state by the front video processing unit 12, and further converted into an optimal signal for the liquid crystal panel by the panel drive unit 9, and then input to the liquid crystal panel 10 as an image as shown in FIG. The image is enlarged and projected on the screen.

  FIG. 1 is a diagram showing the main configuration of the front video processing unit 12 of the projector of FIG. 6, and is a configuration diagram of the video signal processing device according to the first embodiment of the present invention. 2 shows the distribution of the optimum value of the sampling clock phase when the frequency of the sampling clock is the optimum value, FIG. 3 shows the distribution of the optimum value of the sampling clock phase when the frequency of the sampling clock is not the optimum value, and FIG. FIG. 5 is an explanatory diagram of a state where a signal input is sampled with a sampling clock whose frequency is optimal by A / D conversion, and FIG. 5 is an explanatory diagram of a state where the video signal input is sampled by a sampling clock whose frequency is not optimal by A / D conversion. .

  In FIG. 1, a synchronization signal 1 input from a signal source 11 is sent to a signal discrimination circuit 2. The signal discrimination circuit 2 discriminates the scanning frequency and effective resolution of the signal source 11 and sends the signal discrimination result to the microcomputer 3. In the microcomputer 3, the sampling condition determined to be optimal for the signal source from the result of signal discrimination is set in the PLL 7 and the phase control circuit 8 as initial values.

  On the other hand, the video signal 4 is converted into a digital signal by the A / D converter 5, and then used as information on the luminance difference in the adjacent pixel luminance difference detection circuit 6, and is sent to the panel drive unit 9 to be sent to the liquid crystal panel 10. After being converted into a signal form optimal for display, it is output to the liquid crystal panel 10. The image display is optimized from such a state. The optimization of the image display is performed by first optimizing the sampling clock frequency (optimizing the PLL division ratio) and then optimizing the sampling clock phase.

  First, the relationship between the luminance difference between adjacent pixels and the sampling condition will be described with reference to FIG.

  FIG. 4A shows a case where sampling is performed in an optimum phase state using a sampling clock having the same frequency as that generated by the signal source. The luminance at the sampling point 0 is S0, and the sampling point 1 adjacent thereto. If the luminance at S1 is S2, the luminance at sampling point 2 is S2, and the luminance at sampling point 3 is S3, then the luminance difference between adjacent pixels | S0-S1 |, | S1-S2 |, | S2 -S3 | becomes the maximum value at the same sampling clock phase.

 On the other hand, FIG. 4B shows a state in which the sampling phase of the sampling clock is not optimal. In this case, the luminance differences | S0-S1 |, | S1-S2 |, | S2-S3 | Must not.

 5 (a) and 5 (b) both show a state in which the sampling clock frequency is not optimal. In the case of (a), | S2-S3 | has a maximum value at a certain sampling clock phase. S0-S1 | and | S1-S2 | are not maximum values. In FIG. 5B, | S0−S1 | and | S1−S2 | are maximum values at different sampling clock phases from those in FIG. 5A, but | S2−S3 | is not. That is, the luminance between all adjacent pixels does not reach the maximum value at the same sampling clock phase. The same is true for general personal computer images as well as when inputting special test patterns. The difference is the absolute amount when the luminance difference between adjacent pixels reaches the maximum value. Therefore, the frequency of the sampling clock is optimized using this property.

  In FIG. 1, after the microcomputer 3 sets the sampling conditions obtained by signal discrimination in the PLL 7 and the phase control circuit 8, the phase of the sampling clock is controlled by the phase control circuit 8 so that the luminance difference between adjacent pixels becomes the maximum value. Is obtained from the detection result of the luminance difference detection circuit 6 between adjacent pixels. In this case, the variable range of the phase of the sampling clock is considered in one clock cycle in order to make it easy to think. The number of samples of the phase data of the sampling clock is one less than the horizontal effective resolution when considered per line. When the phase data is arranged in the order of detection, if the frequency of the sampling clock is optimum, the phase data converges to a certain value as shown in FIG. This certain value does not exist as an absolute value due to the influence of the delay relationship between the input video signal and the synchronization signal, the horizontal frequency, variations in the video signal processing device, and the like.

  If the frequency of the sampling clock is not optimum, the change is repeated with periodicity without converging to a constant value as shown in FIGS. The amount and direction of phase change at that time vary depending on whether the frequency is shifted from the optimum value or how much the frequency shift is. Therefore, in order to optimize the frequency of the sampling clock, it is only necessary to control the direction in which the phase change is reduced. In the case of this method, since the judgment is made based on the phase characteristics per line, even if image information is partially lost or there is noise in the video signal and noise is detected by sampling, noise is removed and misjudgment occurs. It is possible to avoid another. On the contrary, it is also possible to reduce the number of data samples per line within a range in which the phase characteristics per line can be obtained depending on the situation.

  Next, regarding the optimization of the phase of the sampling clock, the maximum value of the luminance difference between adjacent pixels in the state where the frequency of the sampling clock is optimized, that is, in the state where the optimum value is given to the PLL 7 from the microcomputer 3, ie, The constant in the state of FIG. 2 may be obtained again and a constant value may be given from the microcomputer 3 to the phase control circuit 8. Alternatively, if the absolute value of the constant value in FIG. 2 does not change due to the change of the sampling clock frequency, the maximum value of the luminance difference between adjacent pixels in the state where the sampling clock frequency has already been optimized. That is, since the constant value in the state of FIG. 2 has been obtained, this can be applied to give a constant value to the phase control circuit 8 from the microcomputer 3. Through the above procedure, the dot clock frequency and phase can be adjusted correctly without being affected by noise, even when the image is only displayed in a part of the effective area or in the case of a video signal of a format other than the standard. Is possible.

(Embodiment 2)
Next, an embodiment of the invention described in claim 2 of the present invention will be described with reference to FIGS. However, FIG. 1 is common to the first embodiment, and the description of the components that operate in the same manner as the first embodiment will be omitted.

  In the second embodiment, for optimization of the frequency of the sampling clock, after setting the sampling condition obtained by signal discrimination, the phase of the sampling clock is controlled by the phase control circuit 8, and the sampling in which the luminance difference between adjacent pixels takes the minimum value is performed. The phase of the clock is obtained from the detection result of the luminance difference detection circuit 6 between adjacent pixels. In order to make it easy to consider the variable range of the phase of the sampling clock, it will be considered in one clock cycle as in the first embodiment.

  Also, the maximum number of samples of the phase data of the sampling clock is one less than the horizontal effective resolution when considered per line, as in the first embodiment. In the case where the frequency of the sampling clock is optimum and the case where it is not optimum, the same phase characteristics as in the first embodiment can be obtained even when considering the minimum value of the luminance difference between adjacent pixels. However, the sampling phase value is 180 degrees different from the maximum value. Therefore, the dot clock frequency and phase are correctly adjusted without being affected by noise even when the image is displayed only in a part of the effective area or in the case of a video signal of a format other than the standard as in the first embodiment. It is possible.

(Embodiment 3)
Next, an embodiment of the invention described in claim 3 of the present invention will be described with reference to FIGS. However, FIG. 1 is common to the first embodiment, and the description of the components that operate in the same manner as the first embodiment will be omitted.

  In the third embodiment, for optimization of the frequency of the sampling clock, after setting the sampling condition obtained by signal discrimination, the phase of the sampling clock is controlled by the phase control circuit 8, and the sampling in which the luminance difference between adjacent pixels takes the minimum value is performed. The phase of the clock is obtained from the detection result of the luminance difference detection circuit 6 between adjacent pixels. In order to make it easy to consider the variable range of the phase of the sampling clock, it will be considered in one clock cycle as in the first embodiment.

  Also, the maximum number of samples of the phase data of the sampling clock is one less than the horizontal effective resolution when considered per line, as in the first embodiment. In the case where the frequency of the sampling clock is optimal and the case where the frequency is not optimal, the frequency of the sampling clock and the phase are adjusted using the respective phase characteristics at the maximum value and the minimum value of the luminance difference between adjacent pixels. By using the property that the absolute value of the phase is 180 degrees different between the maximum value and the minimum value, adjustment with higher accuracy is possible. Therefore, the dot clock frequency and phase are correctly adjusted without being affected by noise even when the image is displayed only in a part of the effective area or in the case of a video signal of a format other than the standard as in the first embodiment. It is possible.

(Embodiment 4)
Next, an embodiment of the invention described in claim 4 of the present invention will be described with reference to FIGS. However, FIG. 1 is common to the first embodiment, and the description of the components that operate in the same manner as the first embodiment will be omitted.

  In the fourth embodiment, for sampling clock optimization, after setting a sampling condition obtained by signal discrimination, the phase of the sampling clock is controlled by the phase control circuit 8, and the sampling clock having a minimum luminance difference between adjacent pixels is selected. The phase is obtained from the detection result of the luminance difference detection circuit 6 between adjacent pixels. In order to make it easy to consider the variable range of the phase of the sampling clock, it will be considered in one clock cycle as in the first embodiment. Also, the maximum number of samples of the phase data of the sampling clock is one less than the horizontal effective resolution when considered per line, as in the first embodiment.

  In the case where the frequency of the sampling clock is optimal and the case where the frequency is not optimal, the frequency of the sampling clock and the phase are adjusted using the respective phase characteristics with the maximum value and the minimum value of the luminance difference between adjacent pixels. However, if the dot clock used on the signal source side has insufficient frequency uniformity in one line, the phase characteristics of the sampling clock that takes the maximum and minimum luminance differences between adjacent pixels are optimal. Even if adjustment is performed to show the result, the absolute value of the phase and the horizontal position are continuous as shown in FIGS. 7A and 7B without converging to a constant value as shown in FIG. It converges to binary. In this case, by adding a judgment that the frequency uniformity of the sampling clock used on the signal source side is not sufficient and the adjustment of the clock frequency is an optimum value, the image is in the effective area as in the first embodiment. Even when only a part is displayed or when the video signal has a format other than the standard, the frequency and phase of the dot clock can be correctly adjusted without being affected by noise.

(Embodiment 5)
Next, an embodiment of the invention described in claim 5 of the present invention will be described with reference to FIGS. However, FIG. 1 is common to the first embodiment, and the description of the components that operate in the same manner as the first embodiment will be omitted.

  In the fifth embodiment, with respect to the optimization of the sampling clock, after setting the sampling condition obtained by signal discrimination, the phase of the sampling clock is controlled by the phase control circuit 8, and the sampling clock having the minimum luminance difference between adjacent pixels is selected. The phase is obtained from the detection result of the luminance difference detection circuit 6 between adjacent pixels. In order to make it easy to consider the variable range of the phase of the sampling clock, it will be considered in one clock cycle as in the first embodiment.

  Also, the maximum number of samples of the phase data of the sampling clock is one less than the horizontal effective resolution when considered per line, as in the first embodiment. In the case where the frequency of the sampling clock is optimal and the case where the frequency is not optimal, the frequency of the sampling clock and the phase are adjusted using the respective phase characteristics with the maximum value and the minimum value of the luminance difference between adjacent pixels. However, if the dot clock reproduced on the signal processing device side is not sufficiently uniform in frequency in one line, the phase characteristics of the sampling clock that takes the maximum value and the minimum value of the luminance difference between adjacent pixels are optimum results. Even if the adjustment is performed as shown in FIG. 7, as in the fourth embodiment, the phase does not converge to a constant value as shown in FIG. 2, and the absolute value of the phase and the horizontal value as shown in FIGS. The direction position converges to a continuous binary value. In this case, by adding a judgment that the uniformity of the frequency of the sampling clock reproduced on the signal processing device side is not sufficient and the adjustment of the clock frequency is an optimum value, the image is a part of the effective area as in the first embodiment. Even when only the image is displayed or in the case of a video signal of a format other than the standard, it is possible to correctly adjust the frequency and phase of the dot clock without being affected by noise.

(Embodiment 6)
Next, an embodiment of the invention described in claim 6 of the present invention will be described with reference to FIGS. However, FIG. 1 is common to the first embodiment, and the description of the components that operate in the same manner as the first embodiment will be omitted.

  In the sixth embodiment, for the optimization of the sampling clock, after setting the sampling condition obtained by signal discrimination, the phase of the sampling clock is controlled by the phase control circuit 8, and the sampling clock having the minimum luminance difference between adjacent pixels is selected. The phase is obtained from the detection result of the luminance difference detection circuit 6 between adjacent pixels. In order to make it easy to consider the variable range of the phase of the sampling clock, it will be considered in one clock cycle as in the first embodiment. Also, the maximum number of samples of the phase data of the sampling clock is one less than the horizontal effective resolution when considered per line, as in the first embodiment.

  In the case where the frequency of the sampling clock is optimal and the case where the frequency is not optimal, the frequency of the sampling clock and the phase are adjusted using the respective phase characteristics with the maximum value and the minimum value of the luminance difference between adjacent pixels. However, if there is a difference between the frequency uniformity in one line of the dot clock used on the video source side and the frequency uniformity in one line of the dot clock reproduced on the video processing device side, As shown in FIG. 2, the phase characteristics of the sampling clock that takes the maximum value and the minimum value of the luminance difference between adjacent pixels are adjusted as shown in FIG. Instead of converging to a constant value, as shown in FIGS. 7A and 7B, the absolute value of the phase and the position in the horizontal direction converge to two continuous values. In this case, by adding a judgment that the uniformity of the frequency of the sampling clock reproduced on the signal processing device side is not sufficient and the adjustment of the clock frequency is an optimum value, the image is a part of the effective area as in the first embodiment. Even when only the image is displayed or in the case of a video signal of a format other than the standard, it is possible to correctly adjust the frequency and phase of the dot clock without being affected by noise.

  The video signal processing apparatus according to the present invention avoids erroneous discrimination due to noise and corrects the frequency and phase of the dot clock even when the image is displayed only in a part of the effective area or when the video signal has a format other than the standard. This is useful because it has an effect of realizing an optimal image display state by adjusting.

Configuration diagram of video signal processing apparatus according to Embodiment 1 of the present invention Explanatory diagram of the distribution of phase values when the sampling clock frequency is optimal in the first embodiment of the present invention Explanatory diagram of the distribution of phase values when the sampling clock frequency is not optimal in the first embodiment of the present invention Explanatory diagram of video signal input and sampling clock in A / D converter when sampling clock frequency is optimal in embodiment 1 of the present invention Explanatory drawing of video signal input and sampling clock in A / D converter when sampling clock frequency is not optimum in Embodiment 1 of the present invention 1 is a configuration diagram of a video signal processing system according to Embodiment 1 of the present invention. Explanatory diagram of the distribution of phase values when the dot clock used on the signal source side in Embodiment 4 of the present invention is not sufficiently uniform in frequency per line and the sampling clock frequency is optimal. The figure which shows the conventional image display apparatus

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Synchronization signal input 2 Signal discrimination circuit 3 Microcomputer 4 Video signal input 5 A / D converter 6 Brightness difference detection circuit between adjacent pixels 7 PLL
8 Phase control circuit 9 Panel drive unit 10 Liquid crystal panel 11 Signal source 12 Front image processing unit 13 Liquid crystal projector 14 Screen

Claims (3)

A signal discriminating circuit for discriminating the scanning frequency and effective resolution of the video source from the input synchronization signal;
An A / D converter that converts the input video source into a digital signal in real time;
A PLL circuit that generates a sampling clock that can be varied to an arbitrary frequency in order to digitize the video signal from an input synchronization signal;
A phase control circuit for controlling the phase of the sampling clock signal;
A luminance difference detection circuit between adjacent pixels that detects a luminance difference between adjacent pixels while changing the phase of the sampling clock;
With
Wherein detection by the luminance difference detection circuit between adjacent pixels results, based on the distribution of the sampling clock phase data luminance difference is the maximum value between adjacent pixels, and controls the PLL circuit and the phase control circuit, a sampling clock A video signal processing apparatus characterized by obtaining an optimum value of frequency. A signal discriminating circuit for discriminating the scanning frequency and effective resolution of the video source from the input synchronization signal;
An A / D converter that converts the input video source into a digital signal in real time;
A PLL circuit that generates a sampling clock that can be varied to an arbitrary frequency in order to digitize the video signal from an input synchronization signal;
A phase control circuit for controlling the phase of the sampling clock signal;
A luminance difference detection circuit between adjacent pixels that detects a luminance difference between adjacent pixels while changing the phase of the sampling clock;
With
Wherein detection by the luminance difference detection circuit between adjacent pixels results, based on the distribution of the sampling clock phase data luminance difference is the minimum value between adjacent pixels, and controls the PLL circuit and the phase control circuit, a sampling clock A video signal processing apparatus characterized by obtaining an optimum value of frequency. A signal discriminating circuit for discriminating the scanning frequency and effective resolution of the video source from the input synchronization signal;
An A / D converter that converts the input video source into a digital signal in real time;
A PLL circuit that generates a sampling clock that can be varied to an arbitrary frequency in order to digitize the video signal from an input synchronization signal;
A phase control circuit for controlling the phase of the sampling clock signal;
A luminance difference detection circuit between adjacent pixels that detects a luminance difference between adjacent pixels while changing the phase of the sampling clock;
With
As a result of detection by the luminance difference detection circuit between adjacent pixels , the sampling clock phase data distribution in which the luminance difference between adjacent pixels becomes the maximum value and the minimum value is used together to control the PLL circuit and the phase control circuit. Te, a video signal processing apparatus characterized by determining the optimal value of the sampling clock frequency.

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